JP5837783B2 - 半導体集積回路装置 - Google Patents
半導体集積回路装置 Download PDFInfo
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- JP5837783B2 JP5837783B2 JP2011195707A JP2011195707A JP5837783B2 JP 5837783 B2 JP5837783 B2 JP 5837783B2 JP 2011195707 A JP2011195707 A JP 2011195707A JP 2011195707 A JP2011195707 A JP 2011195707A JP 5837783 B2 JP5837783 B2 JP 5837783B2
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Description
先ず、本願において開示される発明の代表的な実施の形態について概要を説明する。
(a)第1の主面を有する半導体基板;
(b)前記半導体基板の前記第1の主面に設けられた複数のMISFET;
(c)前記半導体基板の前記第1の主面および前記複数のMISFETの上方に設けられた埋め込み型多層配線層;
(d)前記埋め込み型多層配線層上に設けられた非埋め込み型アルミニウム系パッドメタル層;
(e)前記非埋め込み型アルミニウム系パッドメタル層の一部として設けられた複数のメタルボンディングパッド;
(f)前記非埋め込み型アルミニウム系パッドメタル層よりも上層に形成されたファイナルパッシベーション膜;
(g)前記複数のメタルボンディングパッドの各々の上方の前記ファイナルパッシベーション膜に設けられたパッド開口、
ここで、前記非埋め込み型アルミニウム系パッドメタル層は、実質的に電源リング配線を有しない。
(h)前記埋め込み型多層配線層の内の埋め込み型最上層配線層の一部として設けられた電源リング配線。
(i)前記電源リング配線内に設けられたディッシング防止用スリット。
(j)前記複数のメタルボンディングパッドの各々の下方に、前記埋め込み型最上層配線層の一部として設けられ、その上方のメタルボンディングパッドと形状および面積がほぼ同様の下地メタルパッド。
(k)前記複数のメタルボンディングパッドの各々と、その下方の下地メタルパッドとの間に設けられた単一のスルーホール。
(k)前記複数のメタルボンディングパッドの各々と、その下方の下地メタルパッドとの間に設けられた複数のスルーホール。
(m)前記第1の主面の内部領域に、前記非埋め込み型アルミニウム系パッドメタル層の一部として、ほぼ均一に分布するように設けられた多数の占有率調整用ダミーパターン。
(n)前記第1の主面の外周に沿って、前記非埋め込み型アルミニウム系パッドメタル層の一部として、アルミニウム系シールリング。
(p)前記複数のメタルボンディングパッドの各々の上面に接続されたボンディングワイヤ。
(q)前記ファイナルパッシベーション膜上を被う封止樹脂層。
1.本願において、実施の態様の記載は、必要に応じて、便宜上複数のセクションに分けて記載する場合もあるが、特にそうでない旨明示した場合を除き、これらは相互に独立別個のものではなく、単一の例の各部分、一方が他方の一部詳細または一部または全部の変形例等である。また、原則として、同様の部分は繰り返しを省略する。また、実施の態様における各構成要素は、特にそうでない旨明示した場合、理論的にその数に限定される場合および文脈から明らかにそうでない場合を除き、必須のものではない。
実施の形態について更に詳述する。各図中において、同一または同様の部分は同一または類似の記号または参照番号で示し、説明は原則として繰り返さない。
このセクションでは、本願の一実施の形態の半導体集積回路装置の構造をメタル配線システム全体から概説する。
このセクションでは、本願の前記一実施の形態の半導体集積回路装置の構造等を非埋め込み型アルミニウム系パッドメタル層および埋め込み型第9配線層(埋め込み型最上層配線層)の平面レイアウト等を中心に説明する。
このセクションでは、本願の前記一実施の形態の半導体集積回路装置の構造等をその要部デバイス構造を中心に説明する。ここで、通常、下地メタルパッドは、例えば図8に示すように、その直下でビアを介して下層の配線に接続されるか、一体となった同層の配線を介して下層の配線等に接続されているが、図9および図10(図19および図20に於いても同じ)においては、図示が煩雑になるので、これらのビアおよび一体となった同層の配線は図示しない。
このセクションでは、セクション1から3の主要なデバイス構造に対する製造方法の一例を示すが、前記構造は、以下に示す以外の製法によっても構成できることは言うまでもない。
このセクションでは、セクション3(図9および図10)で説明したパッド周辺構造(「単一スルーホール接続」という)の変形例の一例を示す。このセクションの方式を「スルーホールリング接続」という。
このセクションでは、図3に示した占有率調整用ダミーパターンの一つの変形例を説明するとともに、これをMIMキャパシタとして利用する可能性を説明する。すなわち、占有率調整用ダミーパターンは、図3や図21に示すものばかりでなく、一定の占有率を均一に達成できるものであれば、種々変形可能である。また、他の素子としての利用も、キャパシタに限らず、インダクタンス、アンテナ、抵抗素子、その他としても可能である。
このセクションでは、前記各実施の形態(変形例を含む)に関する予備的説明および一般的考察を行う。
以上本発明者によってなされた発明を実施形態に基づいて具体的に説明したが、本発明はそれに限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能であることは言うまでもない。
1a 基板又はウエハのデバイス面(第1の主面)
1b 基板又はウエハの裏面(第2の主面)
1s 基板又はウエハのP型単結晶シリコン基板部
2 半導体基板又は集積回路チップ(半導体チップ領域)
3 タングステンプラグ
4 窒化シリコンライナー膜(エッチストップ膜)
5 プリメタル層間絶縁膜
6,6x,6y アルミニウム系ボンディングパッド
6a アルミニウム系主ボンディングパッド膜
6b 窒化チタン系パッドバリアメタル膜
7 (ファイナルパッシベーション膜の)パッド開口
8 ゲート電極
9 パッド層層間絶縁膜
9a プラズマTEOS系主層間絶縁膜
9b SiN系絶縁性バリア膜
10 素子分離フィールド絶縁膜
11 ファイナルパッシベーション膜
11a USG系ファイナルパッシベーション膜
11b SiN系ファイナルパッシベーション膜
12,12x,12y 下地メタルパッド
13 埋め込まれた銅配線
14 SiC系絶縁性バリア膜
15 プラズマTEOS系主層間絶縁膜
16 埋め込み配線最上層層間絶縁膜(グローバル配線層層間絶縁膜)
18 セミグローバル上層配線層層間絶縁膜
19 セミグローバル下層配線層層間絶縁膜
20a アルミニウム系シールリング
20b 銅系シールリング
21 ローカル最上層配線層層間絶縁膜
22a アルミニウム系パッドリング
22b 銅系パッドリング
23 銅埋め込み配線
24 SiC系絶縁性バリア膜
25 SiOC系主層間絶縁膜
26 チップ内部回路形成領域
27 ダイシング領域(スクライブ領域)
28 占有率調整用ダミーパターン
29a アルミニウム系TEGパターン
29b 銅系TEGパターン
30a アルミニウム系レーザートリム用位置決め基準パターン
31a アルミニウム系膜厚モニタ
31b 銅系膜厚モニタ
32a アルミニウム系露光用アライメントパターン
32b 銅系露光用アライメントパターン
33 銅埋め込み配線
34 SiC系絶縁性バリア膜
35 SiOC系主層間絶縁膜
36 電源リング(電源幹配線)
36d Vddリング(電源供給リング)
36g Vssリング(接地リング)
37 スリット
38 同層メタル櫛形MIMキャパシタ
39,39x,39y パッドコンタクト用スルーホール
40 ボンディングワイヤ
40b ボンディングボール
41 スルーホールリング
42 封止樹脂(封止樹脂層)
43 銅埋め込み配線
44 SiC系絶縁性バリア膜
45 SiOC系主層間絶縁膜
53 銅埋め込み配線
54 SiC系絶縁性バリア膜
55 SiOC系主層間絶縁膜
63 銅埋め込み配線
63a 埋め込み型第6配線層銅系メタル膜
63b 窒化タンタル系バリアメタル膜
64 SiC系絶縁性バリア膜
65 SiOC系主層間絶縁膜
73 第7層銅埋め込み配線
74 SiC系絶縁性バリア膜
75a プラズマTEOS系主層間絶縁膜
75b FSG系主層間絶縁膜
75c プラズマTEOS系キャップ膜
83 第8層銅埋め込み配線
84 SiC系絶縁性バリア膜
85a プラズマTEOS系主層間絶縁膜
85b FSG系主層間絶縁膜
85c プラズマTEOS系キャップ膜
93,93x,93y 最上層銅埋め込み配線等(配線、ビア等)
93a 最上層銅埋め込み配線銅系メタル膜
93b 窒化タンタル系バリアメタル膜
94a SiN系絶縁性バリア膜
94b SiC系絶縁性バリア膜
95a プラズマTEOS系主層間絶縁膜
95b プラズマTEOS系主層間絶縁膜
AP 非埋め込み型アルミニウム系パッドメタル層
CM 中層銅埋め込み配線等(配線、ビア等)
CML 中層および下層銅埋め込み配線等(配線、ビア等)
CL 下層銅埋め込み配線等(配線、ビア等)
DW 埋め込み型多層配線層
ILD 埋め込み型多層配線層層間絶縁膜
M1 埋め込み型第1配線層
M2 埋め込み型第2配線層
M3 埋め込み型第3配線層
M4 埋め込み型第4配線層
M5 埋め込み型第5配線層
M6 埋め込み型第6配線層
M7 埋め込み型第7配線層
M8 埋め込み型第8配線層
M9 埋め込み型第9配線層(埋め込み型最上層配線層)
NSD N型ソースドレイン領域
NW N型ウエル領域
PM プリメタル領域
PSD P型ソースドレイン領域
PW P型ウエル領域
Qn Nチャネル型MISFET
Qp Pチャネル型MISFET
R1 Vssリング切り出し領域
Claims (14)
- 以下を含む半導体集積回路装置:
(a)第1の主面を有する半導体基板;
(b)前記半導体基板の前記第1の主面に設けられた複数のMISFET;
(c)前記半導体基板の前記第1の主面および前記複数のMISFETの上方に設けられた埋め込み型多層配線層;
(d)前記埋め込み型多層配線層上に設けられた非埋め込み型アルミニウム系パッドメタル層;
(e)前記非埋め込み型アルミニウム系パッドメタル層の一部として設けられた複数のメタルボンディングパッド;
(f)前記非埋め込み型アルミニウム系パッドメタル層よりも上層に形成されたファイナルパッシベーション膜;
(g)前記複数のメタルボンディングパッドの各々の上方の前記ファイナルパッシベーション膜に設けられたパッド開口;
(h)前記埋め込み型多層配線層の内の埋め込み型最上層配線層の一部として設けられた電源リング配線、
ここで、前記非埋め込み型アルミニウム系パッドメタル層は、実質的に前記電源リング配線を有しない。 - 請求項1に記載の半導体集積回路装置において、更に以下を含む:
(i)前記電源リング配線内に設けられたディッシング防止用スリット。 - 請求項1に記載の半導体集積回路装置において、前記複数のメタルボンディングパッドの各々は、プラグを介することなく、前記埋め込み型最上層配線層に接続されている。
- 請求項3に記載の半導体集積回路装置において、更に以下を含む:
(j)前記複数のメタルボンディングパッドの各々の下方に、前記埋め込み型最上層配線層の一部として設けられ、その上方のメタルボンディングパッドと形状および面積がほぼ同様の下地メタルパッド。 - 請求項4に記載の半導体集積回路装置において、更に以下を含む:
(k)前記複数のメタルボンディングパッドの各々と、その下方の下地メタルパッドとの間に設けられた単一のスルーホール。 - 請求項4に記載の半導体集積回路装置において、更に以下を含む:
(k)前記複数のメタルボンディングパッドの各々と、その下方の下地メタルパッドとの間に設けられた複数のスルーホール。 - 請求項5に記載の半導体集積回路装置において、前記非埋め込み型アルミニウム系パッドメタル層は、実質的に配線を有しない。
- 請求項7に記載の半導体集積回路装置において、更に以下を含む:
(m)前記第1の主面の内部領域に、前記非埋め込み型アルミニウム系パッドメタル層の一部として、ほぼ均一に分布するように設けられた多数の占有率調整用ダミーパターン。 - 請求項8に記載の半導体集積回路装置において、更に以下を含む:
(n)前記第1の主面の外周に沿って、前記非埋め込み型アルミニウム系パッドメタル層の一部として、アルミニウム系シールリング。 - 請求項1に記載の半導体集積回路装置において、前記非埋め込み型アルミニウム系パッドメタル層は、実質的に信号配線を有しない。
- 請求項1に記載の半導体集積回路装置において、更に以下を含む:
(p)前記複数のメタルボンディングパッドの各々の上面に接続されたボンディングワイヤ。 - 請求項10に記載の半導体集積回路装置において、更に以下を含む:
(q)前記ファイナルパッシベーション膜上を被う封止樹脂層。 - 請求項9に記載の半導体集積回路装置において、前記複数のメタルボンディングパッドは、アルミニウム系シールリングに沿うように、その内側に、リング状に配列されている。
- 請求項13に記載の半導体集積回路装置において、前記埋め込み型多層配線層は、銅系埋め込み型多層配線層である。
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JP2011129722A (ja) | 2009-12-17 | 2011-06-30 | Panasonic Corp | 半導体装置 |
JP2011146563A (ja) * | 2010-01-15 | 2011-07-28 | Panasonic Corp | 半導体装置 |
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