JP7353121B2 - 半導体装置および機器 - Google Patents
半導体装置および機器 Download PDFInfo
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- JP7353121B2 JP7353121B2 JP2019185458A JP2019185458A JP7353121B2 JP 7353121 B2 JP7353121 B2 JP 7353121B2 JP 2019185458 A JP2019185458 A JP 2019185458A JP 2019185458 A JP2019185458 A JP 2019185458A JP 7353121 B2 JP7353121 B2 JP 7353121B2
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- 239000004065 semiconductor Substances 0.000 title claims description 199
- 229910052751 metal Inorganic materials 0.000 claims description 65
- 239000002184 metal Substances 0.000 claims description 65
- 238000000034 method Methods 0.000 claims description 8
- 238000006243 chemical reaction Methods 0.000 claims description 7
- 230000003287 optical effect Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 150000003377 silicon compounds Chemical class 0.000 description 6
- 230000007797 corrosion Effects 0.000 description 4
- 238000005260 corrosion Methods 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000003628 erosive effect Effects 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000012447 hatching Effects 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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Description
図1を参照して、本発明の第1の実施形態に係る半導体装置100の構造の例について説明する。図1は、半導体装置100の平面図である。図1は、半導体装置100の一例として光電変換装置(例えば、固体撮像装置)を示す。半導体装置100は、その中央に、複数の画素103が2次元アレイ状に配置された画素領域102を有する。各画素103は、例えばフォトダイオードのような光電変換素子と、トランジスタのようなスイッチ素子とを含んでもよい。
図6を参照して、本発明の第2の実施形態に係る半導体装置600の構造の例について説明する。半導体装置600のうち、半導体装置100と同様の構成要素については重複する説明を省略する。すなわち、別段の記載がない限り、半導体装置100についての上述の説明は半導体装置600に対しても当てはまる。
図8を参照して、本発明の第3の実施形態に係る半導体装置800の構造の例について説明する。半導体装置800のうち、半導体装置100又は600と同様の構成要素については重複する説明を省略する。すなわち、別段の記載がない限り、半導体装置100又は600についての上述の説明は半導体装置800に対しても当てはまる。
上述の第1の実施形態から第3の実施形態は、以下のように一般化できる。半導体装置は、接合面200に交差する面(以下、交差面と呼ぶ)を有する。交差面、第1の実施形態では、接合面200を通る開口104に面する面である。また、交差面は、第2の実施形態では、半導体装置600のエッジ101、または接合面200を通る開口104に面する面である。複数の接合部232のうち、交差面に最も近い接合部を直近接合部と呼ぶ。接合面200において、直近接合部の幅をWdとし、交差面と直近接合部との間の距離をDfdとし、複数の接合部232のうち隣り合う2つの接合部の間隔をSdとすると、Wd<Dfdおよび/またはDfd<3×(Wd+Sd)を満たす。Wd+Sd≦Dfdを満たしてもよく、Dfd≦2×(Wd+Sd)を満たしてもよい。Dfdは、第1の実施形態ではDodに一致(Dfd=Dod)し、第2の実施形態ではDod又はDedに一致(Dfd=DodまたはDed)する。また、絶縁層の一部を介して互いに対向する2つ交差面の間の距離をDffとすると、Dfd<Dffを満たしうる。Dffは、第1の実施形態ではDooに一致(Dff=Doo)し、第2の実施形態ではDoeに一致(Dff=Doe)する。第1の実施形態に示した図3にはエッジ101とエッジ101への直近接合部との距離Dfdを記載しており、エッジ101とエッジ101への直近接合部との関係において、Wd<Dfdを満たし、さらに、Dfd<Dff(Dfd<Doe)を満たす。第2の実施形態においては、エッジ101とエッジ101への直近接合部との関係において、Wd<Dfdを満たし、Dfd<Dffを満たし、さらに、Dfd<3×(Wd+Sd)を満たす。
以下、図9が示す、半導体装置930を備える機器9191について詳細に説明する。半導体装置930は、上述の半導体装置100、600および800のいずれかであってもよい。半導体装置930は、半導体デバイス910と、半導体デバイス910を収容するパッケージ920を含むことができる。パッケージ920は、半導体デバイス910が固定された基体と、半導体デバイス910に対向するガラスなどの蓋体と、を含むことができる。パッケージ920は、さらに、基体に設けられた端子と半導体デバイス910に設けられた端子(ボンディングパッド201a、201b)とを接続するボンディングワイヤやバンプなどの接合部材を含むことができる。
Claims (21)
- 半導体装置であって、
第1の絶縁層と、前記第1の絶縁層の第1の面に設けられた凹部に埋め込まれた複数の第1の金属パッドとを有する第1の半導体部品と、
第2の絶縁層と、前記第2の絶縁層の第2の面に設けられた凹部に埋め込まれた複数の第2の金属パッドとを有する第2の半導体部品と、を備え、
前記第1の半導体部品と前記第2の半導体部品とは、前記第1の面と前記第2の面とが対向するように互いに積層されており、
前記複数の第1の金属パッドの各々と前記複数の第2の金属パッドの各々とが互いに接合することによって複数の接合部が形成されており、
前記半導体装置に、前記第1の絶縁層と前記第2の絶縁層との間の接合面を通る第1の開口および第2の開口が形成されており、
前記半導体装置は、前記複数の接合部を取り囲むエッジを有し、
前記第1の開口と前記第2の開口とは、前記半導体装置のエッジに沿って並んでおり、
前記複数の接合部は、前記第1の開口と前記第2の開口との間にある第1の接合部を含み、前記エッジに平行な方向において前記第1の接合部と前記第1の開口との間には前記複数の接合部のいずれも位置せず、
前記接合面において、前記エッジに平行な方向における前記第1の接合部の幅をWdとし、前記エッジに平行な方向における前記第1の開口の幅をWoとし、前記第1の開口と前記第2の開口との間の距離をDooとし、前記第1の開口と前記第1の接合部との間の距離をDodとし、前記第1の開口と前記エッジとの間の距離をDoeとすると、
Doo<2×Wo、Doe<2×Wo、かつDod>Wd
を満たすことを特徴とする半導体装置。 - 前記接合面において、前記複数の接合部のうち前記エッジに平行な方向において前記第1の接合部に隣り合う別の接合部と前記第1の接合部との間隔をSdとすると、Doo>10×(Wd+Sd)をさらに満たすことを特徴とする請求項1に記載の半導体装置。
- 前記接合面において、前記複数の接合部のうち前記第1の接合部に隣り合う別の接合部と前記第1の接合部との間隔をSdとすると、Dod<3×(Wd+Sd)をさらに満たすことを特徴とする請求項1または2に記載の半導体装置。
- Dod<Doo/4をさらに満たすことを特徴とする請求項1乃至3のいずれか1項に記載の半導体装置。
- 前記複数の接合部は、前記第1の開口と前記第2の開口との間において、前記第1の開口と前記第2の開口とを結ぶ方向に沿って並ぶ5個以上の接合部を含むことを特徴とする請求項1乃至4のいずれか1項に記載の半導体装置。
- 前記第1の接合部は、前記複数の接合部のうちで前記第1の開口と前記第2の開口との間において前記第1の開口に最も近い接合部であることを特徴とする請求項1乃至5のいずれか1項に記載の半導体装置。
- 前記複数の接合部は、前記第1の開口と前記第2の開口との間にある第2の接合部を含み、前記第2の接合部と前記第2の開口との間には前記複数の接合部のいずれも位置せず、
前記接合面において、前記エッジに平行な方向における前記第2の接合部の幅をWd’とし、前記エッジに平行な方向における前記第2の開口の幅をWo’とし、前記第2の開口と前記第2の接合部との間の距離をDod’とし、前記第2の開口と前記エッジとの間の距離をDoe’とすると、
Doo<2×Wo’、Doe’<2×Wo’、かつDod’>Wd’
を満たすことを特徴とする請求項1乃至6のいずれか1項に記載の半導体装置。 - 前記第2の接合部は、前記複数の接合部のうちで前記第1の開口と前記第2の開口との間において前記第2の開口に最も近い接合部であることを特徴とする請求項7に記載の半導体装置。
- Wo<Dooをさらに満たすことを特徴とする請求項1乃至8のいずれか1項に記載の半導体装置。
- 前記接合面において、前記複数の接合部のうちの1つの接合部の前記エッジに垂直な方向における幅をWd”とし、前記エッジと前記1つの接合部との間の距離をDfdとすると、
Wd”<Dfd
を満たすことを特徴とする請求項1乃至9のいずれか1項に記載の半導体装置。 - 半導体装置であって、
第1の絶縁層と、前記第1の絶縁層の第1の面に設けられた凹部に埋め込まれた複数の第1の金属パッドとを有する第1の半導体部品と、
第2の絶縁層と、前記第2の絶縁層の第2の面に設けられた凹部に埋め込まれた複数の第2の金属パッドとを有する第2の半導体部品と、を備え、
前記第1の半導体部品と前記第2の半導体部品とは、前記第1の面と前記第2の面とが対向するように互いに積層されており、
前記複数の第1の金属パッドの各々と前記複数の第2の金属パッドの各々とが互いに接合することによって複数の接合部が形成されており、
前記半導体装置に、前記第1の絶縁層と前記第2の絶縁層との間の接合面を通る開口が形成されており、
前記半導体装置は、前記複数の接合部を取り囲むエッジを有し、
前記複数の接合部は、前記開口と前記エッジとの間にある第1の接合部を含み、前記エッジに垂直な方向において前記第1の接合部と前記開口との間には前記複数の接合部のいずれも位置せず、
前記接合面において、前記エッジに垂直な方向における前記第1の接合部の幅をWdとし、前記エッジに垂直な方向における前記開口の幅をWoとし、前記開口と前記エッジとの間の距離をDoeとし、前記開口と前記第1の接合部との間の距離をDodとすると、
Doe<2×WoかつDod>Wd
を満たすことを特徴とする半導体装置。 - 前記接合面において、前記複数の接合部のうち前記第1の接合部に隣り合う別の接合部と前記第1の接合部との間隔をSdとすると、Doe>10×(Wd+Sd)をさらに満たすことを特徴とする請求項11に記載の半導体装置。
- 前記接合面において、前記複数の接合部のうち前記エッジに垂直な方向において前記第1の接合部に隣り合う別の接合部と前記第1の接合部との間隔をSdとすると、Dod<3×(Wd+Sd)をさらに満たすことを特徴とする請求項11または12に記載の半導体装置。
- Dod<Doe/4を満たすことを特徴とする請求項11乃至13のいずれか1項に記載の半導体装置。
- 前記複数の接合部は、前記開口と前記エッジとの間において、前記開口と前記エッジとを結ぶ方向に沿って並ぶ5個以上の接合部を含むことを特徴とする請求項11乃至14のいずれか1項に記載の半導体装置。
- 前記第1の接合部は、前記複数の接合部のうちで前記開口と前記エッジとの間において前記開口に最も近い接合部であることを特徴とする請求項11乃至15のいずれか1項に記載の半導体装置。
- 前記複数の接合部は、前記開口と前記エッジとの間にある第2の接合部を含み、前記第2の接合部と前記エッジとの間には前記複数の接合部のいずれも位置せず、
前記接合面において、前記エッジに垂直な方向における前記第2の接合部の幅をWd’とし、前記エッジと前記第2の接合部との間の距離をDedとし、前記複数の接合部のうちで前記第2の接合部に隣り合う接合部と前記第2の接合部との間隔をSd’とすると、
Ded<3×(Wd’+Sd’)
をさらに満たすことを特徴とする請求項11乃至15のいずれか1項に記載の半導体装置。 - Wd2/(Wd+Sd)2<0.3をさらに満たすことを特徴とする請求項2、3、12および13の何れか1項に記載の半導体装置。
- 50μm≦Wo≦200μm、および、1μm≦Wd≦10μmをさらに満たすことを特徴とする請求項1乃至18の何れか1項に記載の半導体装置。
- 前記半導体装置は光電変換装置であることを特徴とする請求項1乃至19の何れか1項に記載の半導体装置。
- 請求項1乃至20のいずれか1項に記載の半導体装置と、
前記半導体装置に対応する光学装置、
前記半導体装置を制御する制御装置、
前記半導体装置から得られた情報を処理する処理装置、
前記半導体装置から得られた情報を表示する表示装置、
前記半導体装置から得られた情報を記憶する記憶装置、および
前記半導体装置から得られた情報に基づいて動作する機械装置、
の6つのうちの少なくともいずれかと、を備える機器。
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Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011035413A (ja) | 1997-03-31 | 2011-02-17 | Renesas Electronics Corp | 半導体集積回路装置 |
JP2012019147A (ja) | 2010-07-09 | 2012-01-26 | Canon Inc | 固体撮像装置 |
JP2012033894A (ja) | 2010-06-30 | 2012-02-16 | Canon Inc | 固体撮像装置 |
JP2012256736A (ja) | 2011-06-09 | 2012-12-27 | Sony Corp | 半導体装置 |
JP2014072297A (ja) | 2012-09-28 | 2014-04-21 | Canon Inc | 半導体装置およびその製造方法 |
WO2015050000A1 (ja) | 2013-10-04 | 2015-04-09 | ソニー株式会社 | 半導体装置および固体撮像素子 |
JP2018073851A (ja) | 2016-10-24 | 2018-05-10 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置、製造方法、及び、固体撮像装置 |
JP2019153675A (ja) | 2018-03-02 | 2019-09-12 | ルネサスエレクトロニクス株式会社 | 固体撮像装置およびその製造方法 |
Family Cites Families (44)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR0155874B1 (ko) | 1995-08-31 | 1998-12-01 | 김광호 | 반도체장치의 평탄화방법 및 이를 이용한 소자분리방법 |
JP3638778B2 (ja) | 1997-03-31 | 2005-04-13 | 株式会社ルネサステクノロジ | 半導体集積回路装置およびその製造方法 |
JP3425582B2 (ja) | 2000-04-14 | 2003-07-14 | Necエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
JP3719650B2 (ja) | 2000-12-22 | 2005-11-24 | 松下電器産業株式会社 | 半導体装置 |
JP2002198419A (ja) | 2000-12-26 | 2002-07-12 | Nec Corp | 半導体装置の製造方法、半導体装置の設計方法 |
US6617663B2 (en) | 2001-03-05 | 2003-09-09 | Seiko Epson Corporation | Methods of manufacturing semiconductor devices |
US6638863B2 (en) | 2001-04-24 | 2003-10-28 | Acm Research, Inc. | Electropolishing metal layers on wafers having trenches or vias with dummy structures |
JP2003224098A (ja) | 2002-01-30 | 2003-08-08 | Semiconductor Leading Edge Technologies Inc | 配線の設計方法、プログラムおよびそのプログラムを記録した記録媒体 |
CA2479873A1 (en) | 2002-04-12 | 2003-10-23 | Acm Research, Inc. | Electropolishing and electroplating methods |
JP3536104B2 (ja) | 2002-04-26 | 2004-06-07 | 沖電気工業株式会社 | 半導体装置の製造方法 |
JP2004153015A (ja) | 2002-10-30 | 2004-05-27 | Fujitsu Ltd | 半導体装置及びその製造方法 |
KR20040093277A (ko) * | 2003-04-29 | 2004-11-05 | 매그나칩 반도체 유한회사 | 버팅콘택을 포함하여 구성된 퓨즈를 구비한 시모스이미지센서 및 이를 이용한 퓨즈 리페어 방법 |
WO2004097916A1 (ja) | 2003-04-30 | 2004-11-11 | Fujitsu Limited | 半導体装置の製造方法、半導体ウエハおよび半導体装置 |
KR100546354B1 (ko) | 2003-07-28 | 2006-01-26 | 삼성전자주식회사 | 원하는 분석 위치를 용이하게 찾을 수 있는 반도체 소자 |
JP4615846B2 (ja) | 2003-11-14 | 2011-01-19 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP4191110B2 (ja) | 2004-07-26 | 2008-12-03 | Necエレクトロニクス株式会社 | 半導体装置 |
JP2006165040A (ja) | 2004-12-02 | 2006-06-22 | Renesas Technology Corp | 半導体装置及び半導体装置のパターン設計方法 |
JP2006339406A (ja) | 2005-06-02 | 2006-12-14 | Renesas Technology Corp | 半導体装置 |
JP2007250705A (ja) | 2006-03-15 | 2007-09-27 | Nec Electronics Corp | 半導体集積回路装置及びダミーパターンの配置方法 |
JP2007251070A (ja) * | 2006-03-18 | 2007-09-27 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2007294783A (ja) | 2006-04-27 | 2007-11-08 | Renesas Technology Corp | 半導体装置の製造方法および半導体装置の設計支援システム |
JP4705881B2 (ja) * | 2006-05-09 | 2011-06-22 | パナソニック株式会社 | リードフレーム及びそれを用いた半導体装置 |
JP4916241B2 (ja) * | 2006-07-28 | 2012-04-11 | パナソニック株式会社 | 半導体装置及びその製造方法 |
JP2008041984A (ja) | 2006-08-08 | 2008-02-21 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2009147150A (ja) | 2007-12-14 | 2009-07-02 | Nec Electronics Corp | 半導体装置 |
JP5356742B2 (ja) | 2008-07-10 | 2013-12-04 | ラピスセミコンダクタ株式会社 | 半導体装置、半導体装置の製造方法および半導体パッケージの製造方法 |
JP2010287638A (ja) | 2009-06-10 | 2010-12-24 | Sony Corp | 固体撮像装置とその製造方法および撮像装置 |
JP5497392B2 (ja) * | 2009-09-25 | 2014-05-21 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2011243612A (ja) * | 2010-05-14 | 2011-12-01 | Sony Corp | 半導体装置及びその製造方法並びに電子機器 |
JP6342033B2 (ja) | 2010-06-30 | 2018-06-13 | キヤノン株式会社 | 固体撮像装置 |
JP5553693B2 (ja) | 2010-06-30 | 2014-07-16 | キヤノン株式会社 | 固体撮像装置及び撮像システム |
JP5843475B2 (ja) | 2010-06-30 | 2016-01-13 | キヤノン株式会社 | 固体撮像装置および固体撮像装置の製造方法 |
JP5693060B2 (ja) | 2010-06-30 | 2015-04-01 | キヤノン株式会社 | 固体撮像装置、及び撮像システム |
JP5517800B2 (ja) * | 2010-07-09 | 2014-06-11 | キヤノン株式会社 | 固体撮像装置用の部材および固体撮像装置の製造方法 |
WO2012161044A1 (ja) | 2011-05-24 | 2012-11-29 | ソニー株式会社 | 半導体装置 |
JP5837783B2 (ja) | 2011-09-08 | 2015-12-24 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置 |
JP5925711B2 (ja) | 2013-02-20 | 2016-05-25 | 浜松ホトニクス株式会社 | 検出器、pet装置及びx線ct装置 |
JP6329059B2 (ja) * | 2014-11-07 | 2018-05-23 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP7058479B2 (ja) | 2016-10-18 | 2022-04-22 | ソニーセミコンダクタソリューションズ株式会社 | 光検出器 |
US11127773B2 (en) * | 2017-04-04 | 2021-09-21 | Sony Semiconductor Solutions Corporation | Semiconductor device, method of manufacturing semiconductor device, and electronic apparatus |
JP7037547B2 (ja) * | 2017-04-04 | 2022-03-16 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置、半導体装置の製造方法、及び電子機器 |
JP2019114595A (ja) | 2017-12-21 | 2019-07-11 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置およびその製造方法 |
JP2019140237A (ja) | 2018-02-09 | 2019-08-22 | キヤノン株式会社 | 光電変換装置および撮像システム |
CN108511475B (zh) * | 2018-05-17 | 2023-10-10 | 黄琴 | 一种超小型pad的辅助焊接元件的制造方法和辅助焊接方法 |
-
2019
- 2019-10-08 JP JP2019185458A patent/JP7353121B2/ja active Active
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- 2020-09-29 CN CN202011049822.0A patent/CN112635501B/zh active Active
- 2020-09-30 US US17/038,177 patent/US11342293B2/en active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011035413A (ja) | 1997-03-31 | 2011-02-17 | Renesas Electronics Corp | 半導体集積回路装置 |
JP2012033894A (ja) | 2010-06-30 | 2012-02-16 | Canon Inc | 固体撮像装置 |
JP2012019147A (ja) | 2010-07-09 | 2012-01-26 | Canon Inc | 固体撮像装置 |
JP2012256736A (ja) | 2011-06-09 | 2012-12-27 | Sony Corp | 半導体装置 |
JP2014072297A (ja) | 2012-09-28 | 2014-04-21 | Canon Inc | 半導体装置およびその製造方法 |
WO2015050000A1 (ja) | 2013-10-04 | 2015-04-09 | ソニー株式会社 | 半導体装置および固体撮像素子 |
JP2018073851A (ja) | 2016-10-24 | 2018-05-10 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置、製造方法、及び、固体撮像装置 |
JP2019153675A (ja) | 2018-03-02 | 2019-09-12 | ルネサスエレクトロニクス株式会社 | 固体撮像装置およびその製造方法 |
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