JP5356742B2 - 半導体装置、半導体装置の製造方法および半導体パッケージの製造方法 - Google Patents
半導体装置、半導体装置の製造方法および半導体パッケージの製造方法 Download PDFInfo
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Description
11 STI領域
12 絶縁膜
13 電極パッド
18 絶縁膜
20 貫通電極
21 貫通孔
22 バリアメタル
23 めっきシード膜
24 めっき膜
25 裏面配線
30 能動素子
100 フィールド領域
200〜205 ダミーアクティブ
Claims (7)
- 複数の能動素子が形成されているアクティブ領域と、前記アクティブ領域以外のフィールド領域とを有する半導体基板と、前記能動素子のいずれかに電気的に接続された少なくとも1つの電極パッドと、前記半導体基板の裏面から前記フィールド領域を貫通して形成されるとともに前記電極パッドに電気的に接続された少なくとも1つの貫通電極と、を有する半導体装置であって、
前記フィールド領域は、前記半導体基板に絶縁膜を形成することにより得られる絶縁領域と前記絶縁領域内に前記半導体基板の基材を残すことにより得られるダミー部とを有し、前記貫通電極の外縁が前記絶縁領域と前記ダミー部との界面と交差しておらず、前記フィールド領域には、前記貫通電極がよぎる領域の外側にのみ前記ダミー部が設けられていることを特徴とする半導体装置。 - 前記貫通電極がよぎる領域を囲むリング状のダミー部を更に有することを特徴とする請求項1に記載の半導体装置。
- 前記ダミー部は、前記絶縁領域内に均一に配置された複数の島状ダミー部を含むことを特徴とする請求項1又は2に記載の半導体装置。
- 前記半導体基板は、前記アクティブ領域に形成された複数の撮像素子を含み、前記貫通電極の形成部分は前記撮像素子の外周に延在するフィールド領域内に存在していることを特徴とする請求項1乃至3のいずれか1つに記載の半導体装置。
- 半導体基板に複数の能動素子が形成されたアクティブ領域と前記アクティブ領域以外のフィールド領域とを形成する工程と、前記能動素子のいずれかに電気的に接続された少なくとも1つの電極パッドを形成する工程と、前前記半導体基板の裏面から前記フィールド領域を貫通して形成されるとともに前記電極パッドに電気的に接続された少なくとも1つの貫通電極が形成される半導体装置の製造方法であって、
前記フィールド領域を形成する工程は、前記半導体基板に絶縁膜を形成して絶縁領域を形成する工程と前記絶縁領域内に前記半導体基板の基材を残すことにより前記貫通電極がよぎる領域の外側にのみダミー部を形成する工程とを含み、前記貫通電極の外縁が前記絶縁領域と前記ダミー部との界面と交差していないことを特徴とする半導体装置の製造方法。 - 前記貫通電極がよぎる領域を囲むリング状のダミー部を設ける工程を更に有することを特徴とする請求項5に記載の半導体装置の製造方法。
- 請求項1乃至4のいずれか1つに記載の半導体装置を含む半導体パッケージの製造方法であって、
前記半導体基板の前記貫通電極の形成部分に前記半導体基板の裏面から前記電極パッドに達する貫通孔を形成する工程と、
前記貫通孔の内壁および前記半導体基板の裏面に絶縁膜を形成する工程と、
前記貫通孔の底面の前記絶縁膜を選択的に除去して前記貫通孔の内部において前記電極パッドを露出させる工程と、
前記貫通孔の内壁および前記半導体基板の裏面を覆うバリアメタルおよび導電膜を順次形成して前記貫通電極を形成するとともに、前記半導体基板の裏面に前記貫通電極と電気的に接続された裏面配線を形成する工程と、
前記半導体基板の裏面に開口部を有する絶縁膜を形成する工程と、
前記開口部において露出している部分の前記裏面配線に外部接続端子を形成する工程と、を含むことを特徴とする半導体パッケージの製造方法。
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JP2008180289A JP5356742B2 (ja) | 2008-07-10 | 2008-07-10 | 半導体装置、半導体装置の製造方法および半導体パッケージの製造方法 |
US12/458,324 US9892968B2 (en) | 2008-07-10 | 2009-07-08 | Semiconductor device having a dummy portion, method for manufacturing the semiconductor device, method for manufacturing a semiconductor package having the semiconductor device |
US15/879,006 US20180151434A1 (en) | 2008-07-10 | 2018-01-24 | Method for manufacturing a semiconductor device having a dummy section |
US16/460,969 US10892189B2 (en) | 2008-07-10 | 2019-07-02 | Method for manufacturing a semiconductor device having a dummy section |
US17/117,727 US11798847B2 (en) | 2008-07-10 | 2020-12-10 | Method for manufacturing a semiconductor device having a dummy section |
US18/360,814 US20230386922A1 (en) | 2008-07-10 | 2023-07-28 | Method for manufacturing a semiconductor device having a dummy section |
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JP2010205921A (ja) * | 2009-03-03 | 2010-09-16 | Olympus Corp | 半導体装置および半導体装置の製造方法 |
US8624342B2 (en) * | 2010-11-05 | 2014-01-07 | Invensas Corporation | Rear-face illuminated solid state image sensors |
US8742564B2 (en) * | 2011-01-17 | 2014-06-03 | Bai-Yao Lou | Chip package and method for forming the same |
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