JP4191110B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4191110B2 JP4191110B2 JP2004217443A JP2004217443A JP4191110B2 JP 4191110 B2 JP4191110 B2 JP 4191110B2 JP 2004217443 A JP2004217443 A JP 2004217443A JP 2004217443 A JP2004217443 A JP 2004217443A JP 4191110 B2 JP4191110 B2 JP 4191110B2
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- wiring
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- semiconductor device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Description
10 半導体基板
12 回路形成層
14 ローカル配線層(第1の配線層)
16 セミグローバル配線層
18 グローバル配線層(第2の配線層)
24 ローカル配線(第1の配線)
26 セミグローバル配線
28 グローバル配線(第2の配線)
34 ダミー配線(第1のダミー配線)
38 ダミー配線(第2のダミー配線)
Claims (4)
- 半導体基板上に設けられ、第1の配線および第1のダミー配線を含む第1の配線層と、
前記第1の配線層上に設けられ、第2の配線および第2のダミー配線を含む第2の配線層と、を備え、
前記第1の配線の厚みは、前記第2の配線の厚みよりも小さく、
前記第1のダミー配線の最大幅は、前記第2のダミー配線の最小幅よりも小さいことを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記第1のダミー配線の幅は、前記第1の配線の最小幅以上最大幅以下であり、
前記第2のダミー配線の幅は、前記第2の配線の最小幅以上最大幅以下である半導体装置。 - 請求項1または2に記載の半導体装置において、
前記第2のダミー配線の最大アスペクト比を1としたとき、
前記第1のダミー配線の最小アスペクト比は0.5以上10以下である半導体装置。 - 請求項1乃至3の何れかに記載の半導体装置において、
前記第2のダミー配線の最小幅は、前記第2の配線の最小配線間隔よりも大きい半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004217443A JP4191110B2 (ja) | 2004-07-26 | 2004-07-26 | 半導体装置 |
US11/184,946 US7358609B2 (en) | 2004-07-26 | 2005-07-20 | Semiconductor device |
CN2005100849828A CN1728380B (zh) | 2004-07-26 | 2005-07-26 | 半导体器件 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004217443A JP4191110B2 (ja) | 2004-07-26 | 2004-07-26 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006041114A JP2006041114A (ja) | 2006-02-09 |
JP4191110B2 true JP4191110B2 (ja) | 2008-12-03 |
Family
ID=35656281
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004217443A Active JP4191110B2 (ja) | 2004-07-26 | 2004-07-26 | 半導体装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7358609B2 (ja) |
JP (1) | JP4191110B2 (ja) |
CN (1) | CN1728380B (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8049340B2 (en) | 2006-03-22 | 2011-11-01 | Lsi Corporation | Device for avoiding parasitic capacitance in an integrated circuit package |
US9542522B2 (en) * | 2014-09-19 | 2017-01-10 | Intel Corporation | Interconnect routing configurations and associated techniques |
EP3007224A1 (en) | 2014-10-08 | 2016-04-13 | Nxp B.V. | Metallisation for semiconductor device |
JP7353121B2 (ja) | 2019-10-08 | 2023-09-29 | キヤノン株式会社 | 半導体装置および機器 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11307633A (ja) * | 1997-11-17 | 1999-11-05 | Sony Corp | 低誘電率膜を有する半導体装置、およびその製造方法 |
JP3638778B2 (ja) * | 1997-03-31 | 2005-04-13 | 株式会社ルネサステクノロジ | 半導体集積回路装置およびその製造方法 |
JP2001196372A (ja) * | 2000-01-13 | 2001-07-19 | Mitsubishi Electric Corp | 半導体装置 |
JP3806016B2 (ja) | 2000-11-30 | 2006-08-09 | 富士通株式会社 | 半導体集積回路 |
JP2003045876A (ja) * | 2001-08-01 | 2003-02-14 | Seiko Epson Corp | 半導体装置 |
JP2003273210A (ja) * | 2002-03-12 | 2003-09-26 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP4040363B2 (ja) * | 2002-05-20 | 2008-01-30 | 富士通株式会社 | 半導体装置 |
JP4307022B2 (ja) | 2002-07-05 | 2009-08-05 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置の設計方法、半導体装置の設計プログラム及び半導体装置の設計装置 |
JP2004153015A (ja) * | 2002-10-30 | 2004-05-27 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP4230334B2 (ja) * | 2003-10-31 | 2009-02-25 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
-
2004
- 2004-07-26 JP JP2004217443A patent/JP4191110B2/ja active Active
-
2005
- 2005-07-20 US US11/184,946 patent/US7358609B2/en active Active
- 2005-07-26 CN CN2005100849828A patent/CN1728380B/zh active Active
Also Published As
Publication number | Publication date |
---|---|
US7358609B2 (en) | 2008-04-15 |
CN1728380B (zh) | 2010-12-22 |
US20060017167A1 (en) | 2006-01-26 |
CN1728380A (zh) | 2006-02-01 |
JP2006041114A (ja) | 2006-02-09 |
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