JP4230334B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP4230334B2 JP4230334B2 JP2003372304A JP2003372304A JP4230334B2 JP 4230334 B2 JP4230334 B2 JP 4230334B2 JP 2003372304 A JP2003372304 A JP 2003372304A JP 2003372304 A JP2003372304 A JP 2003372304A JP 4230334 B2 JP4230334 B2 JP 4230334B2
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- film
- wiring
- insulating film
- layer
- interlayer insulating
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- 239000004065 semiconductor Substances 0.000 title claims description 94
- 238000004519 manufacturing process Methods 0.000 title claims description 51
- 239000010410 layer Substances 0.000 claims description 516
- 239000011229 interlayer Substances 0.000 claims description 199
- 230000004888 barrier function Effects 0.000 claims description 107
- 229910052751 metal Inorganic materials 0.000 claims description 106
- 239000002184 metal Substances 0.000 claims description 106
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 75
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 71
- 238000000034 method Methods 0.000 claims description 64
- 238000009792 diffusion process Methods 0.000 claims description 53
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 52
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 52
- 239000004020 conductor Substances 0.000 claims description 30
- 238000005498 polishing Methods 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 27
- 230000002265 prevention Effects 0.000 claims description 19
- 229910021426 porous silicon Inorganic materials 0.000 claims description 4
- 239000010408 film Substances 0.000 description 953
- 239000010949 copper Substances 0.000 description 100
- 239000011295 pitch Substances 0.000 description 87
- 230000008569 process Effects 0.000 description 36
- 239000000463 material Substances 0.000 description 32
- 239000011347 resin Substances 0.000 description 24
- 229920005989 resin Polymers 0.000 description 24
- 229920002120 photoresistant polymer Polymers 0.000 description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 21
- 229910052710 silicon Inorganic materials 0.000 description 21
- 239000010703 silicon Substances 0.000 description 21
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 19
- 238000000206 photolithography Methods 0.000 description 14
- 229910052715 tantalum Inorganic materials 0.000 description 14
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 14
- 239000005871 repellent Substances 0.000 description 13
- 230000007547 defect Effects 0.000 description 12
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 11
- 238000005229 chemical vapour deposition Methods 0.000 description 10
- 239000013039 cover film Substances 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000004140 cleaning Methods 0.000 description 7
- 238000005530 etching Methods 0.000 description 7
- 238000002955 isolation Methods 0.000 description 7
- 238000004544 sputter deposition Methods 0.000 description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
- 238000004380 ashing Methods 0.000 description 6
- 230000007797 corrosion Effects 0.000 description 6
- 238000005260 corrosion Methods 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 6
- 238000010030 laminating Methods 0.000 description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 238000001035 drying Methods 0.000 description 4
- 238000009713 electroplating Methods 0.000 description 4
- 230000035945 sensitivity Effects 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000011065 in-situ storage Methods 0.000 description 3
- 238000002156 mixing Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 238000009832 plasma treatment Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- 150000004760 silicates Chemical class 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910008051 Si-OH Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910006358 Si—OH Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
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- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
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- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
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- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
- H01L2224/05089—Disposition of the additional element
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- H01L2224/05075—Plural internal layers
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- H01L2224/05089—Disposition of the additional element
- H01L2224/05093—Disposition of the additional element of a plurality of vias
- H01L2224/05096—Uniform arrangement, i.e. array
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- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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Description
シリコン基板300の素子領域には、ゲート電極304及びソース/ドレイン拡散層306を有するMOSトランジスタが形成されている。
シリコン基板10の素子領域には、ゲート電極20及びソース/ドレイン拡散層22を有するMOSトランジスタが形成されている。
本発明は上記実施形態に限らず種々の変形が可能である。
基板上に形成され、第1の低誘電率膜と、前記第1の低誘電率膜上に形成された親水性絶縁膜とを有する第1の層間絶縁膜と、
前記第1の層間絶縁膜に形成された第1の配線溝内に埋め込まれ、最小の配線ピッチが第1のピッチである第1の配線層と、
前記第1の層間絶縁膜上に形成され、第2の低誘電率膜を有する第2の層間絶縁膜と、
前記第2の層間絶縁膜に形成された第2の配線溝内に埋め込まれ、最小の配線ピッチが前記第1のピッチよりも広い第2のピッチである第2の配線層と、
前記第2の低誘電率膜及び前記第2の配線層上に直に形成された拡散防止膜と
を有することを特徴とする半導体装置。
付記1記載の半導体装置において、
前記第2の層間絶縁膜上に形成され、前記第1の低誘電率膜及び前記第2の低誘電率膜よりも誘電率の高い絶縁膜を有する第3の層間絶縁膜と、
前記第3の層間絶縁膜に形成された第3の配線溝内に埋め込まれ、最小の配線ピッチが前記第1のピッチ及び前記第2のピッチよりも広い第3のピッチである第3の配線層とを更に有する
ことを特徴とする半導体装置。
付記1又は2記載の半導体装置において、
前記親水性絶縁膜及び前記第1の配線層上に直に形成された拡散防止膜を更に有する
ことを特徴とする半導体装置。
付記1乃至3のいずれかに記載の半導体装置において、
前記第2のピッチは、前記第1のピッチの1.5倍以上である
ことを特徴とする半導体装置。
付記1乃至4のいずれかに記載の半導体装置において、
前記低誘電率膜は、SiOC膜、SiLK膜、BCB膜、FLARE膜、又は多孔質シリコン酸化膜である
ことを特徴とする半導体装置。
付記1乃至5のいずれかに記載の半導体装置において、
前記配線層は、前記層間絶縁膜に形成されたビアホール内、及び前記層間絶縁膜の前記ビアホールを含む領域上に形成された前記配線溝内に埋め込まれている
ことを特徴とする半導体装置。
付記1乃至6のいずれかに記載の半導体装置において、
前記配線層の主材料は、Cu又はAlである
ことを特徴とする半導体装置。
基板上に形成され、最小の配線ピッチが第1のピッチである複数の配線層を含む第1の多層配線層と、
前記第1の多層配線層上に形成され、最小の配線ピッチが前記第1のピッチよりも広い第2のピッチである複数の配線層を含む第2の多層配線層とを有する半導体装置であって、
前記第1の多層配線層を構成する前記複数の配線層のうちの少なくとも1層は、第1の低誘電率膜と、前記第1の低誘電率膜上に形成された親水性絶縁膜とを有する第1の層間絶縁膜に形成された開口部に埋め込まれており、
前記第2の多層配線層を構成する前記複数の配線層のそれぞれは、拡散防止膜と、前記拡散防止膜上に形成された第2の低誘電率膜とを有する第2の層間絶縁膜に形成された開口部に埋め込まれており、
一の前記第2の層間絶縁膜の前記第2の低誘電率膜上に、他の前記第2の層間絶縁膜の前記拡散防止膜が直に形成されている
ことを特徴とする半導体装置。
付記8記載の半導体装置において、
前記第2の多層配線層上に形成され、最小の配線ピッチが前記第1のピッチ及び前記第2のピッチよりも広い第3のピッチである複数の配線層を含む第3の多層配線層を更に有し、
前記第3の多層配線層を構成する前記複数の配線層は、前記第1の低誘電率膜及び前記第2の低誘電率膜よりも誘電率の高い絶縁膜を有する第3の層間絶縁膜に形成された開口部に埋め込まれている
ことを特徴とする半導体装置。
基板上に、第1の低誘電率膜と、前記第1の低誘電率膜上に形成された第1の親水性絶縁膜とを有する第1の層間絶縁膜を形成する工程と、
前記第1の層間絶縁膜に、第1の配線溝を形成する工程と、
前記第1の配線溝が形成された前記第1の層間絶縁膜上に第1の導電体膜を形成する工程と、
前記第1の導電体膜を研磨することにより、前記第1の親水性絶縁膜を露出するとともに、前記第1の配線溝内に前記第1の導電体膜を埋め込み、最小の配線ピッチが第1のピッチである第1の配線層を形成する工程と、
前記第1の層間絶縁膜上に、第2の低誘電率膜を有する第2の層間絶縁膜を形成する工程と、
前記第2の層間絶縁膜に、第2の配線溝を形成する工程と、
前記第2の配線溝が形成された前記第2の層間絶縁膜上に、第2の導電体膜を形成する工程と、
前記第2の導電体膜を研磨することにより、前記第2の低誘電率膜を露出するとともに、前記第2の配線溝内に前記第2の導電体膜を埋め込み、最小の配線ピッチが前記第1のピッチよりも広い第2のピッチである第2の配線層を形成する工程と
を有することを特徴とする半導体装置の製造方法。
付記10記載の半導体装置の製造方法において、
前記第2の配線層を形成する工程の後に、前記第2の低誘電率膜及び前記第2の配線層上に、拡散防止膜を直に形成する工程を更に有する
ことを特徴とする半導体装置の製造方法。
付記10又は11記載の半導体装置の製造方法において、
前記第1の導電体膜を形成する工程では、バリアメタル層と、前記バリアメタル層上に形成された金属膜とを有する前記第1の導電体膜を形成し、
前記第1の配線層を形成する工程では、前記バリアメタル層に対して選択的に前記金属膜を研磨し、前記バリアメタル層の表面で研磨を停止し、次いで、前記バリアメタル層を研磨することにより、前記第1の親水性絶縁膜を露出する
ことを特徴とする半導体装置の製造方法。
付記10乃至12のいずれかに記載の半導体装置の製造方法において、
前記第2の層間絶縁膜を形成する工程は、前記第2の低誘電率膜上に第2の親水性絶縁膜を形成する工程を有し、
前記第2の配線層を形成する工程では、前記第2の導電体膜及び前記第2の親水性絶縁膜を研磨することにより、前記第2の低誘電率膜を露出する
ことを特徴とする半導体装置の製造方法。
付記13記載の半導体装置の製造方法において、
前記第2の導電体膜を形成する工程では、バリアメタル層と、前記バリアメタル層上に形成された金属膜とを有する前記第2の導電体膜を形成し、
前記第2の配線層を形成する工程では、前記バリアメタル層に対して選択的に前記金属膜を研磨し、前記バリアメタル層の表面で研磨を停止し、次いで、前記バリアメタル層と前記第2の親水性絶縁膜とを研磨することにより、前記第2の低誘電率膜を露出する
ことを特徴とする半導体装置の製造方法。
付記13又は14記載の半導体装置の製造方法において、
前記第1の層間絶縁膜を形成する工程では、前記第2の親水性絶縁膜よりも厚い膜厚で前記第1の親水性絶縁膜を形成する
ことを特徴とする半導体装置の製造方法。
付記10乃至15のいずれかに記載の半導体装置の製造方法において、
前記第1の配線溝内に前記第1の導体膜を埋め込む工程の後に、HF処理により異物を除去する工程を更に有する
ことを特徴とする半導体装置の製造方法。
12…下層配線部
14…中間層配線部
16…上層配線部
18…素子分離膜
20…ゲート電極
22…ソース/ドレイン拡散層
24…層間絶縁膜
26…ビアホール
28…コンタクトプラグ
30、46、50、68、72、90、94、112、116…SiC膜
32、48、52、70、74、92、96、114、118…low−k膜
34、54、76、98、120…親水性絶縁膜
36、56、78、100、122…層間絶縁膜
38a、38b、60a、60b、82a、82b、104a、104b、126a、126b…配線溝
40、62、84、106、128…バリアメタル層
42、64、86、108、130…Cu膜
44a、44b、66a、66b、88a、88b、110a、110b、132a、132b…配線層
58、80、102、124…ビアホール
134、138、154、158…SiC膜
136、140、156、160…low−k膜
142、162…層間絶縁膜
144、164…ビアホール
146a、146b、166a、166b…配線溝
148、168…バリアメタル層
150、170…Cu膜
152a、152b、172a、172b…配線層
174、178、194、198…SiC膜
176、180、196、200…シリコン酸化膜
182、202…層間絶縁膜
184、204…ビアホール
186a、186b、206a、206b…配線溝
188、208…バリアメタル層
190、210…Cu膜
192a、192b、212a、212b…配線層
214…SiC膜
216…シリコン酸化膜
218…層間絶縁膜
220…ビアホール
222…コンタクトプラグ
224…電極
226…カバー膜
226a…シリコン酸化膜
226b…シリコン窒化膜
228…開口部
232、236、246、254…シリコン窒化膜
234、238、242、248、252、256、260…フォトレジスト膜
240、250、258…樹脂
244…親水性絶縁膜
300…シリコン基板
302…素子分離膜
304…ゲート電極
306…ソース/ドレイン拡散層
308…コンタクトプラグ
310…層間絶縁膜
312、316、318、322、324、328、330…層間絶縁膜
314a、314b、320a、320b、326a、326b、332a、332b…配線層
334、336、340、342…層間絶縁膜
338a、338b、344a、344b…配線層
346…層間絶縁膜
348…コンタクトプラグ
350…電極
352…カバー膜
352a…シリコン酸化膜
352b…シリコン窒化膜
354…開口部
Claims (14)
- 基板上に形成され、第1の低誘電率膜と、前記第1の低誘電率膜上に形成された親水性絶縁膜とを有する第1の層間絶縁膜と、
前記第1の層間絶縁膜に形成された第1の配線溝内に埋め込まれ、最小の配線ピッチが第1のピッチである第1の配線層と、
前記親水性絶縁膜及び前記第1の配線層上に直に形成された第1の拡散防止膜と、
前記第1の拡散防止膜上に形成され、第2の低誘電率膜を有する第2の層間絶縁膜と、
前記第2の層間絶縁膜に形成された第2の配線溝内に埋め込まれ、最小の配線ピッチが前記第1のピッチよりも広い第2のピッチである第2の配線層と、
前記第2の低誘電率膜及び前記第2の配線層上に直に形成された第2の拡散防止膜と
を有することを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第2の層間絶縁膜上に形成され、前記第1の低誘電率膜及び前記第2の低誘電率膜よりも誘電率の高い絶縁膜を有する第3の層間絶縁膜と、
前記第3の層間絶縁膜に形成された第3の配線溝内に埋め込まれ、最小の配線ピッチが前記第1のピッチ及び前記第2のピッチよりも広い第3のピッチである第3の配線層とを更に有する
ことを特徴とする半導体装置。 - 請求項1又は2記載の半導体装置において、
前記第2のピッチは、前記第1のピッチの1.5倍以上である
ことを特徴とする半導体装置。 - 基板上に形成され、最小の配線ピッチが第1のピッチである複数の配線層を含む第1の多層配線層と、
前記第1の多層配線層上に形成され、最小の配線ピッチが前記第1のピッチよりも広い第2のピッチである複数の配線層を含む第2の多層配線層とを有する半導体装置であって、
前記第1の多層配線層を構成する前記複数の配線層のうちの少なくとも1層は、第1の低誘電率膜と、前記第1の低誘電率膜上に形成された親水性絶縁膜とを有する第1の層間絶縁膜に形成された開口部に埋め込まれており、前記親水性絶縁膜及び前記第1の配線層上に第1の拡散防止膜が直に形成されており、
前記第2の多層配線層を構成する前記複数の配線層のそれぞれは、第2の拡散防止膜と、前記第2の拡散防止膜上に形成された第2の低誘電率膜とを有する第2の層間絶縁膜に形成された開口部に埋め込まれており、
一の前記第2の層間絶縁膜の前記第2の低誘電率膜上に、他の前記第2の層間絶縁膜の前記第2の拡散防止膜が直に形成されている
ことを特徴とする半導体装置。 - 請求項1乃至4のいずれか1項に記載の半導体装置において、
前記親水性絶縁膜は、シリコン酸化膜又はFSG膜である
ことを特徴とする半導体装置。 - 請求項1乃至5のいずれか1項に記載の半導体装置において、
前記第1及び/又は第2の拡散防止膜は、SiC膜又はシリコン窒化膜である
ことを特徴とする半導体装置。 - 請求項1乃至6のいずれか1項に記載の半導体装置において、
前記第1及び/又は第2の低誘電率膜は、SiOC膜、SiLK膜、BCB膜、FLARE膜、又は多孔質シリコン酸化膜である
ことを特徴とする半導体装置。 - 基板上に、第1の低誘電率膜と、前記第1の低誘電率膜上に形成された第1の親水性絶縁膜とを有する第1の層間絶縁膜を形成する工程と、
前記第1の層間絶縁膜に、第1の配線溝を形成する工程と、
前記第1の配線溝が形成された前記第1の層間絶縁膜上に第1の導電体膜を形成する工程と、
前記第1の導電体膜を研磨することにより、前記第1の親水性絶縁膜を露出するとともに、前記第1の配線溝内に前記第1の導電体膜を埋め込み、最小の配線ピッチが第1のピッチである第1の配線層を形成する工程と、
前記親水性絶縁膜及び前記第1の配線層上に、第1の拡散防止膜を直に形成する工程と、
前記第1の拡散防止膜上に、第2の低誘電率膜を有する第2の層間絶縁膜を形成する工程と、
前記第2の層間絶縁膜に、第2の配線溝を形成する工程と、
前記第2の配線溝が形成された前記第2の層間絶縁膜上に、第2の導電体膜を形成する工程と、
前記第2の導電体膜を研磨することにより、前記第2の低誘電率膜を露出するとともに、前記第2の配線溝内に前記第2の導電体膜を埋め込み、最小の配線ピッチが前記第1のピッチよりも広い第2のピッチである第2の配線層を形成する工程と、
前記第2の低誘電率膜及び前記第2の配線層上に、第2の拡散防止膜を直に形成する工程と
を有することを特徴とする半導体装置の製造方法。 - 請求項8記載の半導体装置の製造方法において、
前記第1の導電体膜を形成する工程では、バリアメタル層と、前記バリアメタル層上に形成された金属膜とを有する前記第1の導電体膜を形成し、
前記第1の配線層を形成する工程では、前記バリアメタル層に対して選択的に前記金属膜を研磨し、前記バリアメタル層の表面で研磨を停止し、次いで、前記バリアメタル層を研磨することにより、前記第1の親水性絶縁膜を露出する
ことを特徴とする半導体装置の製造方法。 - 請求項8又は9記載の半導体装置の製造方法において、
前記第2の層間絶縁膜を形成する工程は、前記第2の低誘電率膜上に第2の親水性絶縁膜を形成する工程を有し、
前記第2の配線層を形成する工程では、前記第2の導電体膜及び前記第2の親水性絶縁膜を研磨することにより、前記第2の低誘電率膜を露出する
ことを特徴とする半導体装置の製造方法。 - 請求項10記載の半導体装置の製造方法において、
前記第2の導電体膜を形成する工程では、バリアメタル層と、前記バリアメタル層上に形成された金属膜とを有する前記第2の導電体膜を形成し、
前記第2の配線層を形成する工程では、前記バリアメタル層に対して選択的に前記金属膜を研磨し、前記バリアメタル層の表面で研磨を停止し、次いで、前記バリアメタル層と前記第2の親水性絶縁膜とを研磨することにより、前記第2の低誘電率膜を露出する
ことを特徴とする半導体装置の製造方法。 - 請求項8乃至11のいずれか1項に記載の半導体装置の製造方法において、
前記第1及び/又は第2の親水性絶縁膜は、シリコン酸化膜又はFSG膜である
ことを特徴とする半導体装置の製造方法。 - 請求項8乃至12のいずれか1項に記載の半導体装置の製造方法において、
前記第1及び/又は第2の拡散防止膜は、SiC膜又はシリコン窒化膜である
ことを特徴とする半導体装置の製造方法。 - 請求項8乃至13のいずれか1項に記載の半導体装置の製造方法において、
前記第1及び/又は第2の低誘電率膜は、SiOC膜、SiLK膜、BCB膜、FLARE膜、又は多孔質シリコン酸化膜である
ことを特徴とする半導体装置の製造方法。
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