JP2009206241A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2009206241A JP2009206241A JP2008045666A JP2008045666A JP2009206241A JP 2009206241 A JP2009206241 A JP 2009206241A JP 2008045666 A JP2008045666 A JP 2008045666A JP 2008045666 A JP2008045666 A JP 2008045666A JP 2009206241 A JP2009206241 A JP 2009206241A
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Abstract
【解決手段】銅を主導電層とする埋め込み配線5、8、11を内部に形成した層間絶縁膜4、7、10と、埋め込み配線5、8、11のキャップ絶縁膜6、9、12を積層した構造を備えた半導体装置において、相対的にヤング率の小さいLow−k膜からなる層間絶縁膜7と上面で接する相対的にヤング率の大きいキャップ絶縁膜6は、半導体装置の端部において、非設置となるように形成する。
【選択図】図4
Description
主面に半導体素子が形成され、前記平面矩形でパターニングされた半導体基板と、
前記半導体基板の主面上に形成された第1の絶縁膜と、
前記第1の絶縁膜に形成された第1の溝部に導電性膜を埋め込んで形成された第1の配線と、
前記第1の絶縁膜及び前記第1の配線上に形成された第2の絶縁膜と、
前記第2の絶縁膜上に前記第2の絶縁膜と接するように形成された第3の絶縁膜とを有し、
前記第2の絶縁膜は、前記第3の絶縁膜と比べてヤング率が大きく、
前記半導体チップの平面外周に面した第1の領域においては、前記第2の絶縁膜が除去されているものである。
主面に半導体素子が形成され、前記平面矩形でパターニングされた半導体基板と、
前記半導体基板の主面上に形成された第1の絶縁膜と、
前記第1の絶縁膜に形成された第1の溝部に導電性膜を埋め込んで形成された第1の配線と、
前記第1の絶縁膜及び前記第1の配線上に形成された第2の絶縁膜と、
前記第2の絶縁膜上に前記第2の絶縁膜と接するように形成された第3の絶縁膜とを有し、
前記第3の絶縁膜は、前記第2の絶縁膜と比べて上層または下層の膜との密着度が低く、
前記半導体チップの平面外周に面した第1の領域においては、前記第2の絶縁膜が除去されているものである。
以下、本実施の形態1について、図4〜図14を参照して詳細に説明する。
次に、本実施の形態2について、図面を参照して詳細に説明する。図15は、本実施の形態2の半導体装置(チップ)の端部付近の要部断面図である。
次に、本実施の形態3について、図16を参照して詳細に説明する。図16は、本実施の形態3の半導体装置におけるキャップ絶縁膜6(図4も参照)の非設置箇所31を説明する平面レイアウト図である。
次に、本実施の形態4について、図17と図18を参照して詳細に説明する。
次に、本実施の形態5について、図19を参照して詳細に説明する。
2、4 層間絶縁膜(第1の絶縁膜)
3 ビア
3A ビアホール
3B ビア
3C ビアホール
5 埋め込み配線(第1の配線)
5A 溝(第1の溝部)
5B 埋め込み配線(第2の配線)
5C 溝(第2の溝部)
6、9、12 キャップ絶縁膜(第2の絶縁膜)
7、10 層間絶縁膜(第3の絶縁膜)
8 埋め込み配線(第3の配線)
8A コンタクトホール(第3の溝部)
8B 溝(第3の溝部)
8C 埋め込み配線
8D コンタクトホール
8E 溝
11 埋め込み配線
11A コンタクトホール
11B 溝
11C 埋め込み配線
11D コンタクトホール
11E 溝
13 層間絶縁膜
14 ビア
14A ビアホール
14B ビア
14C ビアホール
15 配線
15B 配線
16 表面保護膜
17 フォトレジスト膜
21 半導体装置(半導体チップ)
22a、22b 金属フレーム
23 レジン
24 金属配線
25 実装基板
26 半田ボール
27 金バンプ
28 アンダーフィル樹脂
31 非設置箇所(第1の領域)
41 ガードリング配線
106 キャップメタル膜
Claims (12)
- 平面矩形の半導体チップを備えた半導体装置であって、前記半導体チップは、
主面に半導体素子が形成され、前記平面矩形でパターニングされた半導体基板と、
前記半導体基板の主面上に形成された第1の絶縁膜と、
前記第1の絶縁膜に形成された第1の溝部に導電性膜を埋め込んで形成された第1の配線と、
前記第1の配線上に形成された第1のキャップ膜とを有し、
前記第1のキャップ膜は、
前記半導体チップの平面外周に面した第1の領域においては、前記第1のキャップ膜が非設置であることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第1のキャップ膜は、Co膜、W膜、CoW膜、CoWP膜、Cuシリサイド膜、Ru膜、あるいは、これらの積層構造からなることを特徴とする半導体装置。 - 平面矩形の半導体チップを備えた半導体装置であって、前記半導体チップは、
主面に半導体素子が形成され、前記平面矩形でパターニングされた半導体基板と、
前記半導体基板の主面上に形成された第1の絶縁膜と、
前記第1の絶縁膜に形成された第1の溝部に導電性膜を埋め込んで形成された第1の配線と、
前記第1の絶縁膜及び前記第1の配線上に形成された第2の絶縁膜と、
前記第2の絶縁膜上に前記第2の絶縁膜と接するように形成された第3の絶縁膜とを有し、
前記第2の絶縁膜は、前記第3の絶縁膜と比べてヤング率が大きく、
前記半導体チップの平面外周に面した第1の領域においては、前記第2の絶縁膜が除去されていることを特徴とする半導体装置。 - 平面矩形の半導体チップを備えた半導体装置であって、前記半導体チップは、
主面に半導体素子が形成され、前記平面矩形でパターニングされた半導体基板と、
前記半導体基板の主面上に形成された第1の絶縁膜と、
前記第1の絶縁膜に形成された第1の溝部に導電性膜を埋め込んで形成された第1の配線と、
前記第1の絶縁膜及び前記第1の配線上に形成された第2の絶縁膜と、
前記第2の絶縁膜上に前記第2の絶縁膜と接するように形成された第3の絶縁膜とを有し、
前記第3の絶縁膜は、前記第2の絶縁膜と比べて上層または下層の膜との密着度が低く、
前記半導体チップの平面外周に面した第1の領域においては、前記第2の絶縁膜が除去されていることを特徴とする半導体装置。 - 請求項3または4記載の半導体装置において、
前記第2の絶縁膜は、SiN膜、SiCN膜、SiCO膜あるいはこれらの積層膜から形成され、
前記第3の絶縁膜は、CVD法で成膜された酸化シリコン膜より相対的に誘電率が低いことを特徴とする半導体装置。 - 請求項3〜5のいずれか1項に記載の半導体装置において、
前記導電性膜は、銅を主成分とすることを特徴とする半導体装置。 - 請求項3〜6のいずれか1項に記載の半導体装置において、
前記第1の領域は、少なくとも前記半導体チップの平面角部を含むことを特徴とする半導体装置。 - 請求項7記載の半導体装置において、
前記第1の領域は、少なくとも前記半導体チップの前記平面角部から1μm〜5μmの領域を含むことを特徴とする半導体装置。 - 請求項8記載の半導体装置において、
前記第1の領域は、少なくとも前記半導体チップの平面四辺から1μm〜5μmの領域を含むことを特徴とする半導体装置。 - 請求項9記載の半導体装置において、
前記第1の領域は、前記半導体チップの前記平面角部からの広さが前記平面四辺からの広さより大きく確保されていることを特徴とする半導体装置。 - 請求項3〜10のいずれか1項に記載の半導体装置において、
前記半導体チップ内は、平面で回路形成領域が規定され、
前記第1の配線は、平面で前記回路形成領域内に形成され、
前記第1の絶縁膜には、平面で前記回路形成領域を取り囲むように第2の溝部が形成され、
前記第2の溝部には、前記導電性膜が埋め込まれて第2の配線が形成され、
前記第1の領域は、平面で前記第2の配線の外側に配置されていることを特徴とする半導体装置。 - 請求項3〜11のいずれか1項に記載の半導体装置において、
前記第3の絶縁膜に形成された第3の溝部に前記導電性膜を埋め込んで形成された第3の配線を備え、
前記半導体基板の前記主面上には、複数層の配線層が形成され、
前記複数層の配線層は、前記第3の絶縁膜、前記第3の配線及び前記第2の絶縁膜を積層して形成され、
前記第1の領域において、複数層の前記第2の絶縁膜のうち、少なくとも最下層の前記第2の絶縁膜は除去されていることを特徴とする半導体装置。
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JP5468445B2 (ja) * | 2010-03-31 | 2014-04-09 | 株式会社東芝 | 半導体装置及びその製造方法 |
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