JP4675146B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4675146B2 JP4675146B2 JP2005137593A JP2005137593A JP4675146B2 JP 4675146 B2 JP4675146 B2 JP 4675146B2 JP 2005137593 A JP2005137593 A JP 2005137593A JP 2005137593 A JP2005137593 A JP 2005137593A JP 4675146 B2 JP4675146 B2 JP 4675146B2
- Authority
- JP
- Japan
- Prior art keywords
- protective film
- semiconductor device
- interlayer insulating
- film
- resin protective
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/06179—Corner adaptations, i.e. disposition of the bonding areas at the corners of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
本発明の一側面に係る半導体装置において、樹脂保護膜は、絶縁膜の上面にのみ形成されている。
以下に、本発明の第1の実施形態に係る半導体装置について説明する。
図5は、本発明の第1の実施形態に係る半導体装置の変形例(1)の断面図を示している。
図6は、本発明の第1の実施形態に係る半導体装置の変形例(2)の断面図を示している。
以上に説明したように、本発明に係る半導体装置は、半導体チップのコーナー部に樹脂保護膜を形成することにより、応力を緩和して層間絶縁膜の膜剥がれを防止することが特徴であるが、以下では、シールリング構造を備えた半導体装置に、本発明を適用した場合の例をその他の実施形態として説明する。
12 半導体チップ
13 スクライブライン
21 コーナー部
22 電極パッド
23 素子形成領域
31、32、34、35、37、38 層間絶縁膜
33、36、39 ストッパー材
40 表面保護膜
41、43、45 プラグ
42、44、46 配線
47 電極パッド
48 樹脂保護膜
50 実装基板
51 バンプ電極
52 マウント材
53 ボンディングワイヤ
54 モールド樹脂
71 溝部
72 ダイシングブレード
80 シールリング構造
81、82 樹脂保護膜
Claims (13)
- 基板におけるチップ領域に形成された素子と、
前記基板上に形成された複数の層間絶縁膜と、
前記複数の層間絶縁膜のうちの少なくとも1つに形成された配線と、
前記複数の層間絶縁膜のうちの少なくとも1つに形成され、且つ前記素子と前記配線とを接続するか又は前記配線同士を接続するプラグと、
前記複数の層間絶縁膜の上に形成された表面保護膜と、
前記チップ領域のコーナー部に存在している前記表面保護膜を覆うように形成された樹脂保護膜とを備えており、
前記チップ領域の周縁部に存在している前記複数の層間絶縁膜中に形成され、前記チップ領域における素子形成領域を取り囲むシールリングをさらに備え、
前記樹脂保護膜は、前記シールリングの上部と平面的配置にて重ならない位置に形成されていることを特徴とする半導体装置。 - 前記表面保護膜は、少なくとも窒素を含む絶縁膜であることを特徴とする請求項1に記載の半導体装置。
- 前記樹脂保護膜は、前記表面保護膜の上面にのみ形成されていることを特徴とする請求項1又は2に記載の半導体装置。
- 前記樹脂保護膜は、前記表面保護膜の上面における周縁部を露出させていることを特徴とする請求項1〜3のうちいずれか1項に記載の半導体装置。
- 前記樹脂保護膜は、前記表面保護膜の上面、並びに前記表面保護膜の側面及び前記複数の層間絶縁膜の側面に形成されていることを特徴とする請求項1又は2に記載の半導体装置。
- 前記層間絶縁膜は低誘電率膜を含んでおり、
前記低誘電率膜上に接するようにストッパー材が形成されており、
前記樹脂保護膜は、前記低誘電率膜と前記ストッパー材の側面にも形成されていることを特徴とする請求項5に記載の半導体装置。 - 前記層間絶縁膜の側面に形成された前記樹脂保護膜は前記基板まで達していることを特徴とする請求項5又は6に記載の半導体装置。
- 前記シールリングは、前記素子形成領域の周囲を連続的に取り囲んでいることを特徴とする請求項1〜7のうちいずれか1項に記載の半導体装置。
- 前記シールリングは、前記素子形成領域の周囲を不連続的に取り囲んでいることを特徴とする請求項1〜7のうちいずれか1項に記載の半導体装置。
- 前記樹脂保護膜は、前記チップ領域のコーナー部における前記シールリングの外側に形成されていることを特徴とする請求項1〜9のうちいずれか1項に記載の半導体装置。
- 前記樹脂保護膜は、前記チップ領域のコーナー部における前記シールリングの内側にさらに形成されていることを特徴とする請求項10に記載の半導体装置。
- 前記樹脂保護膜は、該樹脂保護膜にかかる応力を緩和する材料よりなることを特徴とする請求項1〜11のうちいずれか1項に記載の半導体装置。
- 前記複数の層間絶縁膜のうちの少なくとも1つは、シリコン酸化膜よりも誘電率の低い低誘電率材料よりなることを特徴とする請求項1〜12のうちいずれか1項に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005137593A JP4675146B2 (ja) | 2005-05-10 | 2005-05-10 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005137593A JP4675146B2 (ja) | 2005-05-10 | 2005-05-10 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006318988A JP2006318988A (ja) | 2006-11-24 |
JP4675146B2 true JP4675146B2 (ja) | 2011-04-20 |
Family
ID=37539412
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005137593A Expired - Fee Related JP4675146B2 (ja) | 2005-05-10 | 2005-05-10 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4675146B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104428890A (zh) * | 2012-07-11 | 2015-03-18 | 三菱电机株式会社 | 半导体装置及其制造方法 |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009021528A (ja) * | 2007-07-13 | 2009-01-29 | Toshiba Corp | 半導体装置 |
JP4646993B2 (ja) | 2008-02-27 | 2011-03-09 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US9385007B2 (en) | 2012-07-11 | 2016-07-05 | Mitsubishi Electric Corporation | Semiconductor device and method of manufacturing the same |
JP5655844B2 (ja) * | 2012-11-09 | 2015-01-21 | 富士通セミコンダクター株式会社 | 半導体装置およびその製造方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004296905A (ja) * | 2003-03-27 | 2004-10-21 | Toshiba Corp | 半導体装置 |
JP2006100558A (ja) * | 2004-09-29 | 2006-04-13 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
JP2006179542A (ja) * | 2004-12-21 | 2006-07-06 | Renesas Technology Corp | 半導体装置 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60140739A (ja) * | 1983-12-28 | 1985-07-25 | Hitachi Ltd | パツシベ−シヨン構造を備えたプラスチツクicパツケ−ジ |
JPS61171156A (ja) * | 1985-01-25 | 1986-08-01 | Mitsubishi Electric Corp | 半導体装置 |
JPS61269333A (ja) * | 1985-05-24 | 1986-11-28 | Hitachi Ltd | 半導体装置 |
JPH0230138A (ja) * | 1988-07-19 | 1990-01-31 | Seiko Epson Corp | 半導体装置 |
JPH08172062A (ja) * | 1994-12-16 | 1996-07-02 | Oki Electric Ind Co Ltd | 半導体ウエハ及び半導体ウエハの製造方法 |
-
2005
- 2005-05-10 JP JP2005137593A patent/JP4675146B2/ja not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004296905A (ja) * | 2003-03-27 | 2004-10-21 | Toshiba Corp | 半導体装置 |
JP2006100558A (ja) * | 2004-09-29 | 2006-04-13 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
JP2006179542A (ja) * | 2004-12-21 | 2006-07-06 | Renesas Technology Corp | 半導体装置 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104428890A (zh) * | 2012-07-11 | 2015-03-18 | 三菱电机株式会社 | 半导体装置及其制造方法 |
US9543252B2 (en) | 2012-07-11 | 2017-01-10 | Mitsubishi Electric Corporation | Semiconductor apparatus and method for producing the same |
Also Published As
Publication number | Publication date |
---|---|
JP2006318988A (ja) | 2006-11-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI629759B (zh) | 晶片封裝體及其製造方法 | |
JP5205066B2 (ja) | 半導体装置およびその製造方法 | |
JP5175066B2 (ja) | 半導体装置 | |
US8035197B2 (en) | Electronic device and method for fabricating the same | |
JP4675159B2 (ja) | 半導体装置 | |
JP5448304B2 (ja) | 半導体装置 | |
KR101581431B1 (ko) | 가드링들을 갖는 반도체 칩들 및 그 제조방법들 | |
KR100393140B1 (ko) | 반도체 장치 | |
JP2007329396A (ja) | 半導体装置、その製造方法及びその実装方法 | |
US9397054B2 (en) | Semiconductor structure with an interconnect level having a conductive pad and metallic structure such as a base of a crackstop | |
JP2009124042A (ja) | 半導体装置 | |
JP4675146B2 (ja) | 半導体装置 | |
KR100514019B1 (ko) | 반도체 장치 | |
JP6301763B2 (ja) | 半導体装置、および半導体装置の製造方法 | |
JP5361264B2 (ja) | 半導体装置 | |
JP4675147B2 (ja) | 半導体装置 | |
US20110204487A1 (en) | Semiconductor device and electronic apparatus | |
JP4777899B2 (ja) | 半導体装置 | |
JP5424747B2 (ja) | 半導体装置 | |
KR101059625B1 (ko) | 웨이퍼 레벨 칩 스케일 패키지 및 그 제조방법 | |
JP2002026064A (ja) | 半導体素子のボンディングパッド構造体及びその製造方法 | |
JP2007173419A (ja) | 半導体装置 | |
JP2012160547A (ja) | 半導体装置及びその製造方法 | |
JP5564557B2 (ja) | 半導体装置 | |
JP5006026B2 (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20071220 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20091030 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20101109 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20101117 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20110111 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110125 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140204 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
LAPS | Cancellation because of no payment of annual fees |