JP2009124042A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2009124042A JP2009124042A JP2007298361A JP2007298361A JP2009124042A JP 2009124042 A JP2009124042 A JP 2009124042A JP 2007298361 A JP2007298361 A JP 2007298361A JP 2007298361 A JP2007298361 A JP 2007298361A JP 2009124042 A JP2009124042 A JP 2009124042A
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- film
- wiring
- passivation film
- semiconductor device
- post bump
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Abstract
【解決手段】半導体チップ2上には、配線6が形成されている。配線6は、パッシベーション膜7によって被覆されている。パッシベーション膜7には、配線6をパッシベーション膜7から部分的に露出させるための開口8が形成されている。配線6における開口8に臨む部分上には、バリア膜9が形成されている。バリア膜9上には、隆起状に形成され、その周縁部がバリア膜9の周縁部よりも側方にはみ出したポストバンプ3が形成されている。
【選択図】図2
Description
図4は、WL−CSP技術が適用された半導体装置の構造を示す図解的な断面図である。
また、パッシベーション膜104におけるクラックの発生を防止するために、パッシベーション膜104上に開口105と連通する貫通孔を有するポリイミド層を形成し、バリア膜106の周縁部をポリイミド層上に配置することが考えられる。バリア膜106の周縁部とパッシベーション膜104との間にポリイミド層が介在されるため、バリア膜106およびポストバンプ107の周縁部に応力が集中しても、その応力は、ポリイミド層によって吸収され、パッシベーション膜104に伝達されない。よって、パッシベーション膜104にクラックが生じるのを防止することができる。
そこで、本発明の目的は、製造工程数の増加や厚さの増大などの問題を生じることなく、パッシベーション膜にクラックが生じるのを防止することができる半導体装置を提供することにある。
また、請求項2に記載のように、前記介在膜の周縁に対する前記ポストバンプの周縁部のはみ出し量は、前記介在膜の膜厚よりも大きいことが好ましい。
図1は、本発明の一実施形態に係る半導体装置の外観を示す側面図である。
この半導体装置1は、WL−CSP技術が適用された半導体装置であり、半導体チップ2と、半導体チップ2上に設けられた複数のポストバンプ3と、各ポストバンプ3に接合された半田ボール4とを備えている。
半導体チップ2の表層部には、SiO2からなる層間絶縁膜5が形成されている。層間絶縁膜5上には、Alからなる配線6が所定の配線パターンで形成されている。
層間絶縁膜5および配線6上には、配線6を被覆するパッシベーション膜7が形成され、パッシベーション膜7には、配線6の一部をパッシベーション膜7から露出させるための開口8が形成されている。
バリア膜9上には、Cuからなるシード膜10が形成されている。シード膜10の周縁部は、バリア膜9の周縁に対して側方に、バリア膜9の膜厚Tよりも大きいはみ出し量Dではみ出して形成されている。
ポストバンプ3の周縁部がバリア膜9の周縁よりも側方にはみ出していることにより、ポストバンプ3の周縁部とパッシベーション膜7との間に空間が生じている。この空間が存在することにより、ポストバンプ3の周縁部は、パッシベーション膜7との対向方向に変形可能である。よって、ポストバンプ3に応力が生じても、その応力をポストバンプ3の周縁部の変形により吸収することができる。その結果、パッシベーション膜7にクラックが生じるのを防止することができる。
また、ポストバンプ3の周縁部のはみ出し量Dは、バリア膜9の膜厚Tよりも大きい。これにより、ポストバンプ3における変形可能な周縁部の幅をバリア膜9の膜厚よりも大きく確保することができる。
まず、図3Aに示すように、CVD(Chemical Vapor Deposition:化学的気相成長)法により、層間絶縁膜5が形成される。その後、スパッタ法により、層間絶縁膜5上の全面に、Alからなる金属膜(図示せず)が形成される。そして、公知のフォトリソグラフィ技術およびエッチング技術により、層間絶縁膜5上の金属膜が選択的に除去される。これにより、層間絶縁膜5上に、所定の配線パターンを有する配線6が形成される。
たとえば、上記の実施例では、バリア膜9の材料としてTiWを用いたが、バリア膜9の材料としては、Cuの拡散に対するバリア性を有する材料であればよく、例えば、Ti(チタン)、Ta(タンタル)およびTaN(窒化タンタル)などを例示することができる。
また、配線6は、Cuを含む金属材料を用いて形成されていてもよい。Cuを含む金属材料としては、例えば、AlCu(アルミニウム/銅合金)およびCuを例示することができる。その場合、層間絶縁膜5に、その上面から掘り下がった配線溝が形成され、この配線溝に配線6が埋設されてもよい。
2 半導体チップ
3 ポストバンプ
6 配線
7 パッシベーション膜
8 開口
9 バリア膜(介在膜)
D はみ出し量
T 膜厚(介在膜の膜厚)
Claims (3)
- 半導体チップと、
前記半導体チップ上に形成された配線と、
前記配線を被覆するパッシベーション膜と、
前記パッシベーション膜を貫通して形成され、前記配線を前記パッシベーション膜から部分的に露出させるための開口と、
前記配線における前記開口に臨む部分上に形成された介在膜と、
前記介在膜上に隆起状に形成され、その周縁部が前記介在膜の周縁よりも側方にはみ出したポストバンプとを備える、半導体装置。 - 前記介在膜の周縁に対する前記ポストバンプの周縁部のはみ出し量は、前記介在膜の膜厚よりも大きい、請求項1に記載の半導体装置。
- 前記介在膜は、その周縁部が前記パッシベーション膜における前記開口の周囲に乗り上げて形成されている、請求項1または2に記載の半導体装置。
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US12/272,001 US9035455B2 (en) | 2007-11-16 | 2008-11-17 | Semiconductor device |
US14/690,982 US9437544B2 (en) | 2007-11-16 | 2015-04-20 | Semiconductor device |
US15/236,016 US9607957B2 (en) | 2007-11-16 | 2016-08-12 | Semiconductor device |
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JP2011222738A (ja) * | 2010-04-09 | 2011-11-04 | Renesas Electronics Corp | 半導体装置の製造方法 |
US9219044B2 (en) * | 2013-11-18 | 2015-12-22 | Applied Materials, Inc. | Patterned photoresist to attach a carrier wafer to a silicon device wafer |
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US10903151B2 (en) * | 2018-05-23 | 2021-01-26 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and method of manufacturing the same |
JP7319808B2 (ja) * | 2019-03-29 | 2023-08-02 | ローム株式会社 | 半導体装置および半導体パッケージ |
US11393780B2 (en) | 2019-07-26 | 2022-07-19 | Sandisk Technologies Llc | Bonded assembly containing oxidation barriers, hybrid bonding, or air gap, and methods of forming the same |
US11515273B2 (en) | 2019-07-26 | 2022-11-29 | Sandisk Technologies Llc | Bonded assembly containing oxidation barriers, hybrid bonding, or air gap, and methods of forming the same |
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US20150228575A1 (en) | 2015-08-13 |
US20160351519A1 (en) | 2016-12-01 |
US9035455B2 (en) | 2015-05-19 |
JP5627835B2 (ja) | 2014-11-19 |
US20170179060A1 (en) | 2017-06-22 |
US9607957B2 (en) | 2017-03-28 |
US9437544B2 (en) | 2016-09-06 |
US9941231B2 (en) | 2018-04-10 |
US20090127709A1 (en) | 2009-05-21 |
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