JP2006100558A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 145
- 238000004519 manufacturing process Methods 0.000 title claims description 26
- 239000000758 substrate Substances 0.000 claims abstract description 69
- 230000002265 prevention Effects 0.000 claims abstract description 47
- 239000010949 copper Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 20
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052802 copper Inorganic materials 0.000 claims abstract description 17
- 238000009713 electroplating Methods 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 114
- 239000011241 protective layer Substances 0.000 claims description 28
- 238000005530 etching Methods 0.000 claims description 16
- 230000000149 penetrating effect Effects 0.000 claims description 5
- 230000004888 barrier function Effects 0.000 abstract description 14
- 230000000694 effects Effects 0.000 abstract description 11
- 229910000679 solder Inorganic materials 0.000 abstract description 8
- 238000003475 lamination Methods 0.000 abstract 1
- 239000011229 interlayer Substances 0.000 description 8
- 230000001681 protective effect Effects 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 230000008646 thermal stress Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1462—Coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/564—Details not otherwise provided for, e.g. protection against moisture
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
【解決手段】半導体装置100のコーナー部に、絶縁膜17、保護層23の剥離を防止するための剥離防止層30を形成する。剥離防止層30はコーナー部以外の半導体装置10の空きスペース、例えば、ボール状の導電端子24の間に配置することでさらに剥離防止効果を高めることができる。その断面構造は、半導体基板10の裏面に形成された絶縁膜17上に剥離防止層30が形成され、この絶縁膜17及び剥離防止層30を被覆するようにソルダーレジスト等から成る保護層23が形成される。剥離防止層30は、電解メッキ法により形成する場合には、バリアシード層20と上層の銅層25からなる積層構造を有する。
【選択図】 図3
Description
Claims (16)
- 半導体基板と、前記半導体基板の表面に第1の絶縁膜を介して形成されたパッド電極と、前記半導体基板を貫通し前記パッド電極に到達するビアホールと、前記ビアホールの側壁及び半導体基板の裏面を覆う第2の絶縁膜と、前記ビアホールの中に形成され前記パッド電極と接続された貫通電極と、前記第2の絶縁膜上に形成された剥離防止層と、前記貫通電極、前記第2の絶縁膜及び前記剥離防止層を被覆する保護層と、を備えることを特徴とする半導体装置。
- 前記剥離防止層は前記半導体基板のコーナー部に設けられたことを特徴とする請求項1に記載の半導体装置。
- 前記半導体基板の裏面に溝又は穴部が形成され、前記第2の絶縁膜及び前記剥離防止層の一部がこの溝又は穴部の中に配置されていることを特徴とする請求項1又は請求項2に記載の半導体装置。
- 前記保護層が複数の島領域に分割されていることを特徴とする請求項1、2、3のいずれか1項に記載の半導体装置。
- 前記剥離防止層は少なくとも銅層を含むことを特徴とする請求項1、2、3、4のいずれか1項に記載の半導体装置。
- 半導体基板と、前記半導体基板の表面に第1の絶縁膜を介して形成されたパッド電極と、前記半導体基板を貫通し前記パッド電極に到達するビアホールと、前記ビアホールの側壁及び半導体基板の裏面を覆う第2の絶縁膜と、前記ビアホールの中に形成され前記パッド電極と接続された貫通電極と、前記貫通電極と接続され前記半導体基板の裏面の前記絶縁膜上を延在する配線層と、前記第2の絶縁膜上に形成された剥離防止層と、前記貫通電極、前記第2の絶縁膜、前記配線層及び前記剥離防止層を被覆する保護層と、前記配線層上に形成された前記保護層の開口部を通して前記配線層に接続された導電端子と、を備えることを特徴とする半導体装置。
- 前記剥離防止層は前記半導体基板のコーナー部に設けられたことを特徴とする請求項6に記載の半導体装置。
- 前記半導体基板の裏面に溝又は穴部が形成され、前記第2の絶縁膜及び前記剥離防止層の一部がこの溝又は穴部の中に配置されていることを特徴とする請求項6又は請求項7に記載の半導体装置。
- 前記保護層が複数の島領域に分割されていることを特徴とする請求項6、7、8のいずれか1項に記載の半導体装置。
- 前記剥離防止層は少なくとも銅層を含むことを特徴とする請求項6、7、8、9のいずれか1項に記載の半導体装置。
- その表面に第1の絶縁膜を介してパッド電極が形成された半導体基板を準備し、
前記パッド電極に対応する位置に前記半導体基板を貫通するビアホールを形成する工程と、
前記ビアホールの側壁及び前記半導体基板の裏面を被覆する第2の絶縁膜を形成する工程と、
前記ビアホールの中に前記パッド電極と接続された貫通電極及び、前記半導体基板の裏面上の前記第2の絶縁膜上の剥離防止層とを同時に形成する工程と、
前記前記貫通電極、前記第2の絶縁膜及び前記剥離防止層を被覆する保護層を形成する工程とを備えることを特徴とする半導体装置の製造方法。 - 前記貫通電極及び前記剥離防止層は電解メッキ法により形成されることを特徴とする請求項11に記載の半導体装置の製造方法。
- 前記剥離防止層は前記半導体基板のコーナー部に形成されることを特徴とする請求項11又は請求項12に記載の半導体装置の製造方法。
- 前記ビアホールと同時に前記半導体基板の裏面に溝又は穴部をエッチングにより形成する工程とを備え、前記第2の絶縁膜及び前記剥離防止層の一部がこの溝又は穴部の中に形成されることを特徴とする請求項11、12、13のいずれか1項に記載の半導体装置の製造方法。
- 前記保護層を複数の島領域に分割する工程を備えることを特徴とする請求項11、12、13、14のいずれか1項に記載の半導体装置の製造方法。
- 前記剥離防止層は少なくとも銅層を含むことを特徴とする請求項11、12、13、14、15のいずれか1項に記載の半導体装置の製造方法。
Priority Applications (6)
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JP2004284794A JP4966487B2 (ja) | 2004-09-29 | 2004-09-29 | 半導体装置及びその製造方法 |
TW094129820A TWI305020B (en) | 2004-09-29 | 2005-08-31 | Semiconductor device and manufacturing process therefor |
KR1020050088565A KR100648122B1 (ko) | 2004-09-29 | 2005-09-23 | 반도체 장치 및 그 제조 방법 |
CNB2005101068638A CN100530609C (zh) | 2004-09-29 | 2005-09-26 | 半导体装置及其制造方法 |
US11/236,881 US7382037B2 (en) | 2004-09-29 | 2005-09-28 | Semiconductor device with a peeling prevention layer |
US12/109,800 US7906430B2 (en) | 2004-09-29 | 2008-04-25 | Method of manufacturing a semiconductor device with a peeling prevention layer |
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JP2004284794A JP4966487B2 (ja) | 2004-09-29 | 2004-09-29 | 半導体装置及びその製造方法 |
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JP2006100558A true JP2006100558A (ja) | 2006-04-13 |
JP4966487B2 JP4966487B2 (ja) | 2012-07-04 |
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JP (1) | JP4966487B2 (ja) |
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Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2006318988A (ja) * | 2005-05-10 | 2006-11-24 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP2007311771A (ja) * | 2006-04-21 | 2007-11-29 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
JP2010129577A (ja) * | 2008-11-25 | 2010-06-10 | Panasonic Corp | 半導体装置 |
JP2010129952A (ja) * | 2008-12-01 | 2010-06-10 | Nippon Telegr & Teleph Corp <Ntt> | 貫通電極配線の製造方法 |
JP2011082524A (ja) * | 2009-10-09 | 2011-04-21 | Taiwan Semiconductor Manufacturing Co Ltd | スルーシリコンビア(tsv)ワイヤボンド構造 |
JP2011193021A (ja) * | 2011-06-01 | 2011-09-29 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
JP2011249718A (ja) * | 2010-05-31 | 2011-12-08 | Panasonic Corp | 半導体装置及びその製造方法 |
JP2012033576A (ja) * | 2010-07-28 | 2012-02-16 | Sumitomo Electric Device Innovations Inc | 半導体装置及び製造方法 |
KR20160051688A (ko) * | 2013-06-29 | 2016-05-11 | 인텔 코포레이션 | 비아들과 조합되는 미세 피치 후면측 금속 재분포 라인들을 포함하는 상호접속 구조 |
WO2017150343A1 (ja) * | 2016-03-03 | 2017-09-08 | 株式会社デンソー | 半導体装置 |
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US7786592B2 (en) | 2005-06-14 | 2010-08-31 | John Trezza | Chip capacitive coupling |
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JP2006318988A (ja) * | 2005-05-10 | 2006-11-24 | Matsushita Electric Ind Co Ltd | 半導体装置 |
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Also Published As
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TWI305020B (en) | 2009-01-01 |
US7382037B2 (en) | 2008-06-03 |
CN1755916A (zh) | 2006-04-05 |
JP4966487B2 (ja) | 2012-07-04 |
TW200629442A (en) | 2006-08-16 |
KR100648122B1 (ko) | 2006-11-24 |
US7906430B2 (en) | 2011-03-15 |
US20060071342A1 (en) | 2006-04-06 |
CN100530609C (zh) | 2009-08-19 |
KR20060051564A (ko) | 2006-05-19 |
US20080254618A1 (en) | 2008-10-16 |
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