JP4376715B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP4376715B2 JP4376715B2 JP2004210188A JP2004210188A JP4376715B2 JP 4376715 B2 JP4376715 B2 JP 4376715B2 JP 2004210188 A JP2004210188 A JP 2004210188A JP 2004210188 A JP2004210188 A JP 2004210188A JP 4376715 B2 JP4376715 B2 JP 4376715B2
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- insulating film
- via hole
- semiconductor substrate
- etching
- semiconductor device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
Description
Claims (5)
- 表面に第1の絶縁膜を介してパッド電極が形成された半導体基板を準備し、
前記半導体基板の裏面の前記パッド電極に対応する位置から当該半導体基板の表面に貫通するビアホールを形成する工程と、
前記ビアホールの底部で露出する第1の絶縁膜をエッチングして除去する工程と、
前記ビアホール内を含む前記半導体基板の裏面上に第2の絶縁膜を形成する工程と、
前記ビアホールの開口部の縁から当該ビアホールの内側へ向かって突出するオーバーハング部を有する第3の絶縁膜を、前記第2の絶縁膜上に形成する工程と、
前記第3の絶縁膜をマスクとして、前記ビアホールの底部の第2の絶縁膜をエッチングして前記パッド電極を露出する工程と、
前記ビアホール内に、前記パッド電極と電気的に接続された貫通電極を形成する工程と、
前記半導体基板を複数の半導体チップに切断分離する工程と、を有することを特徴とする半導体装置の製造方法。 - 前記第3の絶縁膜は、CVD法により、非コンフォーマルな条件で成膜されることを特徴とする請求項1記載の半導体装置の製造方法。
- 表面に第1の絶縁膜を介してパッド電極が形成された半導体基板を準備し、
前記半導体基板の裏面の前記パッド電極に対応する位置から当該半導体基板の表面に貫通するビアホールを形成する工程と、
前記ビアホールの底部で露出する第1の絶縁膜をエッチングして除去する工程と、
前記ビアホール内を含む前記半導体基板の裏面上に第2の絶縁膜を形成する工程と、
前記ビアホール内を除く前記第2の絶縁膜上にスパッタ法により金属層を形成する工程と、
前記金属層をマスクとして、前記ビアホールの底部の第2の絶縁膜をエッチングして前記パッド電極を露出する工程と、
前記金属層を除去する工程と、
前記ビアホール内に、前記パッド電極と電気的に接続された貫通電極を形成する工程と、
前記半導体基板を複数の半導体チップに切断分離する工程と、を有することを特徴とする半導体装置の製造方法。 - 前記半導体基板の裏面上に、前記貫通電極と接続された配線層を形成する工程を有することを特徴とする請求項1、2、3のうちいずれか1項に記載の半導体装置の製造方法。
- 前記配線層上に導電端子を形成する工程を有することを特徴とする請求項4項記載の半導体装置の製造方法。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004210188A JP4376715B2 (ja) | 2004-07-16 | 2004-07-16 | 半導体装置の製造方法 |
TW094120550A TWI257152B (en) | 2004-07-16 | 2005-06-21 | Manufacturing method of semiconductor device |
KR1020050063547A KR100734445B1 (ko) | 2004-07-16 | 2005-07-14 | 반도체 장치의 제조 방법 |
US11/182,024 US7094701B2 (en) | 2004-07-16 | 2005-07-15 | Manufacturing method of semiconductor device |
CNB2005100846552A CN100382247C (zh) | 2004-07-16 | 2005-07-15 | 半导体装置的制造方法 |
KR1020060104894A KR100725565B1 (ko) | 2004-07-16 | 2006-10-27 | 반도체 장치의 제조 방법 |
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Application Number | Priority Date | Filing Date | Title |
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JP2004210188A JP4376715B2 (ja) | 2004-07-16 | 2004-07-16 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
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JP2006032695A JP2006032695A (ja) | 2006-02-02 |
JP4376715B2 true JP4376715B2 (ja) | 2009-12-02 |
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Application Number | Title | Priority Date | Filing Date |
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JP2004210188A Expired - Fee Related JP4376715B2 (ja) | 2004-07-16 | 2004-07-16 | 半導体装置の製造方法 |
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Country | Link |
---|---|
US (1) | US7094701B2 (ja) |
JP (1) | JP4376715B2 (ja) |
KR (2) | KR100734445B1 (ja) |
CN (1) | CN100382247C (ja) |
TW (1) | TWI257152B (ja) |
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JP4511148B2 (ja) * | 2002-10-11 | 2010-07-28 | 三洋電機株式会社 | 半導体装置の製造方法 |
JP4746847B2 (ja) * | 2004-04-27 | 2011-08-10 | 三洋電機株式会社 | 半導体装置の製造方法 |
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