KR100734445B1 - 반도체 장치의 제조 방법 - Google Patents
반도체 장치의 제조 방법 Download PDFInfo
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- KR100734445B1 KR100734445B1 KR1020050063547A KR20050063547A KR100734445B1 KR 100734445 B1 KR100734445 B1 KR 100734445B1 KR 1020050063547 A KR1020050063547 A KR 1020050063547A KR 20050063547 A KR20050063547 A KR 20050063547A KR 100734445 B1 KR100734445 B1 KR 100734445B1
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- insulating film
- via hole
- semiconductor substrate
- etching
- electrode
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 183
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 57
- 238000000034 method Methods 0.000 title claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 100
- 230000000149 penetrating effect Effects 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims description 64
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- 230000003014 reinforcing effect Effects 0.000 abstract description 15
- 239000010408 film Substances 0.000 description 198
- 239000010410 layer Substances 0.000 description 144
- 229910052751 metal Inorganic materials 0.000 description 34
- 239000002184 metal Substances 0.000 description 34
- 230000004888 barrier function Effects 0.000 description 25
- 239000011229 interlayer Substances 0.000 description 23
- 238000009413 insulation Methods 0.000 description 16
- 239000010949 copper Substances 0.000 description 15
- 230000015572 biosynthetic process Effects 0.000 description 12
- 239000000463 material Substances 0.000 description 11
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 11
- 239000011241 protective layer Substances 0.000 description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 238000004544 sputter deposition Methods 0.000 description 8
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 5
- 238000007747 plating Methods 0.000 description 5
- 238000000059 patterning Methods 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000005684 electric field Effects 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 230000002787 reinforcement Effects 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
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- H—ELECTRICITY
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (6)
- 표면에 제1 절연막을 개재하여 패드 전극이 형성된 반도체 기판을 준비하고,상기 반도체 기판의 이면의 상기 패드 전극에 대응하는 위치로부터 상기 반도체 기판의 표면을 관통하는 비아홀을 형성하는 공정과,상기 비아홀의 바닥부에서 노출되는 제1 절연막을 에칭하여 제거하는 공정과,상기 비아홀 내를 포함하는 상기 반도체 기판의 이면 상에 제2 절연막을 형성하는 공정과,상기 비아홀의 개구부의 가장자리로부터 상기 비아홀의 내측으로 향하여 돌출되는 오버행부를 갖는 제3 절연막을, 상기 제2 절연막 상에 형성하는 공정과,상기 제3 절연막을 마스크로 하여, 상기 비아홀의 바닥부의 제2 절연막을 에칭하여 상기 패드 전극을 노출시키는 공정과,상기 비아홀 내에, 상기 패드 전극과 전기적으로 접속된 관통 전극을 형성하는 공정과,상기 반도체 기판을 복수의 반도체 칩으로 절단 분리하는 공정을 갖는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제1항에 있어서,상기 제3 절연막은, CVD법에 의해, 컨포멀하지 않은 조건에서 성막되는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 표면에 제1 절연막을 개재하여 패드 전극이 형성된 반도체 기판을 준비하고,상기 반도체 기판의 이면 상에, 상기 패드 전극에 대응하는 위치에 개구부를 갖는 하드 마스크를 형성하는 공정과,상기 하드 마스크를 마스크로 하여 상기 반도체 기판을 상기 이면으로부터 에칭하여, 상기 개구부보다도 개구경이 크고, 또한 상기 이면으로부터 상기 반도체 기판의 표면을 관통하는 비아홀을 형성하는 공정과,상기 비아홀의 바닥부에서 노출되는 제1 절연막을 에칭하여 제거하는 공정과,상기 비아홀 내 및 상기 하드 마스크 상에, 상기 비아홀의 개구부의 가장자리로부터 상기 비아홀의 내측으로 향하여 돌출되는 오버행부를 갖는 제2 절연막을 형성하는 공정과,상기 하드 마스크 상의 상기 제2 절연막을 마스크로 하여, 상기 비아홀의 바닥부의 제2 절연막을 에칭하여 상기 패드 전극을 노출시키는 공정과,상기 비아홀 내에, 상기 패드 전극과 전기적으로 접속된 관통 전극을 형성하는 공정과,상기 반도체 기판을 복수의 반도체 칩으로 절단 분리하는 공정을 갖는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 삭제
- 제1항 내지 제3항 중 어느 한 항에 있어서,상기 반도체 기판의 이면 상에, 상기 관통 전극과 접속된 배선층을 형성하는 공정을 갖는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제5항에 있어서,상기 배선층 상에 도전 단자를 형성하는 공정을 갖는 것을 특징으로 하는 반도체 장치의 제조 방법.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JPJP-P-2004-00210188 | 2004-07-16 | ||
JP2004210188A JP4376715B2 (ja) | 2004-07-16 | 2004-07-16 | 半導体装置の製造方法 |
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KR1020060104894A Division KR100725565B1 (ko) | 2004-07-16 | 2006-10-27 | 반도체 장치의 제조 방법 |
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KR20060050151A KR20060050151A (ko) | 2006-05-19 |
KR100734445B1 true KR100734445B1 (ko) | 2007-07-02 |
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KR1020050063547A KR100734445B1 (ko) | 2004-07-16 | 2005-07-14 | 반도체 장치의 제조 방법 |
KR1020060104894A KR100725565B1 (ko) | 2004-07-16 | 2006-10-27 | 반도체 장치의 제조 방법 |
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Country | Link |
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US (1) | US7094701B2 (ko) |
JP (1) | JP4376715B2 (ko) |
KR (2) | KR100734445B1 (ko) |
CN (1) | CN100382247C (ko) |
TW (1) | TWI257152B (ko) |
Families Citing this family (82)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4850392B2 (ja) * | 2004-02-17 | 2012-01-11 | 三洋電機株式会社 | 半導体装置の製造方法 |
JP2005235860A (ja) | 2004-02-17 | 2005-09-02 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
JP4139803B2 (ja) * | 2004-09-28 | 2008-08-27 | シャープ株式会社 | 半導体装置の製造方法 |
TWI303864B (en) * | 2004-10-26 | 2008-12-01 | Sanyo Electric Co | Semiconductor device and method for making the same |
JP4443379B2 (ja) * | 2004-10-26 | 2010-03-31 | 三洋電機株式会社 | 半導体装置の製造方法 |
KR100618343B1 (ko) * | 2004-10-28 | 2006-08-31 | 삼성전자주식회사 | 패키징 기판의 제조방법 및 이를 이용한 패키징 방법. |
JP4873517B2 (ja) * | 2004-10-28 | 2012-02-08 | オンセミコンダクター・トレーディング・リミテッド | 半導体装置及びその製造方法 |
US7485967B2 (en) * | 2005-03-10 | 2009-02-03 | Sanyo Electric Co., Ltd. | Semiconductor device with via hole for electric connection |
US7485968B2 (en) * | 2005-08-11 | 2009-02-03 | Ziptronix, Inc. | 3D IC method and device |
JP4882350B2 (ja) * | 2005-11-22 | 2012-02-22 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
JP4812512B2 (ja) * | 2006-05-19 | 2011-11-09 | オンセミコンダクター・トレーディング・リミテッド | 半導体装置の製造方法 |
KR100761468B1 (ko) * | 2006-07-13 | 2007-09-27 | 삼성전자주식회사 | 반도체 장치 및 그 형성 방법 |
JP5103854B2 (ja) * | 2006-10-02 | 2012-12-19 | セイコーエプソン株式会社 | 半導体装置、半導体装置の製造方法、回路基板および電子機器 |
JP4380718B2 (ja) | 2007-03-15 | 2009-12-09 | ソニー株式会社 | 半導体装置の製造方法 |
US8049324B1 (en) * | 2007-05-03 | 2011-11-01 | Maxim Integrated Products, Inc. | Preventing access to stub traces on an integrated circuit package |
JP2008300718A (ja) * | 2007-06-01 | 2008-12-11 | Toshiba Corp | 半導体装置および半導体装置の製造方法 |
US7923373B2 (en) | 2007-06-04 | 2011-04-12 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
JP4937842B2 (ja) * | 2007-06-06 | 2012-05-23 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
KR100895813B1 (ko) * | 2007-06-20 | 2009-05-06 | 주식회사 하이닉스반도체 | 반도체 패키지의 제조 방법 |
KR100907896B1 (ko) * | 2007-06-22 | 2009-07-14 | 주식회사 동부하이텍 | 시스템 인 패키지의 금속 전극 형성방법 |
JP5245135B2 (ja) * | 2007-06-30 | 2013-07-24 | 株式会社ザイキューブ | 貫通導電体を有する半導体装置およびその製造方法 |
JP5302522B2 (ja) * | 2007-07-02 | 2013-10-02 | スパンション エルエルシー | 半導体装置及びその製造方法 |
US7910837B2 (en) | 2007-08-10 | 2011-03-22 | Napra Co., Ltd. | Circuit board, electronic device and method for manufacturing the same |
US7682924B2 (en) | 2007-08-13 | 2010-03-23 | Micron Technology, Inc. | Methods of forming a plurality of capacitors |
US8034702B2 (en) | 2007-08-16 | 2011-10-11 | Micron Technology, Inc. | Methods of forming through substrate interconnects |
JP5656341B2 (ja) | 2007-10-29 | 2015-01-21 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置およびその製造方法 |
TWI394260B (zh) * | 2007-10-31 | 2013-04-21 | Adl Engineering Inc | 具有多晶粒之半導體元件封裝結構及其方法 |
US8388851B2 (en) | 2008-01-08 | 2013-03-05 | Micron Technology, Inc. | Capacitor forming methods |
CN101286505B (zh) * | 2008-05-26 | 2012-06-13 | 日月光半导体制造股份有限公司 | 具有天线的半导体封装结构 |
JP2009295676A (ja) * | 2008-06-03 | 2009-12-17 | Oki Semiconductor Co Ltd | 半導体装置及びその製造方法 |
JP2009295859A (ja) * | 2008-06-06 | 2009-12-17 | Oki Semiconductor Co Ltd | 半導体装置および半導体装置の製造方法 |
JP5289830B2 (ja) | 2008-06-06 | 2013-09-11 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP5455538B2 (ja) * | 2008-10-21 | 2014-03-26 | キヤノン株式会社 | 半導体装置及びその製造方法 |
JP2010114201A (ja) * | 2008-11-05 | 2010-05-20 | Oki Semiconductor Co Ltd | 半導体装置の製造方法 |
JP5596919B2 (ja) * | 2008-11-26 | 2014-09-24 | キヤノン株式会社 | 半導体装置の製造方法 |
JP4278007B1 (ja) | 2008-11-26 | 2009-06-10 | 有限会社ナプラ | 微細空間への金属充填方法 |
US20110217832A1 (en) * | 2009-09-30 | 2011-09-08 | Digvijay Raorane | Method of filling a deep trench in a substrate |
JP5600919B2 (ja) * | 2009-10-06 | 2014-10-08 | セイコーエプソン株式会社 | 半導体装置 |
JP5718342B2 (ja) * | 2009-10-16 | 2015-05-13 | エンパイア テクノロジー ディベロップメント エルエルシー | 半導体ウェーハにフィルムを付加する装置および方法ならびに半導体ウェーハを処理する方法 |
FR2950732A1 (fr) * | 2009-11-27 | 2011-04-01 | Commissariat Energie Atomique | Procede ameliore de remplissage d'une cavite pratiquee dans un substrat et ayant un rapport de forme eleve |
US20110207323A1 (en) * | 2010-02-25 | 2011-08-25 | Robert Ditizio | Method of forming and patterning conformal insulation layer in vias and etched structures |
US9257274B2 (en) | 2010-04-15 | 2016-02-09 | Lam Research Corporation | Gapfill of variable aspect ratio features with a composite PEALD and PECVD method |
FR2959866A1 (fr) * | 2010-05-06 | 2011-11-11 | St Microelectronics Crolles 2 | Procede de realisation d'au moins une liaison traversante electriquement conductrice au sein d'un substrat semi-conducteur dans un circuit integre et circuit integre correspondant. |
KR101097628B1 (ko) * | 2010-06-21 | 2011-12-22 | 삼성전기주식회사 | 인쇄회로기판 및 이의 제조방법 |
US8518788B2 (en) | 2010-08-11 | 2013-08-27 | Micron Technology, Inc. | Methods of forming a plurality of capacitors |
TWI500132B (zh) * | 2010-11-23 | 2015-09-11 | Xintec Inc | 半導體裝置之製法、基材穿孔製程及其結構 |
US8901701B2 (en) * | 2011-02-10 | 2014-12-02 | Chia-Sheng Lin | Chip package and fabrication method thereof |
KR101801137B1 (ko) | 2011-02-21 | 2017-11-24 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
JP2012227328A (ja) | 2011-04-19 | 2012-11-15 | Sony Corp | 半導体装置、半導体装置の製造方法、固体撮像装置及び電子機器 |
KR20130034261A (ko) * | 2011-09-28 | 2013-04-05 | 에스케이하이닉스 주식회사 | 반도체 장치의 제조방법 |
JP5957840B2 (ja) * | 2011-10-04 | 2016-07-27 | ソニー株式会社 | 半導体装置の製造方法 |
US9076680B2 (en) | 2011-10-18 | 2015-07-07 | Micron Technology, Inc. | Integrated circuitry, methods of forming capacitors, and methods of forming integrated circuitry comprising an array of capacitors and circuitry peripheral to the array |
JP2013131600A (ja) * | 2011-12-21 | 2013-07-04 | Seiko Epson Corp | 半導体装置の製造方法、半導体装置、センサー及び電子機器 |
US8946043B2 (en) | 2011-12-21 | 2015-02-03 | Micron Technology, Inc. | Methods of forming capacitors |
KR101896517B1 (ko) | 2012-02-13 | 2018-09-07 | 삼성전자주식회사 | 관통전극을 갖는 반도체 소자 및 그 제조방법 |
KR101867961B1 (ko) | 2012-02-13 | 2018-06-15 | 삼성전자주식회사 | 관통전극을 갖는 반도체 소자 및 그 제조방법 |
FR2987937B1 (fr) * | 2012-03-12 | 2014-03-28 | Altatech Semiconductor | Procede de realisation de plaquettes semi-conductrices |
JP5984134B2 (ja) | 2012-05-15 | 2016-09-06 | ローム株式会社 | 半導体装置およびその製造方法、電子部品 |
US8652926B1 (en) | 2012-07-26 | 2014-02-18 | Micron Technology, Inc. | Methods of forming capacitors |
JP5655825B2 (ja) * | 2012-07-30 | 2015-01-21 | セイコーエプソン株式会社 | 半導体装置、半導体装置の製造方法、回路基板および電子機器 |
KR102031908B1 (ko) | 2013-02-06 | 2019-10-14 | 삼성전자주식회사 | 관통 전극을 갖는 반도체 소자 및 그 형성 방법 |
US10083893B2 (en) | 2014-01-30 | 2018-09-25 | Toshiba Memory Corporation | Semiconductor device and semiconductor device manufacturing method |
JP6081387B2 (ja) * | 2014-01-30 | 2017-02-15 | 株式会社東芝 | 半導体装置および半導体装置の製造方法 |
FR3018151A1 (fr) * | 2014-07-04 | 2015-09-04 | Commissariat Energie Atomique | Procede de realisation d'un niveau d'interconnexion electrique |
JP5871038B2 (ja) * | 2014-08-19 | 2016-03-01 | セイコーエプソン株式会社 | 半導体装置及び電子デバイス |
KR102411064B1 (ko) | 2015-03-10 | 2022-06-21 | 삼성전자주식회사 | 관통전극을 갖는 반도체 소자 및 그의 제조방법 |
JP2016225471A (ja) | 2015-05-29 | 2016-12-28 | 株式会社東芝 | 半導体装置および半導体装置の製造方法 |
JP6479578B2 (ja) * | 2015-05-29 | 2019-03-06 | 東芝メモリ株式会社 | 半導体装置の製造方法および半導体装置 |
CN106328579B (zh) * | 2015-06-24 | 2019-09-27 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的形成方法 |
US9953941B2 (en) | 2015-08-25 | 2018-04-24 | Invensas Bonding Technologies, Inc. | Conductive barrier direct hybrid bonding |
JP2018157110A (ja) * | 2017-03-17 | 2018-10-04 | 東芝メモリ株式会社 | 半導体装置およびその製造方法 |
JP7069586B2 (ja) * | 2017-04-27 | 2022-05-18 | セイコーエプソン株式会社 | Mems素子、電子機器および移動体 |
JP7005988B2 (ja) * | 2017-04-27 | 2022-01-24 | セイコーエプソン株式会社 | Mems素子、電子機器および移動体 |
CN110998790A (zh) | 2017-08-04 | 2020-04-10 | 朗姆研究公司 | 在水平表面上的选择性沉积SiN |
US10763108B2 (en) | 2017-08-18 | 2020-09-01 | Lam Research Corporation | Geometrically selective deposition of a dielectric film |
EP3460835B1 (en) * | 2017-09-20 | 2020-04-01 | ams AG | Method for manufacturing a semiconductor device and semiconductor device |
CN108022898A (zh) * | 2017-12-29 | 2018-05-11 | 苏州晶方半导体科技股份有限公司 | 一种半导体器件及其制作方法 |
JP2019153694A (ja) * | 2018-03-02 | 2019-09-12 | 東芝メモリ株式会社 | 半導体装置およびその製造方法 |
JP7278184B2 (ja) * | 2019-09-13 | 2023-05-19 | キオクシア株式会社 | 半導体装置の製造方法 |
US11289370B2 (en) | 2020-03-02 | 2022-03-29 | Nanya Technology Corporation | Liner for through-silicon via |
US11482506B2 (en) * | 2020-03-31 | 2022-10-25 | Taiwan Semiconductor Manufacturing Company Limited | Edge-trimming methods for wafer bonding and dicing |
US11652025B2 (en) | 2021-01-15 | 2023-05-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-substrate via formation to enlarge electrochemical plating window |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003309221A (ja) * | 2002-04-15 | 2003-10-31 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH03163835A (ja) * | 1989-11-21 | 1991-07-15 | Nec Corp | バイアホール電極構造 |
EP1050905B1 (en) * | 1999-05-07 | 2017-06-21 | Shinko Electric Industries Co. Ltd. | Method of producing a semiconductor device with insulating layer |
JP3544340B2 (ja) * | 1999-05-07 | 2004-07-21 | 新光電気工業株式会社 | 半導体装置の製造方法 |
US6451705B1 (en) * | 2000-08-31 | 2002-09-17 | Micron Technology, Inc. | Self-aligned PECVD etch mask |
JP2003045877A (ja) * | 2001-08-01 | 2003-02-14 | Sharp Corp | 半導体装置およびその製造方法 |
JP2003258156A (ja) * | 2002-03-05 | 2003-09-12 | Ngk Spark Plug Co Ltd | 配線基板 |
TWI229435B (en) * | 2002-06-18 | 2005-03-11 | Sanyo Electric Co | Manufacture of semiconductor device |
JP4511148B2 (ja) * | 2002-10-11 | 2010-07-28 | 三洋電機株式会社 | 半導体装置の製造方法 |
JP4746847B2 (ja) * | 2004-04-27 | 2011-08-10 | 三洋電機株式会社 | 半導体装置の製造方法 |
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TW200605281A (en) | 2006-02-01 |
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