FR2987937B1 - Procede de realisation de plaquettes semi-conductrices - Google Patents
Procede de realisation de plaquettes semi-conductricesInfo
- Publication number
- FR2987937B1 FR2987937B1 FR1200753A FR1200753A FR2987937B1 FR 2987937 B1 FR2987937 B1 FR 2987937B1 FR 1200753 A FR1200753 A FR 1200753A FR 1200753 A FR1200753 A FR 1200753A FR 2987937 B1 FR2987937 B1 FR 2987937B1
- Authority
- FR
- France
- Prior art keywords
- semiconductor wafers
- making semiconductor
- making
- wafers
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title 1
- 235000012431 wafers Nutrition 0.000 title 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1200753A FR2987937B1 (fr) | 2012-03-12 | 2012-03-12 | Procede de realisation de plaquettes semi-conductrices |
DE112013001383.5T DE112013001383T5 (de) | 2012-03-12 | 2013-03-08 | Verfahren zur Herstellung von Halbleiterwafern |
US14/382,731 US20150031202A1 (en) | 2012-03-12 | 2013-03-08 | Method for manufacturing semiconductor wafers |
CN201380013617.0A CN104247004A (zh) | 2012-03-12 | 2013-03-08 | 半导体晶片的制作方法 |
KR1020147028221A KR20150013445A (ko) | 2012-03-12 | 2013-03-08 | 반도체 웨이퍼들을 제조하기 위한 방법 |
PCT/FR2013/050491 WO2013135999A1 (fr) | 2012-03-12 | 2013-03-08 | Procédé de réalisation de plaquettes semi-conductrices |
SG11201405664PA SG11201405664PA (en) | 2012-03-12 | 2013-03-08 | Method for manufacturing semiconductor wafers |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1200753A FR2987937B1 (fr) | 2012-03-12 | 2012-03-12 | Procede de realisation de plaquettes semi-conductrices |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2987937A1 FR2987937A1 (fr) | 2013-09-13 |
FR2987937B1 true FR2987937B1 (fr) | 2014-03-28 |
Family
ID=47002907
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1200753A Active FR2987937B1 (fr) | 2012-03-12 | 2012-03-12 | Procede de realisation de plaquettes semi-conductrices |
Country Status (7)
Country | Link |
---|---|
US (1) | US20150031202A1 (fr) |
KR (1) | KR20150013445A (fr) |
CN (1) | CN104247004A (fr) |
DE (1) | DE112013001383T5 (fr) |
FR (1) | FR2987937B1 (fr) |
SG (1) | SG11201405664PA (fr) |
WO (1) | WO2013135999A1 (fr) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105140267A (zh) * | 2015-07-29 | 2015-12-09 | 浙江大学 | 半导体衬底及选择性生长半导体的方法 |
US10096516B1 (en) * | 2017-08-18 | 2018-10-09 | Applied Materials, Inc. | Method of forming a barrier layer for through via applications |
DE102019006097A1 (de) * | 2019-08-29 | 2021-03-04 | Azur Space Solar Power Gmbh | Passivierungsverfahren für ein Durchgangsloch einer Halbleiterscheibe |
US11289370B2 (en) | 2020-03-02 | 2022-03-29 | Nanya Technology Corporation | Liner for through-silicon via |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5807785A (en) * | 1996-08-02 | 1998-09-15 | Applied Materials, Inc. | Low dielectric constant silicon dioxide sandwich layer |
US6114216A (en) * | 1996-11-13 | 2000-09-05 | Applied Materials, Inc. | Methods for shallow trench isolation |
US20050136684A1 (en) | 2003-12-23 | 2005-06-23 | Applied Materials, Inc. | Gap-fill techniques |
JP4376715B2 (ja) * | 2004-07-16 | 2009-12-02 | 三洋電機株式会社 | 半導体装置の製造方法 |
US7429529B2 (en) * | 2005-08-05 | 2008-09-30 | Farnworth Warren M | Methods of forming through-wafer interconnects and structures resulting therefrom |
WO2008083284A2 (fr) * | 2006-12-29 | 2008-07-10 | Cufer Asset Ltd. L.L.C. | Tranche traitée au niveau de l'extrémité frontale ayant des connexions traversant les puces |
KR100840665B1 (ko) * | 2007-05-18 | 2008-06-24 | 주식회사 동부하이텍 | 반도체 소자의 제조방법 및 이를 이용한 시스템 인 패키지 |
CN101728283A (zh) * | 2008-10-16 | 2010-06-09 | 上海华虹Nec电子有限公司 | 芯片互联工艺中芯片互联通孔的制备方法 |
CN102054752A (zh) * | 2009-11-03 | 2011-05-11 | 中芯国际集成电路制造(上海)有限公司 | 硅通孔制作方法 |
US20120015113A1 (en) * | 2010-07-13 | 2012-01-19 | Applied Materials, Inc. | Methods for forming low stress dielectric films |
FR2963024B1 (fr) | 2010-07-26 | 2016-12-23 | Altatech Semiconductor | Reacteur de depot chimique en phase gazeuse ameliore |
US8487410B2 (en) * | 2011-04-13 | 2013-07-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-silicon vias for semicondcutor substrate and method of manufacture |
-
2012
- 2012-03-12 FR FR1200753A patent/FR2987937B1/fr active Active
-
2013
- 2013-03-08 CN CN201380013617.0A patent/CN104247004A/zh active Pending
- 2013-03-08 WO PCT/FR2013/050491 patent/WO2013135999A1/fr active Application Filing
- 2013-03-08 US US14/382,731 patent/US20150031202A1/en not_active Abandoned
- 2013-03-08 KR KR1020147028221A patent/KR20150013445A/ko not_active Application Discontinuation
- 2013-03-08 DE DE112013001383.5T patent/DE112013001383T5/de not_active Withdrawn
- 2013-03-08 SG SG11201405664PA patent/SG11201405664PA/en unknown
Also Published As
Publication number | Publication date |
---|---|
DE112013001383T5 (de) | 2014-11-27 |
CN104247004A (zh) | 2014-12-24 |
WO2013135999A1 (fr) | 2013-09-19 |
US20150031202A1 (en) | 2015-01-29 |
FR2987937A1 (fr) | 2013-09-13 |
KR20150013445A (ko) | 2015-02-05 |
SG11201405664PA (en) | 2014-10-30 |
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Owner name: UNITY SEMICONDUCTOR, FR Effective date: 20180330 |
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Owner name: KOBUS SAS, FR Effective date: 20180720 |
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