JP2006032695A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 187
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 58
- 238000000034 method Methods 0.000 title claims abstract description 57
- 239000000758 substrate Substances 0.000 claims abstract description 104
- 238000005530 etching Methods 0.000 claims abstract description 73
- 229910052751 metal Inorganic materials 0.000 claims description 36
- 239000002184 metal Substances 0.000 claims description 36
- 230000000149 penetrating effect Effects 0.000 claims description 9
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- 230000002787 reinforcement Effects 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 141
- 230000004888 barrier function Effects 0.000 description 25
- 239000011229 interlayer Substances 0.000 description 21
- 239000010949 copper Substances 0.000 description 15
- 230000015572 biosynthetic process Effects 0.000 description 13
- 230000003014 reinforcing effect Effects 0.000 description 13
- 239000000463 material Substances 0.000 description 11
- 238000009413 insulation Methods 0.000 description 10
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 10
- 239000011241 protective layer Substances 0.000 description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 238000004544 sputter deposition Methods 0.000 description 8
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 6
- 238000007747 plating Methods 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 5
- 238000000059 patterning Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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Abstract
【解決手段】 パッド電極11に対応した位置で半導体基板10を貫通するビアホール16を形成する。次に、ビアホール16を含む半導体基板10の裏面上に絶縁膜17を形成する。次に、半導体基板10の裏面上に、ビアホール16の開口部の縁でオーバーハング部18aを有する補強用絶縁膜18を形成する。そして、補強用絶縁膜18をマスクとして、ビアホール16の側壁の絶縁膜17を残存させつつ、当該底部の絶縁膜17をエッチングして除去する。次に、ビアホール16を含む半導体基板10の裏面に、貫通電極21、配線層22、及び導電端子24を形成する。最後に、ダイシングにより半導体基板10を半導体チップ10Aに切断分離する。
【選択図】 図9
Description
Claims (6)
- 表面に第1の絶縁膜を介してパッド電極が形成された半導体基板を準備し、
前記半導体基板の裏面の前記パッド電極に対応する位置から当該半導体基板の表面に貫通するビアホールを形成する工程と、
前記ビアホールの底部で露出する第1の絶縁膜をエッチングして除去する工程と、
前記ビアホール内を含む前記半導体基板の裏面上に第2の絶縁膜を形成する工程と、
前記ビアホールの開口部の縁から当該ビアホールの内側へ向かって突出するオーバーハング部を有する第3の絶縁膜を、前記第2の絶縁膜上に形成する工程と、
前記第3の絶縁膜をマスクとして、前記ビアホールの底部の第2の絶縁膜をエッチングして前記パッド電極を露出する工程と、
前記ビアホール内に、前記パッド電極と電気的に接続された貫通電極を形成する工程と、
前記半導体基板を複数の半導体チップに切断分離する工程と、を有することを特徴とする半導体装置の製造方法。 - 前記第3の絶縁膜は、CVD法により、非コンフォーマルな条件で成膜されることを特徴とする請求項1記載の半導体装置の製造方法。
- 表面に第1の絶縁膜を介してパッド電極が形成された半導体基板を準備し、
前記半導体基板の裏面上に、前記パッド電極に対応する位置に開口部を有したハードマスクを形成する工程と、
前記ハードマスクをマスクとして前記半導体基板を当該裏面からエッチングして、前記開口部よりも開口径が大きく、かつ当該裏面から当該半導体基板の表面に貫通するビアホールを形成する工程と、
前記ビアホールの底部で露出する第1の絶縁膜をエッチングして除去する工程と、
前記ビアホール内及び前記ハードマスク上に、前記ビアホールの開口部の縁から当該ビアホールの内側へ向かって突出するオーバーハング部を有する第2の絶縁膜を形成する工程と、
前記ハードマスク上の前記第2の絶縁膜をマスクとして、前記ビアホールの底部の第2の絶縁膜をエッチングして前記パッド電極を露出する工程と、
前記ビアホール内に、前記パッド電極と電気的に接続された貫通電極を形成する工程と、
前記半導体基板を複数の半導体チップに切断分離する工程と、を有することを特徴とする半導体装置の製造方法。 - 表面に第1の絶縁膜を介してパッド電極が形成された半導体基板を準備し、
前記半導体基板の裏面の前記パッド電極に対応する位置から当該半導体基板の表面に貫通するビアホールを形成する工程と、
前記ビアホールの底部で露出する第1の絶縁膜をエッチングして除去する工程と、
前記ビアホール内を含む前記半導体基板の裏面上に第2の絶縁膜を形成する工程と、
前記ビアホール内を除く前記第2の絶縁膜上に金属層を形成する工程と、
前記金属層をマスクとして、前記ビアホールの底部の第2の絶縁膜をエッチングして前記パッド電極を露出する工程と、
前記金属層を除去する工程と、
前記ビアホール内に、前記パッド電極と電気的に接続された貫通電極を形成する工程と、
前記半導体基板を複数の半導体チップに切断分離する工程と、を有することを特徴とする半導体装置の製造方法。 - 前記半導体基板の裏面上に、前記貫通電極と接続された配線層を形成する工程を有することを特徴とする請求項1,2,3,4のうちいずれか1項に記載の半導体装置の製造方法。
- 前記配線層上に導電端子を形成する工程を有することを特徴とする請求項5項記載の半導体装置の製造方法。
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JP2004210188A JP4376715B2 (ja) | 2004-07-16 | 2004-07-16 | 半導体装置の製造方法 |
TW094120550A TWI257152B (en) | 2004-07-16 | 2005-06-21 | Manufacturing method of semiconductor device |
KR1020050063547A KR100734445B1 (ko) | 2004-07-16 | 2005-07-14 | 반도체 장치의 제조 방법 |
US11/182,024 US7094701B2 (en) | 2004-07-16 | 2005-07-15 | Manufacturing method of semiconductor device |
CNB2005100846552A CN100382247C (zh) | 2004-07-16 | 2005-07-15 | 半导体装置的制造方法 |
KR1020060104894A KR100725565B1 (ko) | 2004-07-16 | 2006-10-27 | 반도체 장치의 제조 방법 |
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JP (1) | JP4376715B2 (ja) |
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Cited By (39)
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JP2007142309A (ja) * | 2005-11-22 | 2007-06-07 | Seiko Epson Corp | 半導体装置の製造方法 |
JP2008091628A (ja) * | 2006-10-02 | 2008-04-17 | Seiko Epson Corp | 半導体装置、半導体装置の製造方法、回路基板および電子機器 |
JP2008300718A (ja) * | 2007-06-01 | 2008-12-11 | Toshiba Corp | 半導体装置および半導体装置の製造方法 |
JP2008305897A (ja) * | 2007-06-06 | 2008-12-18 | Renesas Technology Corp | 半導体装置およびその製造方法 |
JP2009004722A (ja) * | 2007-06-20 | 2009-01-08 | Hynix Semiconductor Inc | 半導体パッケージの製造方法 |
JP2009016406A (ja) * | 2007-06-30 | 2009-01-22 | Zycube:Kk | 貫通導電体を有する半導体装置およびその製造方法 |
JP2009295859A (ja) * | 2008-06-06 | 2009-12-17 | Oki Semiconductor Co Ltd | 半導体装置および半導体装置の製造方法 |
JP2009295676A (ja) * | 2008-06-03 | 2009-12-17 | Oki Semiconductor Co Ltd | 半導体装置及びその製造方法 |
JP2010114201A (ja) * | 2008-11-05 | 2010-05-20 | Oki Semiconductor Co Ltd | 半導体装置の製造方法 |
JP2010537405A (ja) * | 2007-08-13 | 2010-12-02 | マイクロン テクノロジー, インク. | 複数のキャパシタを形成する方法 |
US7910837B2 (en) | 2007-08-10 | 2011-03-22 | Napra Co., Ltd. | Circuit board, electronic device and method for manufacturing the same |
JP2011082291A (ja) * | 2009-10-06 | 2011-04-21 | Seiko Epson Corp | 半導体装置 |
US8004090B2 (en) | 2007-10-29 | 2011-08-23 | Elpida Memory, Inc | Semiconductor device and method for manufacturing the same |
US8079131B2 (en) | 2008-11-26 | 2011-12-20 | Napra Co., Ltd. | Method for filling metal into fine space |
JP2012235158A (ja) * | 2012-07-30 | 2012-11-29 | Seiko Epson Corp | 半導体装置、半導体装置の製造方法、回路基板および電子機器 |
US8388851B2 (en) | 2008-01-08 | 2013-03-05 | Micron Technology, Inc. | Capacitor forming methods |
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Also Published As
Publication number | Publication date |
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CN100382247C (zh) | 2008-04-16 |
TW200605281A (en) | 2006-02-01 |
CN1722370A (zh) | 2006-01-18 |
KR100734445B1 (ko) | 2007-07-02 |
TWI257152B (en) | 2006-06-21 |
US7094701B2 (en) | 2006-08-22 |
KR100725565B1 (ko) | 2007-06-07 |
US20060024966A1 (en) | 2006-02-02 |
KR20060115986A (ko) | 2006-11-13 |
KR20060050151A (ko) | 2006-05-19 |
JP4376715B2 (ja) | 2009-12-02 |
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