JP2016225474A - 半導体装置の製造方法および半導体装置 - Google Patents
半導体装置の製造方法および半導体装置 Download PDFInfo
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Abstract
【解決手段】実施形態にかかる半導体装置1は、貫通孔180Hが設けられた半導体基板11と、下層配線122を含むデバイス層12と、デバイス層12を覆う絶縁層13と、絶縁層13を貫通する第1貫通電極14と、半導体基板11の貫通孔180Hの開口径と実質的に同じかもしくは大きな径の開口が設けられた第1絶縁膜171/172と、第1絶縁膜171/172上から半導体基板11の貫通孔180Hの内側面に位置する第2絶縁膜173と、第2絶縁膜173上から半導体基板11の貫通孔180H内を経てデバイス層12中の下層配線122と電気的に接続する第2貫通電極18とを備えてもよい。
【選択図】図1
Description
Claims (6)
- 第1面に配線を含むデバイス層と前記デバイス層を覆う絶縁層と前記絶縁層を貫通する第1貫通電極とが形成された半導体基板における前記第1面とは反対側の第2面上に、第1絶縁膜を形成する工程と、
前記第1絶縁膜が形成された前記半導体基板を前記第2面側から異方性ドライエッチングにより彫り込むことで前記デバイス層を露出させる貫通孔を形成する工程と、
前記貫通孔の開口端部分の前記第1絶縁膜をエッチングにより除去する工程と、
前記第1絶縁膜上と前記貫通孔の内側面および底面とに第2絶縁膜を形成する工程と、
前記貫通孔の前記底面に形成された前記第2絶縁膜および前記デバイス層における第3絶縁膜を除去することで前記デバイス層の前記配線を露出させる工程と、
前記第2絶縁膜上から前記貫通孔内を経て前記デバイス層中の前記配線と電気的に接続する第2貫通電極を形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記第1絶縁膜は、前記半導体基板の前記第2面上に位置するシリコン酸化膜を含むことを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第2貫通電極は、
前記第2絶縁膜上から前記貫通孔内側面を経て前記デバイス層中の前記配線と接触する第1メタル層と、
前記第1メタル層上に形成された第2メタル層と、
前記第2メタル層上に形成された第3メタル層と、
を含むことを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記半導体基板の厚さ方向において前記前記第1絶縁膜とオーバラップする領域が残るように前記1メタル層と前記第2メタル層とをパターニングする工程をさらに含むことを特徴とする請求項3に記載の半導体装置の製造方法。
- 前記第1絶縁膜を形成する前に前記半導体基板を50マイクロメートル以下に薄厚化する工程をさらに含むことを特徴とする請求項1に記載の半導体装置の製造方法。
- 第1面から前記第1面とは反対側の第2面まで貫通する貫通孔が設けられた半導体基板と、
前記半導体基板の前記第1面に位置し、配線を含むデバイス層と、
前記デバイス層を覆う絶縁層と、
前記絶縁層を貫通する第1貫通電極と、
前記半導体基板の前記第2面上に位置し、前記半導体基板の前記貫通孔の開口径と実質的に同じかもしくは大きな径の開口が設けられた第1絶縁膜と、
前記第1絶縁膜上から前記半導体基板の前記貫通孔の内側面に位置する第2絶縁膜と、
前記第2絶縁膜上から前記半導体基板の前記貫通孔内を経て前記デバイス層中の前記配線と電気的に接続する第2貫通電極と、
を備えることを特徴とする半導体装置。
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JP2015110789A JP6479578B2 (ja) | 2015-05-29 | 2015-05-29 | 半導体装置の製造方法および半導体装置 |
TW104139211A TWI579968B (zh) | 2015-05-29 | 2015-11-25 | 半導體裝置之製造方法及半導體裝置 |
CN201510848888.9A CN106206416B (zh) | 2015-05-29 | 2015-11-27 | 半导体装置的制造方法以及半导体装置 |
US15/061,659 US10204862B2 (en) | 2015-05-29 | 2016-03-04 | Method of manufacturing semiconductor device, and semiconductor device |
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JP2018170363A (ja) * | 2017-03-29 | 2018-11-01 | 東芝メモリ株式会社 | 半導体装置の製造方法及び半導体装置 |
US11043419B2 (en) | 2018-09-05 | 2021-06-22 | Toshiba Memory Corporation | Semiconductor device and manufacturing method thereof |
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006032695A (ja) * | 2004-07-16 | 2006-02-02 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JP2009158862A (ja) * | 2007-12-27 | 2009-07-16 | Toshiba Corp | 半導体パッケージ |
JP2010232661A (ja) * | 2009-03-27 | 2010-10-14 | Taiwan Semiconductor Manufacturing Co Ltd | ビア構造とそれを形成するビアエッチングプロセス |
JP2013520830A (ja) * | 2010-02-25 | 2013-06-06 | エスピーティーエス テクノロジーズ リミティド | ビア及びエッチングされた構造におけるコンフォーマル絶縁層の形成方法及びパターン形成方法 |
JP2014011309A (ja) * | 2012-06-29 | 2014-01-20 | Ps4 Luxco S A R L | 半導体装置およびその製造方法 |
JP2015002299A (ja) * | 2013-06-17 | 2015-01-05 | 株式会社ザイキューブ | 漏斗状の貫通電極およびその製造方法 |
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JP5656341B2 (ja) * | 2007-10-29 | 2015-01-21 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置およびその製造方法 |
JP2012142414A (ja) | 2010-12-28 | 2012-07-26 | Panasonic Corp | 半導体装置及びその製造方法並びにそれを用いた積層型半導体装置 |
JP2012231096A (ja) | 2011-04-27 | 2012-11-22 | Elpida Memory Inc | 半導体装置及びその製造方法 |
JP2015041691A (ja) * | 2013-08-21 | 2015-03-02 | 株式会社東芝 | 半導体装置および半導体装置の製造方法 |
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Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006032695A (ja) * | 2004-07-16 | 2006-02-02 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JP2009158862A (ja) * | 2007-12-27 | 2009-07-16 | Toshiba Corp | 半導体パッケージ |
JP2010232661A (ja) * | 2009-03-27 | 2010-10-14 | Taiwan Semiconductor Manufacturing Co Ltd | ビア構造とそれを形成するビアエッチングプロセス |
JP2013520830A (ja) * | 2010-02-25 | 2013-06-06 | エスピーティーエス テクノロジーズ リミティド | ビア及びエッチングされた構造におけるコンフォーマル絶縁層の形成方法及びパターン形成方法 |
JP2014011309A (ja) * | 2012-06-29 | 2014-01-20 | Ps4 Luxco S A R L | 半導体装置およびその製造方法 |
JP2015002299A (ja) * | 2013-06-17 | 2015-01-05 | 株式会社ザイキューブ | 漏斗状の貫通電極およびその製造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2018170363A (ja) * | 2017-03-29 | 2018-11-01 | 東芝メモリ株式会社 | 半導体装置の製造方法及び半導体装置 |
US11043419B2 (en) | 2018-09-05 | 2021-06-22 | Toshiba Memory Corporation | Semiconductor device and manufacturing method thereof |
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CN106206416A (zh) | 2016-12-07 |
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CN106206416B (zh) | 2019-05-10 |
US20160351503A1 (en) | 2016-12-01 |
US10204862B2 (en) | 2019-02-12 |
TW201642391A (zh) | 2016-12-01 |
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