JP2015041691A - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

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Publication number
JP2015041691A
JP2015041691A JP2013171746A JP2013171746A JP2015041691A JP 2015041691 A JP2015041691 A JP 2015041691A JP 2013171746 A JP2013171746 A JP 2013171746A JP 2013171746 A JP2013171746 A JP 2013171746A JP 2015041691 A JP2015041691 A JP 2015041691A
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Prior art keywords
integrated circuit
semiconductor substrate
semiconductor device
etching
thickness direction
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Abandoned
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JP2013171746A
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Inventor
貴士 白野
Takashi Shirono
貴士 白野
東　和幸
Kazuyuki Azuma
和幸 東
渡辺　慎也
Shinya Watanabe
慎也 渡辺
達夫 右田
Tatsuo Uda
達夫 右田
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Toshiba Corp
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Toshiba Corp
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Priority to JP2013171746A priority Critical patent/JP2015041691A/ja
Priority to TW103100074A priority patent/TW201508889A/zh
Priority to CN201410016445.9A priority patent/CN104425295A/zh
Priority to US14/194,776 priority patent/US20150054172A1/en
Publication of JP2015041691A publication Critical patent/JP2015041691A/ja
Abandoned legal-status Critical Current

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Abstract

【課題】ＴＳＶと集積回路との接触抵抗を低減することができる半導体装置および半導体装置の製造方法を提供すること。
【解決手段】本発明の一つの実施形態に係る半導体装置は、集積回路と導電性部材とを備える。集積回路は、半導体基板における一方の面側に設けられる。導電性部材は、半導体基板を厚さ方向に貫通して集積回路と接続され、集積回路との接触部における半導体基板の厚さ方向に対して垂直な方向の寸法が、半導体基板を貫通する貫通部における半導体基板の厚さ方向に対して垂直な方向の寸法よりも大きいビアに埋め込まれる。
【選択図】図１

Description

本発明の実施形態は、半導体装置および半導体装置の製造方法に関する。
従来、集積回路が形成された複数の半導体チップを積層し、各半導体チップをＴＳＶ（Through Silicon Via）によって互いに電気的に接続することにより、半導体装置の専有面積を小さくする技術がある。ＴＳＶは、一方の面側に集積回路が形成された半導体基板を厚さ方向に貫通して集積回路まで到達する貫通孔を形成し、貫通孔に導電性部材を埋め込むことによって形成される。
かかるＴＳＶは、半導体チップの小型化および集積回路の高集積化に伴い、半導体基板の厚さ方向に対して垂直な断面の面積が微小化する傾向にある。このように、ＴＳＶの断面が微小化すると、ＴＳＶと集積回路との間の接触抵抗が増大するという問題が生じる。
米国特許出願公開第２０１３／０９９３４９号明細書
本発明の一つの実施形態は、ＴＳＶと集積回路との接触抵抗を低減することができる半導体装置および半導体装置の製造方法を提供することを目的とする。
本発明の一つの実施形態によれば、半導体装置が提供される。半導体装置は、集積回路と導電性部材とを備える。集積回路は、半導体基板における一方の面側に設けられる。導電性部材は、前記半導体基板を厚さ方向に貫通して前記集積回路と接続され、前記集積回路との接触部における前記厚さ方向に対して垂直な方向の寸法が、前記半導体基板を貫通する貫通部における前記厚さ方向に対して垂直な方向の寸法よりも大きいビアに埋め込まれる。
実施形態に係る半導体装置を示す断面模式図。 実施形態に係る半導体装置の製造工程を示す断面模式図。 実施形態に係る半導体装置の製造工程を示す断面模式図。 実施形態に係る半導体装置の製造工程を示す断面模式図。 実施形態に係る半導体装置の製造工程を示す断面模式図。
以下に添付図面を参照して、実施形態にかかる半導体装置および半導体装置の製造方法を詳細に説明する。なお、この実施形態により本発明が限定されるものではない。
図１は、実施形態に係る半導体装置を示す断面模式図である。図１に示すように、実施形態に係る半導体装置１は、例えば、シリコンウェハ等の半導体基板２における一方の面（以下、「表面」と記載する）側に設けられる集積回路３と、半導体基板２を厚さ方向に貫通して集積回路３と接続されるビア４とを備える。
集積回路３は、半導体基板２の表面に形成される層間絶縁膜３０の内部に設けられる。層間絶縁膜３０は、例えば、酸化シリコンによって形成される。かかる集積回路３は、例えば、半導体メモリおよび多層配線を含むＬＳＩ（Large Scale Integration）である。なお、図１には、集積回路３における多層配線の部分を選択的に図示している。
また、集積回路３の表面には、パッシベーション膜５１と保護膜５２とが積層される。パッシベーション膜５１は、例えば、酸化シリコンまたは窒化シリコンによって形成される。保護膜５２は、例えば、ＰＥＴ（ポリエチレンテレフタレート）またはポリイミドなどの樹脂によって形成される。
保護膜５２の表面における所定位置には、上部電極パッド５４が設けられる。上部電極パッド５４は、例えば、金によって形成される。上部電極パッド５４と集積回路３とは、保護膜５２、パッシベーション膜５１、および層間絶縁膜３０を貫通する上部電極５３によって接続される。上部電極５３は、例えば、ニッケルによって形成される。
ビア４は、半導体基板２を貫通するように設けられ、半導体装置１を多段に積層する場合に、下段の半導体装置１が備える集積回路３と上段の半導体装置１が備える集積回路３とを電気的に接続する貫通電極（ＴＳＶ：Through Silicon Via）である。かかるビア４は、例えば、銅によって形成される。
ビア４における半導体基板２の裏面側に露出した端部には、下段の半導体装置１の上部電極パッド５４と導通を取るためのバンプ５５が設けられる。バンプ５５は、例えば、はんだによって形成される。
ここで、一般的なビアは、半導体基板を貫通する円柱状の導電性部材である。このため、円柱状のビアは、半導体装置の小型化および集積回路の高集積化が進んだ場合、径が小さくなり、集積回路との接触面積が小さくなるので、集積回路との接触抵抗が増大する。
そこで、本実施形態に係るビア４は、集積回路３との接触部４２における半導体基板２の厚さ方向に対して垂直な方向の寸法が、半導体基板２を貫通する貫通部４１における半導体基板２の厚さ方向に対して垂直な方向の寸法よりも大きくなるように形成される。
かかるビア４によれば、半導体装置１の小型化、集積回路３の高集積化に伴って、貫通部４１が細く形成されても、貫通部４１よりも断面積が大きな接触部４２によって集積回路３との接続が可能となるので、集積回路３との間の接触抵抗を低減することができる。
また、ビア４の接触部４２は、貫通部４１の上端から半導体基板２の面と平行な方向へせり出す形状であるので、ビア４に引っ張り力が加えられる場合に、楔として機能する。したがって、ビア４によれば、引っ張り力に対する強度が向上する。
また、半導体装置１が備える集積回路３は、ビア４との接触部３１に金属シリサイドを用いる。これにより、ビア４を形成する工程で、半導体基板２を貫通する貫通孔をエッチングによって形成する場合に、接触部３１をエッチングストッパとして機能させることができる。したがって、半導体装置１によれば、ビア４形成用の貫通孔を形成する場合に、オーバーエッチングの発生を防止することができる。
次に、図２〜図５を参照して、実施形態に係る半導体装置１の製造工程について説明する。図２〜図５は、実施形態に係る半導体装置１の製造工程を示す断面模式図である。
半導体装置１を製造する場合には、まず、図２（ａ）に示すように、半導体基板２の表面側に集積回路３を形成する。例えば、集積回路３の多層配線を形成する場合、半導体基板２の表面に酸化シリコン膜を成膜し、酸化シリコン膜に接触部３１を形成するための凹部をフォトリソグラフィーによって形成し、凹部内にポリシリコンを埋め込む。その後ポリシリコン上にニッケル層を形成し、加熱工程を経てニッケルシリサイドとし、接触部３１を形成する。
なお、接触部３１の材料は、ニッケルシリサイドに限定されるものではなく、後述のエッチングを行う際に、エッチングストッパとして機能する材料であれば、任意の金属（例えば、タングステンなど）または、任意の金属シリサイドであってもよい。
その後、酸化シリコン膜を成膜する工程、フォトリソグラフィーによって酸化シリコン膜をパターニングする工程、パターニングによって形成される配線パターンの凹部をバリアメタルによって被覆して導電性部材を埋め込む工程を順次繰り返す。
これにより、層間絶縁膜３０の内部に、層間絶縁膜３０との界面がバリアメタル３５によって被覆された第１配線層３２、第２配線層３３、および第３配線層３４が形成される。その後、層間絶縁膜３０の上面に、例えば、酸化シリコンまたは窒化シリコンを用いたパッシベーション膜５１を形成する。
ここで、第１配線層３２には、例えば、タングステンを用いる。第２配線層３３には、例えば、銅を用いる。第３配線層３４には、アルミニウムを用いる。なお、第１配線層３２、第２配線層３３、および第３配線層３４には、導電性部材であれば、上記した金属以外の金属を用いてもよい。
また、バリアメタル３５には、例えば、チタンナイトライドまたはニッケルナイトライドを用いる。なお、バリアメタル３５には、第１配線層３２、第２配線層３３、および第３配線層３４から層間絶縁膜３０への導電性部材の拡散を抑制可能な材料であれば、上記した材料以外の任意の材料を用いてもよい。
続いて、パッシベーション膜５１の上面に、例えば、ＰＥＴまたはポリイミドなどの樹脂によって保護膜５２を形成した後、保護膜５２、パッシベーション膜５１、および層間絶縁膜３０を貫通して集積回路３まで到達する貫通孔を形成する。その後、図２（ｂ）に示すように、貫通孔に、例えば、ニッケルを埋め込むことによって、上部電極５３を形成する。なお、上部電極５３は、導電性部材であれば、ニッケル以外の金属を用いてもよい。
その後、上部電極５３の上部露出面上に、例えば、アルミニウムを用いて上部電極パッド５４を形成する。なお、上部電極パッド５４には、導電性部材であれば、アルミニウム以外の金属を用いてもよい。
続いて、図２（ｃ）に示すように、上部電極パッド５４および保護膜５２の上面に接着剤６１を塗布した後、接着剤６１の上面に支持基板６２を貼着する。支持基板６２には、例えば、シリコン基板またはガラス基板を用いる。
その後、図３（ａ）に示すように、図２（ｃ）に示す構造体の天地を反転させ、半導体基板２の裏面側から半導体基板２を厚さ方向に貫通して集積回路３の接触部３１まで到達する貫通孔７を形成する。
かかる貫通孔７は、例えば、半導体基板２の裏面から接触部３１へ向けて異方性のプラズマエッチング（以下、「第１のエッチング」と記載する）を行うことによって形成される。このとき、貫通孔７は、前述したように、接触部３１がエッチングストッパとなるニッケルシリサイドによって形成されているので、接触部３１の上面よりも深くまで形成されにくい。また、第１のエッチングのエッチング量を減らすため、第１のエッチングに先立って半導体基板２を裏面側から研磨し、半導体基板２の厚さを薄くしておいてもよい。
続いて、図３（ｂ）に示すように、貫通孔７の集積回路３に到達する到達部７２を拡張する処理を行う。具体的には、第１のエッチングとは処理条件の異なるプラズマエッチング（以下、「第２のエッチング」と記載する）を行うことによって、到達部７２を拡張する。
例えば、第２のエッチングでは、エッチング対象へ衝突させるイオンを加速させるためのバイアス電圧を第１のエッチングのときよりも高く設定する。または、第２のエッチングでは、エッチャントガスの濃度を第１のエッチングのときよりも高く設定する。若しくは、第２のエッチングでは、プラズマ化したエッチャントガスのイオンエネルギーを第１のエッチングのときよりも高く設定したり、エッチャントガスの混合比を変更する。また、第２のエッチングでは、第１のエッチングよりも長い時間エッチングを行う。
上記した複数の処理条件変更のうち、いずれか一つまたは複数の処理条件変更を行うことによって、貫通孔７の到達部７２では、半導体基板２の厚さ方向へのエッチングが進みにくく、半導体基板２の面方向と平行な方向へのエッチングが進む。
これにより、貫通孔７の到達部７２における半導体基板２の厚さ方向に対して垂直な方向の寸法が、半導体基板２を貫通する貫通部７１における半導体基板２の厚さ方向に対して垂直な方向の寸法よりも大きくなるように、到達部７２が拡張される。その後、図３（ｃ）に示すように、貫通孔７の内周面および半導体基板２の裏面を酸化膜８１によって被覆する。
このように、第１のエッチング後に、エッチングの処理条件を変更するだけで、第１のエッチングを行った処理装置をそのまま使用し、第２のエッチングを行うことによって、図３（ｂ）に示すような形状の貫通孔７を形成することが可能である。
続いて、図４（ａ）に示すように、貫通孔７における底部の酸化膜をエッチングによって除去することによって接触部３１の上面を露出させた後、貫通孔７の内周面および半導体基板２の裏面側をバリアメタル８２によって被覆する。
バリアメタル８２には、例えば、チタンナイトライドまたはニッケルナイトライドの被膜を用い、スパッタによって形成される。なお、バリアメタル８２は、後に貫通孔７へ埋め込まれる金属が半導体基板２側へ拡散することを抑制可能な材料であれば、上記した材料以外の任意の材料によって形成されてもよい。
その後、図４（ｂ）に示すように、バリアメタル８２によって裏面側が被覆された半導体基板２の裏面側に、レジスト８３を塗布し、フォトリソグラフィーによってレジスト８３をパターニングする。このとき、貫通孔７における半導体基板２裏面側の開口位置に、貫通孔７よりも開口面積が大きな孔が形成されるように、レジスト８３をパターニングする。
続いて、図４（ｃ）に示すように、貫通孔７の内部へ導電性部材８４を埋め込むことによってビア４を形成する。導電性部材８４は、例えば、銅を用いる。かかるビア４は、スパッタまたはメッキによって形成される。
これにより、ビア４は、集積回路３との接触部４２における半導体基板２の厚さ方向に対して垂直な方向の寸法が、半導体基板２を貫通する貫通部４１における半導体基板２の厚さ方向に対して垂直な方向の寸法よりも大きくなるように形成される。その後、ビア４における半導体基板２裏面側の上面に、例えば、はんだを用いてバンプ５５を形成する。
続いて、図５（ａ）に示すように、レジスト８３およびレジスト８３下のバリアメタル８２を剥離し、さらに、図５（ｂ）に示すように、支持基板６２および接着剤６１を剥離する。そして、図５（ｂ）に示す構造体の天地を反転させることによって、図１に示す半導体装置１が形成される。なお、かかる半導体装置１は、装置単位にダイシングされて積層された後、樹脂などによってモールドされて製品となる。
上述したように、実施形態に係る半導体装置は、半導体基板を貫通して集積回路に接続されるビアを備える。そして、ビアは、集積回路との接触部における半導体基板の厚さ方向と垂直な方向の寸法が、半導体基板を貫通する貫通部における半導体基板の厚さ方向と垂直な方向の寸法よりも大きい。したがって、実施形態に係る半導体装置によれば、ビアと集積回路との接触抵抗を低減することができる。
また、実施形態の半導体装置では、ビアに引っ張り力が加えられる場合に、ビアにおける集積回路との接触部が楔として機能する。したがって、実施形態に係るビアによれば、引っ張り力に対する強度が向上する。
なお、上述した実施形態では、ビア４の貫通部４１および接触部４２における半導体基板２の厚さ方向に対して垂直な断面の形状について特に言及しなかったが、ビア４の断面形状は、円形であってもよく、矩形や楕円であっても構わない。
また、上述した実施形態では、バンプ５５の寸法がビア４の貫通部４１における半導体基板２の厚さ方向に対して垂直な方向の寸法より大きい場合について説明したが、貫通部４１の寸法に合わせて、バンプ５５の寸法を小さくしてもよい。これにより、半導体基板２の裏面におけるバンプ５４の専有面積を小さくすることができる。
また、上述した実施形態では、ビア４の貫通部４１が筒状である場合について説明したが、貫通部４１は、接触部４２から半導体基板２の裏面側へ向うにつれて細くなるようなテーパー形状に形成されてもよい。テーパー形状の貫通部４１は、例えば、第１のエッチングを行う期間に、適宜、エッチングの処理条件を変更することによって形成が可能である。
このように、ビア４の貫通部４１を半導体基板２の裏面側へ向うにつれて細くなるようなテーパー形状に形成し、最も細い端部の寸法に合わせてさらに小さくしたバンプ５５を設けることにより、半導体基板２の裏面におけるバンプ５４の専有面積をさらに小さくすることができる。
本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。
１ 半導体装置、 ２ 半導体基板、 ３ 集積回路、 ３１ 接触部、 ３０ 層間絶縁膜、 ４ ビア、 ４１ 貫通部、 ４２ 接触部、 ５３ 上部電極、 ５４ 上部電極パッド、 ５５ バンプ、 ７ 貫通孔、 ７１ 貫通部、 ７２ 到達部、 ８１ 酸化膜、 ８２ バリアメタル、 ８４ 導電性部材

Claims (5)

  1. 半導体基板における一方の面側に設けられる集積回路と、
    前記半導体基板を厚さ方向に貫通して前記集積回路と接続され、前記集積回路との接触部における前記厚さ方向に対して垂直な方向の寸法が、前記半導体基板を貫通する貫通部における前記厚さ方向に対して垂直な方向の寸法よりも大きいビアに埋め込まれた導電性部材と
    を備えることを特徴とする半導体装置。
  2. 前記集積回路は、
    前記導電性部材との接触部に金属シリサイドを用いる
    ことを特徴とする請求項１に記載の半導体装置。
  3. 半導体基板における一方の面側に集積回路を形成する工程と、
    前記半導体基板を厚さ方向に貫通して前記集積回路まで到達する貫通孔を形成する工程と、
    前記貫通孔における前記集積回路に到達する到達部の前記厚さ方向に対して垂直な方向の寸法が、前記半導体基板を貫通する貫通部の前記厚さ方向に対して垂直な方向の寸法よりも大きくなるように、前記到達部を拡張する工程と
    前記到達部が拡張された前記貫通孔に、導電性部材を設ける工程と
    を含むことを特徴とする半導体装置の製造方法。
  4. エッチングを行うことによって前記貫通孔を形成する工程と、
    前記エッチングとは処理条件の異なるエッチングを行うことによって前記到達部を拡張する工程と
    を含むことを特徴とする請求項３に記載の半導体装置の製造方法。
  5. 前記エッチングを行う場合のエッチングストッパとなる材料を用いて、前記集積回路における前記ビアとの接触部を形成する工程
    を含むことを特徴とする請求項４に記載の半導体装置の製造方法。
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JP5802515B2 (ja) * 2011-10-19 2015-10-28 株式会社東芝 半導体装置及びその製造方法

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