TW201508889A - 半導體裝置及半導體裝置之製造方法 - Google Patents

半導體裝置及半導體裝置之製造方法 Download PDF

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Publication number
TW201508889A
TW201508889A TW103100074A TW103100074A TW201508889A TW 201508889 A TW201508889 A TW 201508889A TW 103100074 A TW103100074 A TW 103100074A TW 103100074 A TW103100074 A TW 103100074A TW 201508889 A TW201508889 A TW 201508889A
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Taiwan
Prior art keywords
integrated circuit
semiconductor substrate
semiconductor device
hole
etching
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TW103100074A
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English (en)
Inventor
Takashi Shirono
Kazuyuki Higashi
Shinya Watanabe
Tatsuo Migita
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Toshiba Kk
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Publication of TW201508889A publication Critical patent/TW201508889A/zh

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Abstract

本發明提供一種可減小TSV與積體電路之接觸電阻之半導體裝置及半導體裝置之製造方法。 本發明之一實施形態之半導體裝置包括積體電路及導電性構件。積體電路設置於半導體基板之一面側。導電性構件係埋入至穿孔中，該穿孔於厚度方向貫通半導體基板並與積體電路連接，且與積體電路之接觸部中之相對於半導體基板之厚度方向垂直之方向的尺寸，大於貫通半導體基板之貫通部中之相對於半導體基板之厚度方向垂直之方向的尺寸。

Description

半導體裝置及半導體裝置之製造方法
[相關申請案]
本申請案係享受將日本專利申請案2013-171746號(申請日：2013年8月21日)作為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之全部內容。
本發明之實施形態係關於一種半導體裝置及半導體裝置之製造方法。
先前，有如下技術：積層形成有積體電路之複數個半導體晶片，並藉由TSV(Through Silicon Via，矽穿孔)而使各半導體晶片相互電性連接，藉此減小半導體裝置之占有面積。TSV係藉由如下方式而形成，即，形成於厚度方向貫通在一面側形成有積體電路之半導體基板並到達至積體電路的貫通孔，並於貫通孔中埋入導電性構件。
該TSV伴隨半導體晶片之小型化及積體電路之高積體化，而有相對於半導體基板之厚度方向垂直之剖面之面積微小化的傾向。如此，若TSV之剖面微小化，則會產生TSV與積體電路之間之接觸電阻增大的問題。
本發明之一實施形態之目的在於提供一種可使TSV與積體電路之接觸電阻減小之半導體裝置及半導體裝置之製造方法。
根據本發明之一實施形態，可提供一種半導體裝置。半導體裝 置包括積體電路及導電性構件。積體電路設置於半導體基板之一面側。導電性構件係埋入至穿孔中，該穿孔於厚度方向貫通上述半導體基板並與上述積體電路連接，且與上述積體電路之接觸部中之相對於上述厚度方向垂直之方向的尺寸，大於貫通上述半導體基板之貫通部中之相對於上述厚度方向垂直之方向的尺寸。
1‧‧‧半導體裝置
2‧‧‧半導體基板
3‧‧‧積體電路
4‧‧‧穿孔
7‧‧‧貫通孔
30‧‧‧層間絕緣膜
31‧‧‧接觸部
32‧‧‧第1配線層
33‧‧‧第2配線層
34‧‧‧第3配線層
35‧‧‧障壁金屬
41‧‧‧貫通部
42‧‧‧接觸部
51‧‧‧鈍化膜
52‧‧‧保護膜
53‧‧‧上部電極
54‧‧‧上部電極墊
55‧‧‧凸塊
61‧‧‧接著劑
62‧‧‧支持基板
71‧‧‧貫通部
72‧‧‧到達部
81‧‧‧氧化膜
82‧‧‧障壁金屬
83‧‧‧抗蝕劑
84‧‧‧導電性構件
圖1係表示實施形態之半導體裝置之剖面模式圖。
圖2(a)-(c)係表示實施形態之半導體裝置之製造步驟的剖面模式圖。
圖3(a)-(c)係表示實施形態之半導體裝置之製造步驟的剖面模式圖。
圖4(a)-(c)係表示實施形態之半導體裝置之製造步驟的剖面模式圖。
圖5(a)、(b)係表示實施形態之半導體裝置之製造步驟的剖面模式圖。
以下，參照隨附圖式，對實施形態之半導體裝置及半導體裝置之製造方法進行詳細說明。再者，本發明並不受該實施形態限定。
圖1係表示實施形態之半導體裝置之剖面模式圖。如圖1所示，實施形態之半導體裝置1包括：積體電路3，其係設置於例如矽晶圓等半導體基板2之一面(以下，記載為「表面」)側；及穿孔4，其於厚度方向貫通半導體基板2並與積體電路3連接。
積體電路3設置於形成於半導體基板2之表面之層間絕緣膜30之內部。層間絕緣膜30例如由氧化矽形成。該積體電路3係包括例如半導體記憶體及多層配線之LSI(Large Scale Integration，大型積體電路)。再者，於圖1中，選擇性地圖示積體電路3中之多層配線之部 分。
又，於積體電路3之表面，積層有鈍化膜51及保護膜52。鈍化膜51係例如由氧化矽或氮化矽形成。保護膜52係例如由PET(polyethylene terephthalate，聚對苯二甲酸乙二酯)或聚醯亞胺等樹脂形成。
於保護膜52之表面之特定位置，設置有上部電極墊54。上部電極墊54例如由金形成。上部電極墊54與積體電路3係藉由貫通保護膜52、鈍化膜51及層間絕緣膜30之上部電極53而連接。上部電極53例如由鎳形成。
穿孔4係以貫通半導體基板2之方式設置，於多層地積層半導體裝置1之情形時，為使下層之半導體裝置1所具備之積體電路3與上層之半導體裝置1所具備之積體電路3電性連接之貫通電極(TSV：Through Silicon Via)。該穿孔4係例如由銅形成。
於穿孔4中之於半導體基板2之背面側露出之端部，設置有用以與下層之半導體裝置1之上部電極墊54獲得導通的凸塊55。凸塊55係例如由焊料形成。
此處，普通之穿孔為貫通半導體基板之圓柱狀之導電性構件。 因此，圓柱狀穿孔係於半導體裝置之小型化及積體電路之高積體化進展之情形時，直徑變小，與積體電路之接觸面積變小，故而與積體電路之接觸電阻增大。
因此，本實施形態之穿孔4係以如下方式形成，即，與積體電路3之接觸部42中之相對於半導體基板2之厚度方向垂直之方向的尺寸大於貫通半導體基板2之貫通部41中之相對於半導體基板2之厚度方向垂直之方向的尺寸。
藉由該穿孔4，即便伴隨半導體裝置1之小型化、積體電路3之高積體化，貫通部41形成為較細，亦可藉由剖面積較貫通部41更大之接 觸部42而實現與積體電路3之連接，故而可使與積體電路3之間之接觸電阻減小。
又，由於穿孔4之接觸部42為自貫通部41之上端向與半導體基板2之面平行之方向突出之形狀，故而於對穿孔4施加拉伸力之情形時，作為楔塞而發揮功能。因此，根據穿孔4，對抗拉伸力之強度提高。
又，半導體裝置1所具備之積體電路3係與穿孔4之接觸部31使用金屬矽化物。藉此，於形成穿孔4之步驟中，於藉由蝕刻而形成貫通半導體基板2之貫通孔之情形時，可使接觸部31作為蝕刻終止層而發揮功能。因此，根據半導體裝置1，於形成穿孔4形成用貫通孔之情形時，可防止過蝕刻之產生。
繼而，參照圖2~圖5，對實施形態之半導體裝置1之製造步驟進行說明。圖2~圖5係表示實施形態之半導體裝置1之製造步驟的剖面模式圖。
於製造半導體裝置1之情形時，首先，如圖2(a)所示，於半導體基板2之表面側形成積體電路3。例如，於形成積體電路3之多層配線之情形時，於半導體基板2之表面成膜氧化矽膜，藉由光微影法於氧化矽膜形成用以形成接觸部31之凹部，並於凹部內埋入多晶矽。其後，於多晶矽上形成鎳層，並經由加熱步驟而使其成為矽化鎳，從而形成接觸部31。
再者，接觸部31之材料並不限定於矽化鎳，於進行下述蝕刻時，只要為作為蝕刻終止層而發揮功能之材料，則亦可為任意之金屬(例如鎢等)或任意之金屬矽化物。
其後，依序重複進行如下步驟：形成氧化矽膜之步驟、藉由光微影法而使氧化矽膜圖案化之步驟、藉由障壁金屬被覆藉由圖案化而形成之配線圖案之凹部並埋入導電性構件之步驟。
藉此，於層間絕緣膜30之內部，形成由障壁金屬35被覆與層間 絕緣膜30之界面之第1配線層32、第2配線層33及第3配線層34。其後，於層間絕緣膜30之上表面形成使用例如氧化矽或氮化矽之鈍化膜51。
此處，第1配線層32例如使用鎢。第2配線層33例如使用銅。第3配線層34使用鋁。再者，只要第1配線層32、第2配線層33及第3配線層34為導電性構件，則亦可使用除上述金屬以外之金屬。
又，障壁金屬35例如使用氮化鈦或氮化鎳。再者，只要為可抑制導電性構件自第1配線層32、第2配線層33及第3配線層34向層間絕緣膜30擴散的材料，則障壁金屬35亦可使用除上述材料以外之任意之材料。
繼而，於在鈍化膜51之上表面，藉由例如PET或聚醯亞胺等樹脂而形成保護膜52之後，形成貫通保護膜52、鈍化膜51及層間絕緣膜30並到達至積體電路3之貫通孔。其後，如圖2(b)所示，藉由例如於貫通孔中埋入鎳，而形成上部電極53。再者，只要上部電極53為導電性構件，則亦可使用除鎳以外之金屬。
其後，於上部電極53之上部露出面上，例如使用鋁而形成上部電極墊54。再者，只要上部電極墊54為導電性構件，則亦可使用除鋁以外之金屬。
繼而，如圖2(c)所示，於在上部電極墊54及保護膜52之上表面塗佈接著劑61之後，於接著劑61之上表面貼合支持基板62。支持基板62例如使用矽基板或玻璃基板。
其後，如圖3(a)所示，使圖2(c)所示之構造體之上下反轉，並形成自半導體基板2之背面側於厚度方向貫通半導體基板2並到達至積體電路3之接觸部31的貫通孔7。
該貫通孔7係例如藉由自半導體基板2之背面朝向接觸部31進行各向異性電漿蝕刻(以下，記載為「第1蝕刻」)而形成。此時，貫通 孔7係如上所述，接觸部31由成為蝕刻終止層之矽化鎳形成，因此不易形成至較接觸部31之上表面更深。又，為了減少第1蝕刻之蝕刻量，亦可於第1蝕刻之前自背面側研磨半導體基板2，將半導體基板2之厚度薄化。
繼而，如圖3(b)所示，進行擴大貫通孔7之到達至積體電路3之到達部72之處理。具體而言，藉由進行處理條件與第1蝕刻不同之電漿蝕刻(以下，記載為「第2蝕刻」)，而擴大到達部72。
例如，於第2蝕刻中，將用以使碰撞至蝕刻對象之離子加速之偏壓電壓設定為較第1蝕刻時更高。或者，於第2蝕刻中，將蝕刻劑氣體之濃度設定為較第1蝕刻時更高。或者，於第2蝕刻中，將已電漿化之蝕刻劑氣體之離子能量設定為較第1蝕刻時更高，或者變更蝕刻劑氣體之混合比。又，於第2蝕刻中進行較第1蝕刻更長時間之蝕刻。
藉由進行上述複數個處理條件變更中之任一或複數個處理條件變更，於貫通孔7之到達部72，蝕刻不易向半導體基板2之厚度方向進展，蝕刻會向與半導體基板2之面方向平行之方向進展。
藉此，以貫通孔7之到達部72中之相對於半導體基板2之厚度方向垂直之方向的尺寸大於貫通半導體基板2之貫通部71中之相對於半導體基板2之厚度方向垂直之方向的尺寸之方式，擴大到達部72。其後，如圖3(c)所示，藉由氧化膜81而被覆貫通孔7之內周面及半導體基板2之背面。
如此，可於第1蝕刻後，僅藉由變更蝕刻之處理條件，而直接使用已進行第1蝕刻之處理裝置，進行第2蝕刻，藉此而形成圖3(b)所示之形狀之貫通孔7。
繼而，如圖4(a)所示，於藉由利用蝕刻去除貫通孔7中之底部之氧化膜而使接觸部31之上表面露出後，藉由障壁金屬82而被覆貫通孔7之內周面及半導體基板2之背面側。
對於障壁金屬82，例如可使用氮化鈦或氮化鎳之覆膜，並藉由濺鍍而形成。再者，只要障壁金屬82為可抑制之後埋入至貫通孔7中之金屬向半導體基板2側擴散之材料，則亦可由除上述材料以外之任意之材料形成。
其後，如圖4(b)所示，於由障壁金屬82被覆背面側之半導體基板2之背面側塗佈抗蝕劑83，並藉由光微影法而使抗蝕劑83圖案化。此時，以於貫通孔7中之半導體基板2背面側之開口位置，形成開口面積大於貫通孔7之孔之方式，將抗蝕劑83圖案化。
繼而，如圖4(c)所示，藉由將導電性構件84埋入至貫通孔7之內部而形成穿孔4。導電性構件84例如使用銅。該穿孔4係藉由濺鍍或鍍敷而形成。
藉此，穿孔4形成為，與積體電路3之接觸部42中之相對於半導體基板2之厚度方向垂直之方向的尺寸，大於貫通半導體基板2之貫通部41中之相對於半導體基板2之厚度方向垂直之方向的尺寸。其後，於穿孔4中之半導體基板2背面側之上表面，例如使用焊料而形成凸塊55。
繼而，如圖5(a)所示，將抗蝕劑83及抗蝕劑83下之障壁金屬82剝離，進而，如圖5(b)所示，將支持基板62及接著劑61剝離。繼而，藉由使圖5(b)所示之構造體之上下反轉，而形成圖1所示之半導體裝置1。再者，該半導體裝置1係於經切割成裝置單位並積層之後，藉由樹脂等予以塑模，從而成為製品。
如上所述，實施形態之半導體裝置包括貫通半導體基板並與積體電路連接之穿孔。並且，穿孔之與積體電路之接觸部中之與半導體基板之厚度方向垂直之方向的尺寸，大於貫通半導體基板之貫通部中之與半導體基板之厚度方向垂直之方向的尺寸。因此，根據實施形態之半導體裝置，可減小穿孔與積體電路之接觸電阻。
又，於實施形態之半導體裝置中，於對穿孔施加拉伸力之情形時，穿孔中之與積體電路之接觸部作為楔塞而發揮功能。因此，根據實施形態之穿孔，對抗拉伸力之強度提高。
再者，於上述實施形態中，關於穿孔4之貫通部41及接觸部42中之相對於半導體基板2之厚度方向垂直之剖面之形狀並未特別言及，但穿孔4之剖面形狀既可為圓形，亦可為矩形或橢圓。
又，於上述實施形態中，對凸塊55之尺寸大於穿孔4之貫通部41中之相對於半導體基板2之厚度方向垂直之方向之尺寸之情形進行了說明，但亦可對照貫通部41之尺寸而減小凸塊55之尺寸。藉此，可減小半導體基板2之背面之凸塊54之占有面積。
又，於上述實施形態中，對穿孔4之貫通部41為筒狀之情形進行了說明，但貫通部41亦可形成為如隨著自接觸部42朝向半導體基板2之背面側變細般之錐形狀。錐形狀之貫通部41係於例如進行第1蝕刻之期間，可藉由適當變更蝕刻之處理條件而形成。
如此，可藉由使穿孔4之貫通部41形成為如隨著朝向半導體基板2之背面側變細般之錐形狀，並設置對照最細端部之尺寸而進一步縮小之凸塊55，而使半導體基板2之背面之凸塊54之占有面積進一步減小。
對本發明之若干實施形態進行了說明，但該等實施形態係作為示例而提出者，並非意欲限定發明之範圍。該等新穎之實施形態能夠以其他各種形態實施，可於不脫離發明之主旨之範圍內進行各種省略、替換、變更。該等實施形態及其變化包含於發明之範圍及主旨中，並且包含於申請專利範圍中記載之發明及其均等範圍內。
1‧‧‧半導體裝置
2‧‧‧半導體基板
3‧‧‧積體電路
4‧‧‧穿孔
30‧‧‧層間絕緣膜
31‧‧‧接觸部
41‧‧‧貫通部
42‧‧‧接觸部
51‧‧‧鈍化膜
52‧‧‧保護膜
53‧‧‧上部電極
54‧‧‧上部電極墊
55‧‧‧凸塊

Claims (5)

  1. 一種半導體裝置，其特徵在於包括：積體電路，其係設置於半導體基板之一面側；及導電性構件，其係埋入至穿孔中，該穿孔於厚度方向貫通上述半導體基板並與上述積體電路連接，且與上述積體電路之接觸部中之相對於上述厚度方向垂直之方向的尺寸大於貫通上述半導體基板之貫通部中之相對於上述厚度方向垂直之方向的尺寸。
  2. 如請求項1之半導體裝置，其中上述積體電路係於與上述導電性構件之接觸部使用金屬矽化物。
  3. 一種半導體裝置之製造方法，其特徵在於包括如下步驟：於半導體基板之一面側形成積體電路；形成於厚度方向貫通上述半導體基板並到達至上述積體電路之貫通孔；以上述貫通孔中之到達至上述積體電路之到達部之相對於上述厚度方向垂直之方向的尺寸，大於貫通上述半導體基板之貫通部之相對於上述厚度方向垂直之方向的尺寸之方式，擴大上述到達部；及於上述到達部經擴大之上述貫通孔中設置導電性構件。
  4. 如請求項3之半導體裝置之製造方法，其包括如下步驟：藉由進行蝕刻而形成上述貫通孔；及藉由進行處理條件與上述蝕刻不同之蝕刻而擴大上述到達部。
  5. 如請求項4之半導體裝置之製造方法，其包括如下步驟：使用進行上述蝕刻之情形時之成為蝕刻終止層之材料，而形成上述積體電路中之與上述穿孔之接觸部。
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TWI621220B (zh) * 2015-05-29 2018-04-11 Toshiba Memory Corp Semiconductor device and method of manufacturing the same
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TWI801811B (zh) * 2020-09-11 2023-05-11 日商鎧俠股份有限公司 半導體裝置及其製造方法

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