TWI569397B - 具有預先堆疊的微電子裝置之無凸塊增層式封裝體(二) - Google Patents
具有預先堆疊的微電子裝置之無凸塊增層式封裝體(二) Download PDFInfo
- Publication number
- TWI569397B TWI569397B TW105110566A TW105110566A TWI569397B TW I569397 B TWI569397 B TW I569397B TW 105110566 A TW105110566 A TW 105110566A TW 105110566 A TW105110566 A TW 105110566A TW I569397 B TWI569397 B TW I569397B
- Authority
- TW
- Taiwan
- Prior art keywords
- microelectronic device
- microelectronic
- active surface
- back surface
- active
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/074—Stacked arrangements of non-apertured devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/117—Stacked arrangements of devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/50—Piezoelectric or electrostrictive devices having a stacked or multilayer structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/16148—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24105—Connecting bonding areas at different heights
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73209—Bump and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73259—Bump and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83909—Post-treatment of the layer connector or bonding area
- H01L2224/83951—Forming additional members, e.g. for reinforcing, fillet sealant
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92224—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
- H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
- H01L2225/06586—Housing with external bump or bump-like connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Description
本發明係有關封裝體,更特別係有關具有預先堆疊的微電子裝置之無凸塊增層式封裝體。
於本文中所描述的本發明之數個實施例大體上係有關微電子裝置封裝體設計之領域,並且更特別係有關在一個無凸塊增層式(BBUL)設計中之具有預先堆疊之微電子裝置的微電子裝置封裝體。
依據本發明之一實施例,係特地提出一種微電子封裝體,其包含:一第一微電子裝置,其具有帶有複數個主動接觸陸塊於其上的一個主動表面、一個相對背表面和至少一個側邊,其中該第一微電子裝置包括至少一個穿矽通孔,其從該第一微電子裝置背表面延伸入該第一微電子裝置但未通過該第一微電子裝置主動表面的該等複數個主動表面接觸陸塊,該至少一穿矽通孔係與該第一微電子裝置的該主動表面之積體電路電氣式聯通;一第二微電子裝置,其具有一個主動表面、一個相對背表面、和至少一個
側邊;至少一個互連件,其電氣式地連接該第二微電子裝置主動表面與鄰近該第一微電子裝置背表面的該至少一個第一微電子裝置穿矽通孔,其中該第一微電子裝置的該主動表面與該第二微電子裝置的該主動表面面對同一方向;一下填材料層,其設置於該第一微電子裝置與該第二微電子裝置之間,該下填材料與該第二微電子晶粒的該至少一側邊直接接觸;一封裝材料,其圍繞該第一微電子裝置以及該第二微電子裝置的至少一部份,該封裝材料接觸與圍繞該第二微電子的該側邊上之該下填材料層的至少一部份;以及一增層,其電氣式連接至該第一微電子裝置主動表面之該等複數個主動表面接觸陸塊。
102‧‧‧第一微電子裝置
104、124‧‧‧主動表面
105‧‧‧主動部份
106、126、156‧‧‧背表面
107‧‧‧基體部份
108、128‧‧‧側邊
112‧‧‧穿矽通孔
114‧‧‧主動表面接觸陸塊
116、132‧‧‧接觸陸塊
122‧‧‧第二微電子裝置
136‧‧‧互連
138‧‧‧下填材料
140‧‧‧堆疊結構
150‧‧‧載體
152‧‧‧封裝材料
154‧‧‧前表面
160‧‧‧基體
162‧‧‧通孔
164、176‧‧‧導通孔
170‧‧‧增層
172、178‧‧‧傳導軌跡
174‧‧‧介電層
180‧‧‧阻焊材料
182‧‧‧開口
184‧‧‧外部互連
190、192‧‧‧微電子封裝體
本發表內容之標的係於本說明書之結尾部份特別指出並清楚請求。從後文中之說明和後附申請專利範圍,並配合隨附圖式,可更充分顯明地看出本發表內容之前述的和其他特徵。應瞭解,隨附圖式僅描繪依據本發表內容的數個實施例,且因此不應被認為是在限制本發表內容之範圍。後文將經由利用隨附圖式來額外具體且詳細地描述本發表內容,以便使本發表內容之優點更容易被確立,於此等隨附圖式中:
第1~9圖例示一種用於形成一個微電子裝置封裝體之處理的側邊剖面圖,其中此微電子裝置封裝體具有在一種無凸塊增層式設計中之預先堆疊的微電子裝置。
第10圖例示另一個微電子裝置封裝體之實施例
的側邊剖面圖,其中此微電子裝置封裝體具有在一種無凸塊增層式設計中之預先堆疊的微電子裝置。
於後文之詳細說明中,係參考藉由例示方式示出數個特定實施例的隨附圖式,其中,本案申請專利範圍中所請求之標的係可在此等實施例中實行。文中係以足以使熟於此技者實行所請求之標的的詳細程度來說明這些實施例。應瞭解,文中之多種實施例雖然互有不同,但並不必然是彼此排斥的。例如,於本文中配合一個實施例所說明的一個特定的特徵、結構或特性係可在其他實施例中實施,而不悖離所請求之標的之精神和範疇。此外,應瞭解,在所揭露的各個實施例中之個別元件的位置或配置係可在不悖離所請求之標的的精神和範疇的情況下被修改。因此,後文中之詳細說明不應被看作是限制形式,並且所請求之標的之範疇僅由被適當解讀的後附申請專利範圍以及後附申請專利範圍所賦現的全方位等效體來界定。於隨附圖式中,相似的標號在這幾個圖畫中係指相同或類似的元件或功能,並且於當中所描繪的元件並不必然係與彼此成比例繪製,相反地,個別元件可能是被放大或縮小,以求於本說明書之內文中所說明的元件能夠更容易被瞭解。
本詳細說明中之實施例係有關製造微電子封裝體的領域,其中,具有穿矽通孔(through-silicon via)的一第一微電子裝置可與一第二微電子裝置堆疊,並用於無
凸塊增層式封裝體中。
第1~8圖例示用於形成一個無凸塊增層式無核(BBUL-C)微電子封裝體之處理的一個實施例的剖面圖。如於第1圖中所示,可提供一第一微電子裝置102,其中此第一微電子裝置102包括有一個主動表面104、相對的實質上與第一微電子裝置主動表面104平行的一個背表面106、以及從第一微電子裝置主動表面104延伸至第一微電子裝置背表面106的至少一個側邊108。第一微電子裝置102可具有鄰近第一微電子裝置主動表面104的一個主動部份105以及從第一微電子裝置主動部份105延伸至第一微電子裝置背表面106的一個基體部份107。如熟於此技者所會瞭解的,第一微電子裝置主動部份105包含第一微電子裝置102的數個積體電路和互連(未示於圖中)。第一微電子裝置102可為任何適合的積體電路裝置,包括但不限制於一個微處理器(單或多核心)、一個記憶體裝置、一個晶片組、一個圖形裝置、一個特定應用積體電路,或其他諸如此類者。在一個實施例中,第一微電子裝置102為一個微處理器。
第一微電子裝置102可具有從第一微電子裝置背表面106延伸穿過第一微電子裝置基體部份107至第一微電子裝置主動部份105的至少一個導通孔。這樣的一個導通孔型態被稱為一個穿矽通孔112。第一微電子裝置穿矽通孔112可與第一微電子裝置主動部份105中之積體電路(未示於圖中)電氣式聯通。各個第一微電子裝置穿矽通孔112可係具有在第一微電子裝置背表面106上的一個接觸陸塊116。
雖然圖中係將第一微電子裝置背表面接觸陸塊示為直接與第一微電子裝置穿矽通孔112鄰接,應瞭解,其亦可係設置在第一微電子晶粒背表面上任何合適的位置而利用軌跡來形成其間之電氣式接觸。第一微電子裝置穿矽通孔112和第一微電子裝置背表面接觸陸塊116可係藉由於此技藝中已知的任何技術而被製造,包括但不限制於鑽鑿(雷射和離子)、微影術、電鍍和沈積,並且可係由任何合適的導電金屬製成,包括但不限制於銅、鋁、銀、金或其中之合金。
如於第2圖中所示,可將一第二微電子裝置122對準第一微電子裝置102。此第二微電子裝置122可具有實質上與第二微電子裝置主動表面124平行的一個一個背表面126、以及從第二微電子裝置主動表面124延伸至第二微電子裝置背表面126的至少一個側邊128。第二微電子裝置122可更進一步地包括有與微電子裝置主動表面124鄰接的至少一個接觸陸塊132,其中,第二微電子裝置接觸陸塊132可係連接至第二微電子裝置122內的積體電路(未示於圖中)。第二微電子裝置122可為任何適合的積體電路裝置,包括但不限制於一個微處理器(單或多核心)、一個記憶體裝置、一個晶片組、一個圖形裝置、一個特定應用積體電路,或其他諸如此類者。在一個實施例中,第二微電子裝置122為一個記憶體裝置。第二微電子裝置接觸陸塊132可為任何合適的導電金屬,包括但不限制於銅、鋁、銀、金或其中之合金。
如於第2圖中所更進一步示出的,第二微電子裝
置122可透過將第二微電子裝置接觸陸塊132連接至第一微電子裝置背表面接觸陸塊116的多個互連136(圖中係示為焊球)而附接至第一微電子裝置102,因而形成一個堆疊結構140。可在第一微電子裝置背表面106和第二微電子裝置主動表面124之間與此等多個互連136周圍佈置一種下填材料138,像是環氧材料等。下填材料138可增進堆疊結構140之結構完整性。
如於第3圖中所示,第二微電子裝置背表面126可如熟於此技者所習知地,藉由像是DBF(晶粒被測薄膜)或黏著劑(未示於圖中),而被附接至一個載體150。可將一個封裝材料152佈置為相鄰於第二微電子裝置側邊128、第一微電子裝置側邊108處、和在包括有第一微電子裝置主動表面接觸陸塊114的第一微電子裝置主動表面104上,因而形成封裝材料152的一個前表面154,如於第4圖中所示出的。將第二微電子裝置背表面126設置在載體150上可造成封裝材料152的一個背表面156被形成為實質上與第二微電子裝置背表面126呈平面,因而形成基體160。
封裝材料152可係藉由於此技藝中所習知的任何處理程序,包括層壓處理程序,來佈置,如熟於此技者會能識出的,並且可為任何合適的介電材料,包括但不受限於填矽環氧(silica-filled epoxy),像是可從台素股份有限公司(Ajinomoto Fine-Techno Co.,Inc.),〒210-0801日本川崎市川崎區鈴木町1-2(1-2 Suzuki-cho,Kawasaki-ku,Kawasaki-shi,210-0801,Japan)購得者(Ajinomoto GX13、
Ajinomoto GX92及其他諸如此類者)。
可形成穿過封裝材料前表面154的數個通孔162,以將各個第一微電子裝置主動表面接觸陸塊114之至少一部份暴露出來,如於第5圖中所示的。第5圖之通孔162可係藉由於此技藝中所習知的任何技術,包括但不受限於雷射鑽鑿、離子鑽鑿和微影術,而形成,如熟於此技者會能識出的。可利用一種型樣化及電鍍處理程序來填充通孔162,以形成導通孔164,並同時形成第一層傳導軌跡172,如熟於此技者會能識出的,如於第6圖中所示。
如於第7圖中所示,可在封裝材料前表面154上形成一個增層170。增層170可包含多個介電層,其具有形成於各個介電層上的傳導軌跡,並以延伸穿過各個介電層的導通孔來連接不同層的傳導軌跡。請參考第7圖,增層170可包含第一層傳導軌跡172,並具有被形成為與第一層傳導軌跡172和封裝材料前表面154相鄰的一個介電層174。至少一個軌跡對軌跡導通孔176可延伸穿過介電層174,以將至少一個第一層傳導軌跡172連接至一個第二層傳導軌跡178。可在介電層174和第二層傳導軌跡178上以圖樣成形一種阻焊材料180,而使至少一個開口182暴露出至少一部分第二層傳導軌跡178。
如於第8圖中所示,可透過在阻焊材料180中以圖樣成形的開口182而在第二層傳導軌跡178上形成至少一個外部互連184。此等外部互連184可為一種焊接材料,並且可用來將增層170連接至外部部件(未示於圖中)。
應瞭解,雖然圖中僅示出一個介電層和兩個傳導軌跡層,然而,增層170可以是任何合適數量的介電層和傳導軌跡層。此(等)介電層,像是介電層174等,可係藉由於此技藝中所習知的任何技術形成,並且可為任何合適的介電材料。傳導軌跡層,像是第一層傳導軌跡172和第二層傳導軌跡178等,及導通孔176,可係藉由於此技藝中所習知的任何技術而製造,包括但不限制於電鍍和微影術,並且可係由任何合適的導電材料製成,包括但不限制於銅、鋁、銀、金或其中之合金。
可將載體150移除,而產生一個微電子封裝體190,如於第9圖中所示。第一微電子裝置102和第二微電子裝置122之堆疊和封裝致使微電子封裝體190有足夠的厚度來避免微電子封裝體190中之翹曲,如熟於此技者會可明白的,這可致使因焊球橋接和/或未接觸開口所致的產量損失減少。
於第10圖中示出微電子封裝體192的另一個實施例。於此實施例中,第一微電子裝置主動表面104可係透過在第一微電子裝置主動表面接觸陸塊114和第二微電子裝置接觸陸塊132之間延伸的互連136,而與第二微電子裝置主動表面124電氣式聯通。增層170可近鄰地形成於第一微電子裝置背表面上,並可與第一微電子裝置穿矽通孔112電氣式聯通。
亦可瞭解,本說明內容之主題並不必然係限制於例示於第1~10圖中之特定應用。本說明內容之主題係可應
用在其他堆疊裝置應用中。此外,亦可將本說明內容之主題使用在微電子裝置製造領域以外的任何合適的應用中。此外,本說明內容之主題可為一個大型無凸塊增建式封裝體的一部分,其可包括可係在晶圓層級形成的複數個經堆疊微電子晶粒,或任何數量的合適變化,如熟於此技者會可瞭解的。
本詳細說明已透過利用例圖、方塊圖、流程圖和/或範例,而論述此等裝置和/或處理程序的多種實施例。在前文中之此等例圖、方塊圖、流程圖和/或範例含有一或多個功能和/或操作的情況下,熟於此技者會可瞭解,在各個例圖、方塊圖、流程圖和/或範例內的各個功能和/或操作係可藉由種類繁多的硬體、軟體、韌體或實際上的當中之任何組合,而被獨立和/或集體實施。
上文中所論述之主題有時候闡述包含在或連接至其他不同部件的不同部件。應瞭解,此等闡述僅係示範性的,並且係有許多替代結構可被實施來達到相同功能。以概念上來講,用來達到相同功能的對於部件的任何配置方法係被有效「聯繫」,來達成所欲功能。因此,撇開結構或中間部件不談,結合本文中之任何兩個部件來達到特定功能均可被視為彼此「聯繫」來達到所欲功能。同樣的,如此聯繫的任何兩個部件可亦被視為被彼此「可操作性連接」或「可操作性耦接」以達到所欲功能,並且能夠被如此聯繫的任何兩個部件可被視為彼此「可操作性耦接」以達到所欲功能。可操作性耦接的詳細範例包括但不限制於
可實體配接和/或實體互動部件及/或可無線互動和/或無線互動部件及/或邏輯性互動和/或可邏輯性互動部件。
熟於此技者會可瞭解,於本文中所使用的詞語,特別是在後附申請專利範圍中的,一般係意欲作為「開放性」詞語。大體而言,「包括」或「包括有」等詞語分別應被解釋為「包括但不限制於」或「包括有但不限制於」。另外,「具有」一詞應被解釋成「至少具有」。
當對於情境及/或應用而言為適當時,於詳細說明中之複數及/或單數詞語的使用可被從複數至單數解譯和/或被從單數至複數解譯。
熟於此技者會可更進一步地瞭解,若有在請求項中對元件之數量作指示,則要對此請求項如此限制之意圖會很明白地記載於此請求項中,而在沒有此種記載的情況下,是沒有這樣的意圖的。另外,若有明白記載對於所呈現之請求項記述的一個特定數量,則熟於此技者會可識出,此種記載典型上應被解釋成意指「至少」所記載之數量。
於本說明書中對於「一實施例」、「一個實施例」、「一些實施例」、「另一個實施例」或「其他實施例」等詞語之使用可意指配合一或多個實施例所描述的一個特定的特徵、結構或特性可被包括在至少一些實施例中,但並不必然是在所有實施例中。於詳細說明中之對於「一實施例」、「一個實施例」、「另一個實施例」或「其他實施例」等詞語之使用並不必然全係指相同的實施例。
雖然已於本文中利用多種方法和系統來說明並
示出某些示範性技術,但熟於此技者應會瞭解,係可不悖離於本文中所請求之標的或其精神而做出多種其他變異體,並且可由等效體取代。此外,亦可在不悖離於本文中所述之中心概念的情況下,而對所請求之標的做出許多修改來適應特定情況。因此,係意欲使所請求之標的不受限於所揭露之特定範例,並欲使所請求之標的可亦包括所有落於後附申請專利範圍之範疇內的所有實作及其等效體。
102‧‧‧第一微電子裝置
104、124‧‧‧主動表面
105‧‧‧主動部份
106、126‧‧‧背面
107‧‧‧基體部份
108、128‧‧‧側邊
112‧‧‧穿矽通孔
114‧‧‧主動表面接觸陸塊
116、132‧‧‧接觸陸塊
122‧‧‧第二微電子裝置
136‧‧‧互連
138‧‧‧下填材料
140‧‧‧堆疊結構
Claims (14)
- 一種微電子封裝體,其包含:一第一微電子裝置,其具有帶有複數個主動接觸陸塊於其上的一個主動表面、一個相對背表面和至少一個側邊,其中該第一微電子裝置包括至少一個穿矽通孔,其從該第一微電子裝置背表面延伸入該第一微電子裝置但未通過該第一微電子裝置主動表面的該等複數個主動表面接觸陸塊,該至少一穿矽通孔係與該第一微電子裝置的該主動表面之積體電路電氣式聯通;一第二微電子裝置,其具有一個主動表面、一個相對背表面、和至少一個側邊;至少一個互連件,其電氣式地連接該第二微電子裝置主動表面與鄰近該第一微電子裝置背表面的該至少一個第一微電子裝置穿矽通孔,其中該第一微電子裝置的該主動表面與該第二微電子裝置的該主動表面面對同一方向;一下填材料層,其設置於該第一微電子裝置與該第二微電子裝置之間,該下填材料與該第二微電子晶粒的該至少一側邊直接接觸;一封裝材料,其圍繞該第一微電子裝置以及該第二微電子裝置的至少一部份,該封裝材料接觸與圍繞該第二微電子的該側邊上之該下填材料層的至少一部份;以及 一增層,其電氣式連接至該第一微電子裝置主動表面之該等複數個主動表面接觸陸塊。
- 如申請專利範圍第1項之微電子封裝體,其中,該封裝材料包括實質上與該第二微電子裝置背表面呈平面的一個背表面。
- 如申請專利範圍第1項之微電子封裝體,其中,該封裝材料包含填氧化矽環氧化物。
- 一種形成微電子封裝體的方法,其包含以下步驟:形成一第一微電子裝置,其具有帶有複數個主動接觸陸塊於其上的一個主動表面、一個相對背表面和至少一個側邊,其中該第一微電子裝置包括至少一個穿矽通孔,其從該第一微電子裝置背表面延伸入該第一微電子裝置但未通過該第一微電子裝置主動表面的該等複數個主動表面接觸陸塊,該至少一穿矽通孔係與該第一微電子裝置的該等主動表面之積體電路電氣式聯通;形成一第二微電子裝置,其具有一個主動表面、一個相對背表面、和至少一個側邊;電氣式地連接該第二微電子裝置主動表面及鄰近於該第一微電子裝置背表面之該至少一第一微電子裝置穿矽通孔,其中該第一微電子裝置的該主動表面與該第二微電子裝置的該主動表面面對同一方向;形成一下填材料層於該第一微電子裝置與該第二微電子裝置之間,該下填材料層與該第二微電子晶粒的該至少一側邊直接接觸; 設置一封裝材料圍繞該第一微電子裝置與該第二微電子裝置的至少一部份,該封裝材料接觸且環繞該第二微電子裝置的該側邊上之該下填材料層的至少一部份;以及形成一增層,其中形成該增層包括將該增層電氣式連接至該第一微電子裝置主動表面之該等複數個主動表面接觸陸塊。
- 如申請專利範圍第4項之方法,其中,設置該封裝材料包括形成實質上與該第二微電子裝置背表面呈平面的一背表面。
- 如申請專利範圍第4項之方法,其中,設置該封裝材料包括設置一填氧化矽環氧化物。
- 如申請專利範圍第4項之方法,其進一步包括於該封裝材料之設置之前將該第二微電子裝置放置於一載體上。
- 一種微電子封裝體,其包含:一第一微電子裝置,其具有帶有有複數個主動接觸陸塊於其上之一主動表面、一個相對背表面和至少一個側邊,其中該第一微電子裝置包括至少一個穿矽通孔,其從該第一微電子裝置背表面延伸入該第一微電子裝置但未通過該第一微電子裝置主動表面的該等複數個主動表面接觸陸塊,該至少一穿矽通孔係與該第一微電子裝置的該主動表面之積體電路電氣式聯通;一第二微電子裝置,其具有一個主動表面、一個相 對背表面、和至少一個側邊;至少一個互連件,其電氣式地連接該第一微電子裝置主動表面的該等複數個主動表面接觸陸塊與該第二微電子裝置主動表面,其中該第一微電子裝置的該主動表面與該第二微電子裝置的該主動表面彼此面對;一下填材料層,其設置於該第一微電子裝置與該第二微電子裝置之間,該下填材料與該第二微電子晶粒的該至少一側邊直接接觸;一封裝材料,其圍繞該第一微電子裝置以及該第二微電子裝置的至少一部份,該封裝材料接觸與圍繞該第二微電子晶粒的該側邊上之該下填材料層的至少一部份;以及一增層,其電氣式連接至鄰近該第一微電子裝置背表面的該至少一個第一微電子裝置穿矽通孔。
- 如申請專利範圍第8項之微電子封裝體,其中該封裝材料包括實質上與該第二微電子裝置背表面呈平面的一個背表面
- 如申請專利範圍第8項之微電子封裝體,其中該封裝材料包含填氧化矽環氧化物。
- 一種形成一微電子封裝體之方法,其包含以下步驟:形成一第一微電子裝置,其具有帶有複數個主動表面接觸陸塊的一個主動表面、一個相對背表面和至少一個側邊,其中該第一微電子裝置包括至少一個穿矽通孔,其從該第一微電子裝置背表面延伸入該第一微電子裝 置但未通過該第一微電子裝置主動表面的該等複數個主動表面接觸陸塊,該至少一穿矽通孔與該第一微電子裝置的該等主動表面之積體電路電氣式聯通;形成一第二微電子裝置,其具有一個主動表面、一個相對背表面、和至少一個側邊;電氣式地連接該第二微電子裝置主動表面與該該第一微電子裝置主動表面之該等複數個主動表面接觸陸塊,其中該第一微電子裝置的該主動表面與該第二微電子裝置的該主動表面彼此面對;形成配置於該第一微電子裝置與該第二微電子裝置之間之一下填材料層,該下填材料層與該第二微電子晶粒的該至少一側邊直接接觸;設置圍繞該第一微電子裝置與該第二微電子裝置的至少一部份之一封裝材料,該封裝材料接觸且環繞該第二微電子裝置的該側邊上之該下填材料層的至少一部份;以及形成一增層,其中形成該增層包括將該增層電氣式連接至鄰近該第一微電子裝置背表面的該至少一個第一微電子裝置穿矽通孔。
- 如申請專利範圍第11項之方法,其中,設置該封裝材料包括形成實質上與該第二微電子裝置背表面呈平面的一背表面。
- 如申請專利範圍第11項之方法,其中,設置該封裝材料包括設置一填氧化矽環氧化物。
- 如申請專利範圍第11項之方法,其進一步包括於設置該封裝材料之前將該第二微電子裝置放置於一載體上。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/868,816 US8754516B2 (en) | 2010-08-26 | 2010-08-26 | Bumpless build-up layer package with pre-stacked microelectronic devices |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201626534A TW201626534A (zh) | 2016-07-16 |
TWI569397B true TWI569397B (zh) | 2017-02-01 |
Family
ID=45696053
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW105141885A TWI617002B (zh) | 2010-08-26 | 2011-08-08 | 具有預先堆疊的微電子裝置之無凸塊增層式封裝體(三) |
TW100128180A TWI538130B (zh) | 2010-08-26 | 2011-08-08 | 具有預先堆疊的微電子裝置之無凸塊增層式封裝體 |
TW105110566A TWI569397B (zh) | 2010-08-26 | 2011-08-08 | 具有預先堆疊的微電子裝置之無凸塊增層式封裝體(二) |
TW106143976A TWI669799B (zh) | 2010-08-26 | 2011-08-08 | 具有預先堆疊的微電子裝置之無凸塊增層式封裝體(四) |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW105141885A TWI617002B (zh) | 2010-08-26 | 2011-08-08 | 具有預先堆疊的微電子裝置之無凸塊增層式封裝體(三) |
TW100128180A TWI538130B (zh) | 2010-08-26 | 2011-08-08 | 具有預先堆疊的微電子裝置之無凸塊增層式封裝體 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW106143976A TWI669799B (zh) | 2010-08-26 | 2011-08-08 | 具有預先堆疊的微電子裝置之無凸塊增層式封裝體(四) |
Country Status (3)
Country | Link |
---|---|
US (4) | US8754516B2 (zh) |
TW (4) | TWI617002B (zh) |
WO (1) | WO2012027075A2 (zh) |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8535989B2 (en) | 2010-04-02 | 2013-09-17 | Intel Corporation | Embedded semiconductive chips in reconstituted wafers, and systems containing same |
US9847308B2 (en) | 2010-04-28 | 2017-12-19 | Intel Corporation | Magnetic intermetallic compound interconnect |
US8939347B2 (en) | 2010-04-28 | 2015-01-27 | Intel Corporation | Magnetic intermetallic compound interconnect |
US8313958B2 (en) | 2010-05-12 | 2012-11-20 | Intel Corporation | Magnetic microelectronic device attachment |
US8434668B2 (en) | 2010-05-12 | 2013-05-07 | Intel Corporation | Magnetic attachment structure |
US8609532B2 (en) | 2010-05-26 | 2013-12-17 | Intel Corporation | Magnetically sintered conductive via |
US20120001339A1 (en) | 2010-06-30 | 2012-01-05 | Pramod Malatkar | Bumpless build-up layer package design with an interposer |
US8372666B2 (en) | 2010-07-06 | 2013-02-12 | Intel Corporation | Misalignment correction for embedded microelectronic die applications |
US8754516B2 (en) | 2010-08-26 | 2014-06-17 | Intel Corporation | Bumpless build-up layer package with pre-stacked microelectronic devices |
US9741645B2 (en) * | 2011-12-21 | 2017-08-22 | Intel Corporation | Dense interconnect with solder cap (DISC) formation with laser ablation and resulting semiconductor structures and packages |
US9257368B2 (en) * | 2012-05-14 | 2016-02-09 | Intel Corporation | Microelectric package utilizing multiple bumpless build-up structures and through-silicon vias |
US8742597B2 (en) | 2012-06-29 | 2014-06-03 | Intel Corporation | Package substrates with multiple dice |
CN103579128B (zh) * | 2012-07-26 | 2016-12-21 | 碁鼎科技秦皇岛有限公司 | 芯片封装基板、芯片封装结构及其制作方法 |
US20140091440A1 (en) * | 2012-09-29 | 2014-04-03 | Vijay K. Nair | System in package with embedded rf die in coreless substrate |
US9496211B2 (en) | 2012-11-21 | 2016-11-15 | Intel Corporation | Logic die and other components embedded in build-up layers |
US20140175657A1 (en) * | 2012-12-21 | 2014-06-26 | Mihir A. Oka | Methods to improve laser mark contrast on die backside film in embedded die packages |
US9583460B2 (en) * | 2014-02-14 | 2017-02-28 | Qualcomm Incorporated | Integrated device comprising stacked dies on redistribution layers |
TWI517343B (zh) * | 2014-03-25 | 2016-01-11 | 恆勁科技股份有限公司 | 覆晶堆疊封裝結構及其製作方法 |
CN104392940A (zh) * | 2014-10-31 | 2015-03-04 | 南通富士通微电子股份有限公司 | 形成倒装芯片半导体封装的方法 |
US20180005916A1 (en) * | 2016-06-30 | 2018-01-04 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and manufacturing method thereof |
US10074633B2 (en) | 2016-11-08 | 2018-09-11 | Micron Technology, Inc. | Semiconductor die assemblies having molded underfill structures and related technology |
HU231212B1 (hu) | 2018-04-16 | 2021-11-29 | CHINOIN Gyógyszer és Vegyészeti Termékek Gyára Zrt. | Eljárás iloprost előállítására |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040238936A1 (en) * | 2003-05-28 | 2004-12-02 | Rumer Christopher L. | Through silicon via, folded flex microelectronic package |
Family Cites Families (99)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4497033A (en) | 1980-10-24 | 1985-01-29 | Process Technologies, Inc. | Multiplexed arrangement for connecting a plurality of transducers to a field interface device at a storage tank |
US5353498A (en) | 1993-02-08 | 1994-10-11 | General Electric Company | Method for fabricating an integrated circuit module |
US5527741A (en) | 1994-10-11 | 1996-06-18 | Martin Marietta Corporation | Fabrication and structures of circuit modules with flexible interconnect layers |
US5686318A (en) * | 1995-12-22 | 1997-11-11 | Micron Technology, Inc. | Method of forming a die-to-insert permanent connection |
US5841193A (en) | 1996-05-20 | 1998-11-24 | Epic Technologies, Inc. | Single chip modules, repairable multichip modules, and methods of fabrication thereof |
US5834945A (en) * | 1996-12-31 | 1998-11-10 | Micron Technology, Inc. | High speed temporary package and interconnect for testing semiconductor dice and method of fabrication |
US5866943A (en) * | 1997-06-23 | 1999-02-02 | Lsi Logic Corporation | System and method for forming a grid array device package employing electomagnetic shielding |
US6046507A (en) * | 1997-12-08 | 2000-04-04 | Advanced Micro Devices | Electrophoretic coating methodology to improve internal package delamination and wire bond reliability |
US6356429B2 (en) * | 1999-02-18 | 2002-03-12 | Tdk Corporation | Capacitor |
US6306680B1 (en) | 1999-02-22 | 2001-10-23 | General Electric Company | Power overlay chip scale packages for discrete power devices |
US6917525B2 (en) * | 2001-11-27 | 2005-07-12 | Nanonexus, Inc. | Construction structures and manufacturing processes for probe card assemblies and packages having wafer level springs |
US6239482B1 (en) | 1999-06-21 | 2001-05-29 | General Electric Company | Integrated circuit package including window frame |
US6242282B1 (en) | 1999-10-04 | 2001-06-05 | General Electric Company | Circuit chip package and fabrication method |
US6271469B1 (en) | 1999-11-12 | 2001-08-07 | Intel Corporation | Direct build-up layer on an encapsulated die package |
US6154366A (en) | 1999-11-23 | 2000-11-28 | Intel Corporation | Structures and processes for fabricating moisture resistant chip-on-flex packages |
JP4614214B2 (ja) * | 1999-12-02 | 2011-01-19 | 信越化学工業株式会社 | 半導体装置素子用中空パッケージ |
US6555908B1 (en) | 2000-02-10 | 2003-04-29 | Epic Technologies, Inc. | Compliant, solderable input/output bump structures |
US6426545B1 (en) | 2000-02-10 | 2002-07-30 | Epic Technologies, Inc. | Integrated circuit structures and methods employing a low modulus high elongation photodielectric |
US6396148B1 (en) | 2000-02-10 | 2002-05-28 | Epic Technologies, Inc. | Electroless metal connection structures and methods |
US6586836B1 (en) | 2000-03-01 | 2003-07-01 | Intel Corporation | Process for forming microelectronic packages and intermediate structures formed therewith |
US6734534B1 (en) | 2000-08-16 | 2004-05-11 | Intel Corporation | Microelectronic substrate with integrated devices |
US20020020898A1 (en) | 2000-08-16 | 2002-02-21 | Vu Quat T. | Microelectronic substrates with integrated devices |
JP2002076252A (ja) * | 2000-08-31 | 2002-03-15 | Nec Kyushu Ltd | 半導体装置 |
US6586822B1 (en) | 2000-09-08 | 2003-07-01 | Intel Corporation | Integrated core microelectronic package |
US6489185B1 (en) | 2000-09-13 | 2002-12-03 | Intel Corporation | Protective film for the fabrication of direct build-up layers on an encapsulated die package |
US6713859B1 (en) | 2000-09-13 | 2004-03-30 | Intel Corporation | Direct build-up layer on an encapsulated die package having a moisture barrier structure |
US6617682B1 (en) | 2000-09-28 | 2003-09-09 | Intel Corporation | Structure for reducing die corner and edge stresses in microelectronic packages |
US6709898B1 (en) | 2000-10-04 | 2004-03-23 | Intel Corporation | Die-in-heat spreader microelectronic package |
US6423570B1 (en) | 2000-10-18 | 2002-07-23 | Intel Corporation | Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby |
US6555906B2 (en) | 2000-12-15 | 2003-04-29 | Intel Corporation | Microelectronic package having a bumpless laminated interconnection layer |
US6703400B2 (en) | 2001-02-23 | 2004-03-09 | Schering Corporation | Methods for treating multidrug resistance |
US6706553B2 (en) | 2001-03-26 | 2004-03-16 | Intel Corporation | Dispensing process for fabrication of microelectronic packages |
US6888240B2 (en) | 2001-04-30 | 2005-05-03 | Intel Corporation | High performance, low cost microelectronic circuit package with interposer |
US6894399B2 (en) | 2001-04-30 | 2005-05-17 | Intel Corporation | Microelectronic device having signal distribution functionality on an interfacial layer thereof |
US7071024B2 (en) | 2001-05-21 | 2006-07-04 | Intel Corporation | Method for packaging a microelectronic device using on-die bond pad expansion |
TW502422B (en) * | 2001-06-07 | 2002-09-11 | Ultra Tera Corp | Method for encapsulating thin flip-chip-type semiconductor device |
US6586276B2 (en) | 2001-07-11 | 2003-07-01 | Intel Corporation | Method for fabricating a microelectronic device using wafer-level adhesion layer deposition |
TW502406B (en) * | 2001-08-01 | 2002-09-11 | Siliconware Precision Industries Co Ltd | Ultra-thin package having stacked die |
US7183658B2 (en) | 2001-09-05 | 2007-02-27 | Intel Corporation | Low cost microelectronic circuit package |
US6580611B1 (en) | 2001-12-21 | 2003-06-17 | Intel Corporation | Dual-sided heat removal system |
US6841413B2 (en) | 2002-01-07 | 2005-01-11 | Intel Corporation | Thinned die integrated circuit package |
JP2003273317A (ja) * | 2002-03-19 | 2003-09-26 | Nec Electronics Corp | 半導体装置及びその製造方法 |
JP4174823B2 (ja) * | 2003-03-27 | 2008-11-05 | サンケン電気株式会社 | 半導体発光装置 |
TWI230447B (en) * | 2003-04-25 | 2005-04-01 | Advanced Semiconductor Eng | Multi-chips package |
US7187068B2 (en) * | 2004-08-11 | 2007-03-06 | Intel Corporation | Methods and apparatuses for providing stacked-die devices |
US7442581B2 (en) | 2004-12-10 | 2008-10-28 | Freescale Semiconductor, Inc. | Flexible carrier and release method for high volume electronic package fabrication |
US7109055B2 (en) | 2005-01-20 | 2006-09-19 | Freescale Semiconductor, Inc. | Methods and apparatus having wafer level chip scale package for sensing elements |
US7160755B2 (en) | 2005-04-18 | 2007-01-09 | Freescale Semiconductor, Inc. | Method of forming a substrateless semiconductor package |
US7279795B2 (en) * | 2005-12-29 | 2007-10-09 | Intel Corporation | Stacked die semiconductor package |
SG133445A1 (en) | 2005-12-29 | 2007-07-30 | Micron Technology Inc | Methods for packaging microelectronic devices and microelectronic devices formed using such methods |
US20070210433A1 (en) * | 2006-03-08 | 2007-09-13 | Rajesh Subraya | Integrated device having a plurality of chip arrangements and method for producing the same |
US7425464B2 (en) | 2006-03-10 | 2008-09-16 | Freescale Semiconductor, Inc. | Semiconductor device packaging |
US7859098B2 (en) * | 2006-04-19 | 2010-12-28 | Stats Chippac Ltd. | Embedded integrated circuit package system |
JP2007317822A (ja) * | 2006-05-25 | 2007-12-06 | Sony Corp | 基板処理方法及び半導体装置の製造方法 |
US7723164B2 (en) | 2006-09-01 | 2010-05-25 | Intel Corporation | Dual heat spreader panel assembly method for bumpless die-attach packages, packages containing same, and systems containing same |
US7659143B2 (en) | 2006-09-29 | 2010-02-09 | Intel Corporation | Dual-chip integrated heat spreader assembly, packages containing same, and systems containing same |
US20080093723A1 (en) | 2006-10-19 | 2008-04-24 | Myers Todd B | Passive placement in wire-bonded microelectronics |
US7588951B2 (en) | 2006-11-17 | 2009-09-15 | Freescale Semiconductor, Inc. | Method of packaging a semiconductor device and a prefabricated connector |
US7476563B2 (en) | 2006-11-17 | 2009-01-13 | Freescale Semiconductor, Inc. | Method of packaging a device using a dielectric layer |
US7632715B2 (en) | 2007-01-05 | 2009-12-15 | Freescale Semiconductor, Inc. | Method of packaging semiconductor devices |
US7719122B2 (en) * | 2007-01-11 | 2010-05-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | System-in-package packaging for minimizing bond wire contamination and yield loss |
TWI335654B (en) * | 2007-05-04 | 2011-01-01 | Advanced Semiconductor Eng | Package for reducing stress |
US7648858B2 (en) | 2007-06-19 | 2010-01-19 | Freescale Semiconductor, Inc. | Methods and apparatus for EMI shielding in multi-chip modules |
US7868445B2 (en) | 2007-06-25 | 2011-01-11 | Epic Technologies, Inc. | Integrated structures and methods of fabrication thereof with fan-out metallization on a chips-first chip layer |
US7595226B2 (en) | 2007-08-29 | 2009-09-29 | Freescale Semiconductor, Inc. | Method of packaging an integrated circuit die |
US7651889B2 (en) | 2007-09-13 | 2010-01-26 | Freescale Semiconductor, Inc. | Electromagnetic shield formation for integrated circuit die package |
US20090072382A1 (en) | 2007-09-18 | 2009-03-19 | Guzek John S | Microelectronic package and method of forming same |
US9941245B2 (en) | 2007-09-25 | 2018-04-10 | Intel Corporation | Integrated circuit packages including high density bump-less build up layers and a lesser density core or coreless substrate |
US20090079064A1 (en) | 2007-09-25 | 2009-03-26 | Jiamiao Tang | Methods of forming a thin tim coreless high density bump-less package and structures formed thereby |
US7851905B2 (en) | 2007-09-26 | 2010-12-14 | Intel Corporation | Microelectronic package and method of cooling an interconnect feature in same |
US7948095B2 (en) * | 2008-02-12 | 2011-05-24 | United Test And Assembly Center Ltd. | Semiconductor package and method of making the same |
US8035216B2 (en) | 2008-02-22 | 2011-10-11 | Intel Corporation | Integrated circuit package and method of manufacturing same |
US20100109169A1 (en) * | 2008-04-29 | 2010-05-06 | United Test And Assembly Center Ltd | Semiconductor package and method of making the same |
US8253230B2 (en) | 2008-05-15 | 2012-08-28 | Micron Technology, Inc. | Disabling electrical connections using pass-through 3D interconnects and associated systems and methods |
US8093704B2 (en) | 2008-06-03 | 2012-01-10 | Intel Corporation | Package on package using a bump-less build up layer (BBUL) package |
US7800238B2 (en) | 2008-06-27 | 2010-09-21 | Micron Technology, Inc. | Surface depressions for die-to-die interconnects and associated systems and methods |
US7808113B2 (en) * | 2008-07-10 | 2010-10-05 | Texas Instruments Incorporated | Flip chip semiconductor device having workpiece adhesion promoter layer for improved underfill adhesion |
KR101461630B1 (ko) * | 2008-11-06 | 2014-11-20 | 삼성전자주식회사 | 실장 높이는 축소되나, 솔더 접합 신뢰도는 개선되는 웨이퍼 레벨 칩 온 칩 패키지와, 패키지 온 패키지 및 그 제조방법 |
US7843052B1 (en) * | 2008-11-13 | 2010-11-30 | Amkor Technology, Inc. | Semiconductor devices and fabrication methods thereof |
US7858441B2 (en) * | 2008-12-08 | 2010-12-28 | Stats Chippac, Ltd. | Semiconductor package with semiconductor core structure and method of forming same |
US8513119B2 (en) * | 2008-12-10 | 2013-08-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming bump structure having tapered sidewalls for stacked dies |
WO2010098115A1 (ja) | 2009-02-26 | 2010-09-02 | パナソニック株式会社 | 波長変換レーザ光源及び画像表示装置 |
US20100327465A1 (en) * | 2009-06-25 | 2010-12-30 | Advanced Semiconductor Engineering, Inc. | Package process and package structure |
US8183678B2 (en) * | 2009-08-04 | 2012-05-22 | Amkor Technology Korea, Inc. | Semiconductor device having an interposer |
US8803332B2 (en) * | 2009-09-11 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Delamination resistance of stacked dies in die saw |
US20110108999A1 (en) | 2009-11-06 | 2011-05-12 | Nalla Ravi K | Microelectronic package and method of manufacturing same |
US8803305B2 (en) * | 2009-11-18 | 2014-08-12 | Qualcomm Incorporated | Hybrid package construction with wire bond and through silicon vias |
US8304286B2 (en) * | 2009-12-11 | 2012-11-06 | Stats Chippac Ltd. | Integrated circuit packaging system with shielded package and method of manufacture thereof |
US8742561B2 (en) | 2009-12-29 | 2014-06-03 | Intel Corporation | Recessed and embedded die coreless package |
US8901724B2 (en) | 2009-12-29 | 2014-12-02 | Intel Corporation | Semiconductor package with embedded die and its methods of fabrication |
US8891246B2 (en) | 2010-03-17 | 2014-11-18 | Intel Corporation | System-in-package using embedded-die coreless substrates, and processes of forming same |
US8535989B2 (en) | 2010-04-02 | 2013-09-17 | Intel Corporation | Embedded semiconductive chips in reconstituted wafers, and systems containing same |
US8431438B2 (en) | 2010-04-06 | 2013-04-30 | Intel Corporation | Forming in-situ micro-feature structures with coreless packages |
US8319318B2 (en) | 2010-04-06 | 2012-11-27 | Intel Corporation | Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages |
US8618652B2 (en) | 2010-04-16 | 2013-12-31 | Intel Corporation | Forming functionalized carrier structures with coreless packages |
US8313958B2 (en) | 2010-05-12 | 2012-11-20 | Intel Corporation | Magnetic microelectronic device attachment |
US20120001339A1 (en) | 2010-06-30 | 2012-01-05 | Pramod Malatkar | Bumpless build-up layer package design with an interposer |
US8372666B2 (en) | 2010-07-06 | 2013-02-12 | Intel Corporation | Misalignment correction for embedded microelectronic die applications |
US8754516B2 (en) * | 2010-08-26 | 2014-06-17 | Intel Corporation | Bumpless build-up layer package with pre-stacked microelectronic devices |
-
2010
- 2010-08-26 US US12/868,816 patent/US8754516B2/en active Active
-
2011
- 2011-08-02 WO PCT/US2011/046287 patent/WO2012027075A2/en active Application Filing
- 2011-08-08 TW TW105141885A patent/TWI617002B/zh active
- 2011-08-08 TW TW100128180A patent/TWI538130B/zh not_active IP Right Cessation
- 2011-08-08 TW TW105110566A patent/TWI569397B/zh not_active IP Right Cessation
- 2011-08-08 TW TW106143976A patent/TWI669799B/zh not_active IP Right Cessation
-
2014
- 2014-05-05 US US14/269,318 patent/US9362253B2/en active Active
-
2016
- 2016-06-01 US US15/170,833 patent/US9831213B2/en active Active
-
2017
- 2017-10-23 US US15/791,292 patent/US20180047702A1/en not_active Abandoned
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040238936A1 (en) * | 2003-05-28 | 2004-12-02 | Rumer Christopher L. | Through silicon via, folded flex microelectronic package |
Also Published As
Publication number | Publication date |
---|---|
TW201626534A (zh) | 2016-07-16 |
US9831213B2 (en) | 2017-11-28 |
TW201216431A (en) | 2012-04-16 |
TWI538130B (zh) | 2016-06-11 |
TWI617002B (zh) | 2018-03-01 |
WO2012027075A3 (en) | 2012-05-18 |
US20120049382A1 (en) | 2012-03-01 |
TW201727861A (zh) | 2017-08-01 |
US8754516B2 (en) | 2014-06-17 |
WO2012027075A2 (en) | 2012-03-01 |
TW201824501A (zh) | 2018-07-01 |
US20140239510A1 (en) | 2014-08-28 |
US20160276317A1 (en) | 2016-09-22 |
TWI669799B (zh) | 2019-08-21 |
US9362253B2 (en) | 2016-06-07 |
US20180047702A1 (en) | 2018-02-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI569397B (zh) | 具有預先堆疊的微電子裝置之無凸塊增層式封裝體(二) | |
TWI708363B (zh) | 封裝、半導體封裝及封裝結構的形成方法 | |
US11282761B2 (en) | Semiconductor packages and methods of manufacturing the same | |
US10049953B2 (en) | Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors | |
TWI550795B (zh) | 半導體元件及其製造方法 | |
TWI495064B (zh) | 晶圓級半導體封裝件及其製造方法 | |
TW202013652A (zh) | 微電子總成 | |
TWI763638B (zh) | 半導體元件與其製造方法 | |
KR20130033375A (ko) | 인터포저를 갖는 범프레스 빌드-업 층 패키지 디자인 | |
TW201703219A (zh) | 半導體裝置及其製造方法 | |
TWI721038B (zh) | 封裝結構、疊層封裝元件及其形成方法 | |
KR20130041276A (ko) | 완전 매립형 범프리스 빌드업 레이어 패키지 형성 방법 및 그에 의해 형성된 구조물 | |
TW201830531A (zh) | 封裝單體化的方法 | |
TWI606570B (zh) | 積體電路結構及形成方法 | |
KR20230078607A (ko) | 팬 아웃 패키지 및 이의 형성 방법 | |
TWI587464B (zh) | 封裝結構及其製造方法 | |
US9263376B2 (en) | Chip interposer, semiconductor device, and method for manufacturing a semiconductor device | |
TW202021085A (zh) | 半導體封裝 | |
US20210407963A1 (en) | Package structure and method of manufacturing the same | |
TWI662635B (zh) | 封裝結構及其製造方法 | |
TWI612627B (zh) | 電子封裝件及其製法 | |
TWI611530B (zh) | 具有散熱座之散熱增益型面朝面半導體組體及製作方法 | |
TW202405960A (zh) | 熱管理結構及製造熱管理結構的方法 | |
GB2514032A (en) | Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |