TWI495064B - 晶圓級半導體封裝件及其製造方法 - Google Patents

晶圓級半導體封裝件及其製造方法 Download PDF

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TWI495064B
TWI495064B TW099146979A TW99146979A TWI495064B TW I495064 B TWI495064 B TW I495064B TW 099146979 A TW099146979 A TW 099146979A TW 99146979 A TW99146979 A TW 99146979A TW I495064 B TWI495064 B TW I495064B
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interposer
package
semiconductor package
semiconductor
semiconductor wafer
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TW099146979A
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TW201220450A (en
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Hunt John
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Advanced Semiconductor Eng
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Description

晶圓級半導體封裝件及其製造方法
本發明是有關於一種半導體封裝件及其製造方法，且特別是有關於一種晶圓級半導體封裝件(wafer level semiconductor package)及其製造方法。
半導體裝置日漸複雜，且半導體裝置被要求有更小尺寸及更快的處理速度。為了支援增加的功能，包括此些元件的半導體封裝件具有大量的接觸墊以作為對外電性連接之用，例如作為輸入或輸出之用。此些接觸墊將佔據一半導體封裝件之大量的表面積。
在過去，晶圓級封裝可能受限於扇入型(fan-in)結構，其中，最終半導體裝置封裝件之電性觸點及其它元件被限制於由半導體裝置之周緣所定義之一面積。為了滿足接觸墊之增加，晶圓級封裝不再限制於扇入型結構，而是支援一扇出型(fan-out)結構。例如，在一扇出型結構，此些接觸墊可至少部分地位於由半導體裝置之周緣所定義之一面積之外。此些接觸墊位於一半導體封裝件之多面，例如是半導體封裝件之頂面及底面。
然而，形成及改善一半導體裝置之電性連接方式以增加大量的接觸墊可能導致更複雜的製程。以下係描述改善傳統技術以發展晶圓級封裝件及其製造方法。
根據本發明之第一方面，提出一種半導體封裝件。半導體封裝件包括至少一半導體晶片、一中介層元件(interposer element)、一封裝體(package body)及一下重佈層(redistribution layer)。半導體晶片具有一主動面。中介層元件具有一上表面及一下表面，中介層元件具有至少一導通孔(conductive via)，導通孔延伸於上表面與下表面之間。封裝體包覆部分之主動晶片及部分之中介層元件。下重佈層電性連接中介層元件與半導體晶片之主動面。
在一實施例中，根據本發明之第二方面，提出一種堆疊封裝組件。半導體封裝件包括至少一半導體晶片、一中介層元件、一封裝體、一下重佈層及一電性觸點。半導體晶片具有一主動面。中介層元件具有一上表面及一下表面，中介層元件具有至少一導通孔，導通孔延伸於上表面與下表面之間。封裝體包覆部分之主動晶片及部分之中介層元件。下重佈層電性連接中介層元件與半導體晶片之主動面。電性觸點係從半導體晶片之一下周緣露出。其中，下重佈層電性連接電性觸點與半導體晶片之主動面及中介層元件，下重佈層係鄰近半導體晶片之主動面設置。
根據本發明之第三方面，提出一種形成方法。形成方法包括以下步驟。提供一半導體晶片，半導體晶片具有一主動面；鄰近半導體晶片放置一中介層元件，中介層元件具有一上表面及一下表面，中介層元件具有至少一第一導通孔，該至少一第一導通孔延伸至該下表面；以一包覆劑(encapsulant)，包覆部分之半導體晶片及部分之中介層元件，使半導體晶片之主動面、中介層元件之下表面及部分之包覆劑形成一實質上共面(substantially coplanar surface)；以及，形成一下重佈層於實質上共面，下重佈層電性連接於中介層元件與半導體晶片之主動面。
為了對本發明之上述及其他方面有更佳的瞭解，下文特舉至少一實施例，並配合所附圖式，作詳細說明如下：
請參照第1圖，其繪示依照本發明之堆疊半導體組件100之剖視圖。堆疊半導體組件100包括一半導體封裝件192及一半導體封裝件194，半導體封裝件194位於半導體封裝件192之上。半導體封裝件194透過數個導電凸塊(conductive bump)193電性連接於半導體封裝件192。半導體封裝件194也可以半導體封裝件之任一型式，例如是晶圓級封裝件、一BGA封裝件及一基板級封裝件(substrate-level package)。半導體封裝件194可包括一或更多半導體封裝件與/或一或更多被動電性元件(passive electrical component)之組合。半導體封裝件192包括一半導體裝置102，半導體裝置102包括一下表面104、一上表面106及側面108，下表面104於本實施例中係一主動面，例如是具有多個接合墊(bond pad)之主動面。側面108鄰近半導體裝置102之一周緣(periphery)且延伸於下表面104與上表面106之間。在本實施例中，表面104、106及108中至少一者實質上係平面(planar)，側面108具有相對於下表面104或上表面106實質上垂直的方位，然而表面104、106及108亦可變化成其它實施態樣。在一實施例中，上表面106係半導體裝置102之一背面，而下表面104係半導體裝置102之一主動面。下表面104包括數個晶片接合墊111，其提供半導體裝置102與半導體封裝件192之導電結構電性輸入及輸出之用，導電結構例如是一圖案化導電層150(於後續說明)。本實施例中，半導體裝置102係整合電路(integrated circuit)，然而，一般而言，半導體裝置102亦可為任何主動裝置(active device)、任何被動裝置(passive device)或其組合，主動裝置例如是一光學或其它種類之感知器、一微機電系統(MEMS)。半導體裝置102可以是主動晶片。即使半導體裝置繪示如半導體封裝件192，然而其它實施態樣中之半導體封裝件192可包括超過一個半導體裝置。
如第1圖所示，半導體封裝件192亦可包括一封裝體114，其鄰近半導體裝置102設置。本實施例中，封裝體114覆蓋或包覆部分之半導體裝置102及一個或更多之中介層170(於後續說明)之一部分，中介層170例如是數個中介層元件170。封裝體114可提供機械穩定性(mechanical stability)及抵抗氧化、溼度及其它環境條件之保護。本實施例中，封裝體114實質上覆蓋上表面106及半導體裝置102之側面108，且半導體裝置102之下表面104實質上曝露出來或未被封裝體114覆蓋。封裝體114包括一下表面116及一上表面118。本實施例中，下表面116與上表面118中每一者實質上係平面，然而下表面116與上表面118亦可變化為其它實施態樣。
在一實施例中，封裝體114可由一封裝材料(molding material)形成。該封裝材料可包括酚醛基樹脂(Novolac-based resin)、環氧基樹脂(epoxy-based resin)、矽基樹脂(silicone-based resin)或其他適當之包覆劑。該封裝材料亦可包括適當之填充劑(filler)，例如是粉狀之二氧化矽。該封裝材料可以是預浸漬材料(pre-impregnated(prepreg) material)，例如是預浸漬介電材料。
半導體封裝件192更包括一個或更多中介層170。中介層170可鄰近半導體裝置102之一周緣177(例如是側周緣，如第2圖所示)。中介層170可以是接觸式中介層(contiguous interposer)，其環繞半導體晶片(如第7圖所示)之周緣177延伸或如第2圖所示之非接觸式分離之中介層元件。每個中介層170包含一基板材料，例如是玻璃、矽(silicon)、金屬、金屬合金、聚合物(polymer)或另一適當結構材料所形成。半導體封裝件192之中介層170可由相同材質或不同材質所形成。在一實施例中，每個中介層170可定義一個或更多開孔171，其從中介層170之下表面172伸至中介層170之上表面173。一導通孔174係形成於每個開孔171。
如第1及2圖所示，中介層170可包括數個導通孔174。在一實施例中，導通孔174A形成於每個開孔171且可從下表面172及上表面173露出。在另一實施例中，導通孔174B可突出超過下表面172及上表面173。導通孔之其它實施例繪示於第3圖。導通孔174可直接地連接於圖案化導電層150。導通孔174可包括一內導電機制(inner conductive interconnect)275。內導電機制275係一電性元件，其可由金屬材料形成，傳統上係以電鍍、電性貼附(conductive paste)或其它本技術領域熟知此技藝者所知道的方法完成。視中介層170之介電層282之基板材料而定，導通孔174可包括介電材料之一外介電層282，其形成於內導電機制275與基板271(如第2及3圖所示)之間。外介電層282可以是環狀介電質之形式。
在一實施例中，導通孔174之直徑可以介於10微米(μm)與50 μm之間，例如是從約10 μm至約20 μm之間及從約20 μm至約50 μm之間。對於直徑介於約10 μm至約20 μm之導通孔174，導通孔174B之結構可被使用。對於直徑介於約20 μm至約50 μm之導通孔174，導通孔174A之結構可被使用。
封裝件192可包括一或更多重佈層(RDL)151，每個RDL包括圖案化導電層150及一介電層(或保護層)130。圖案化導電層可由銅、銅合金或其它金屬形成。重佈層151可鄰近(例如是設於、接近於或連接於)半導體裝置102之主動面104及封裝體114之下表面116設置。重佈層151可僅包括圖案化導電層150或可以是多層(multi-layered)結構。例如，除了介電層130及圖案化導電層150外，重佈層151可包括一介電層130，使圖案化導電層150設於介電層130與131之間。然於其它實施例中，可使用更多或更少的介電層。介電層130與131中每一者可由介電材料所形成，該介電材料係聚合體或非聚合體。例如，介電層130與131中至少一者可由聚亞醯胺(polyimide)、聚苯噁唑(polybenzoxazole，PBO)、苯環丁烯(benzocyclobutene)或其組合所形成。介電層130與131可由相同或不同介電材質所形成。於一實施例中，介電層130與131中至少一者可由介電材料所形成，該介電材料係光成像性(photoimageable)或感光性(photoactive)。當圖案化使用微影製程(photolithography)。
圖案化導電層150可經由介電層130之開孔136延伸至電性連接於導通孔174，且經由介電層130之開孔146電性連接於接合墊111。用以電性連接堆疊封裝組件100之外部的封裝接合墊175可由部分之圖案化導電層150所形成，部分之圖案化導電層150從介電層130之開孔137露出。
在一實施例中，半導體封裝件192可提供一二維扇出型結構，其圖案化導電層150實質上側向地延伸至半導體裝置102之一周緣177(如第2圖所示)之外。例如，第1圖繪示電性觸點(electrical contact)，其包括導電凸塊190，係至少部分地半導體裝置102之側周緣(lateral periphery)177(如第2圖所示)之外。導電凸塊190可從封裝件192之一下周緣195露出。此允許半導體封裝件192透過重佈層151及導電凸塊190電性連接至半導體封裝件192之外部的裝置。導電凸塊190可透過圖案化導電層150電性連接於半導體裝置102且鄰近封裝接觸墊175設置。導電凸塊190透過圖案化導電層150可電性連接於中介層170。
中介層層170包含導通孔174，藉由提供從半導體裝置102到包括導電凸塊193之電性觸點之間的電性路徑，導通孔174容易地從二維扇出結構延伸至三維扇出及/或扇入結構。導電凸塊193可從封裝件192之上周緣196延伸。此允許半導體封裝件192透過重佈層153及導電凸塊193電性連接至半導體封裝件192之外部的裝置。導電凸塊193可電性連接至上接觸墊176。上接觸墊176係由圖案化導電層152之一部分所構成，重佈層153包括圖案化導電層152且鄰近封裝體114之上表面設置。圖案化導電層152可設於介電層(或保護層)132與介電層133之間。圖案化導電層152可經過介電層132之開孔139延伸至電性連接於導通孔174。上接觸墊176係由圖案化導電層152中從介電層133之開孔138曝露出的部分所構成。重佈層153可具有與前面描述之重佈層152相似的結構特徵。
在一實施例中，重佈層153可不包括介電層132，使圖案化導電層152及介電層133可鄰近封裝體114之上表面118設置。本實施例中，圖案化導電層152亦可鄰近中介層170，如此，在此實施例中，中介層170應由非導電材料製成，例如是玻璃。有利地，只要圖案化導電層152鄰近中介層170之非導電部分，中介層170可包括第一部分及第二部分，第一部份由例如是矽(silicon)之材質所形成，而第二部分由例如是玻璃或其它介電材料之非導電材料所形成。
在一實施例中，藉由透過圖案化導電層152、導通孔174及圖案化導電層150電性連接導電凸塊193A與半導體裝置102，可製出三維扇出結構。有利地或此外，一三維扇入結構係過導電凸塊193B經由圖案化導電層152、導通孔174及圖案化導電層150電性連接於半導體裝置102而建立。此些三維扇入及/或扇出。相較於二維扇出結構，三維扇出及/或扇入結構大幅地增加對封裝體114之上表面之上以及封裝體114之下表面116之下的電性觸點在配置及分隔上的靈活性。如此可降低對半導體裝置102的接觸墊在配置與分隔上的依賴性。依照具有一扇出結構，導電凸塊193A係側向地設於半導體裝置102的周緣之外的至少一部分，依照一扇入結構，導電凸塊193A係側向地至少設於半導體封裝件102之周緣。一般來講導電凸塊190及193亦可設於周緣以內、周緣以外側或周緣之內外，使封裝件100可具有一扇出結構、一扇入結構或一扇出結構與一扇入結構之組合。本實施例中，導電凸塊190及193可以是錫凸塊(solder bump)，例如是回銲後的銲球(solder ball)。
圖案化導電層150、導通孔174及圖案化導電層152可由例如是金屬合金、具有金屬或散佈之金屬合金的基體(matrix)或適當的導電材料。例如，圖案化導電層150、導通孔174與圖案化導電層152中至少一者可由鋁、銅、鈦或其組合所形成。圖案化導電層150、導通孔174與圖案化導電層152可由相同或不同的導電材質形成。
第2圖繪示第1圖半導體封裝件192之A-A面的剖視圖。根據本發明一實施例，剖視圖繪示分離之中介層元件170，其設於半導體晶片102及封裝體114之四側之每者。分離之中介層元件170可從封裝體114之一側周緣115往內設置。封裝體114可環繞每個中介層170之一側周緣178延伸，以使每個中介層170之一側周緣178埋入封裝體114。此外，內導電機制275及外介電層282鄰近同一實施例之內導電機制275設置。外介電層282可環狀介電質之形式。內導電機制275可由類似於形成部分之導通孔174之導電材料所形成，如描述第1圖時所述。外介電層282可由類似於形成介電層130及131之材料所形成，如描述第1圖時所述。剖視圖亦顯示晶片102之上表面106。在此實施例中，不使用的導通孔174可保留不電性連接。
分離之中介層元件170可以切割自中介晶圓(interposer wafer)，依據任一半導體封裝件(如第8B圖所示)所需之貫孔連接(through via connection)的數量及位置，使中介層元件170具有多種尺寸及外形。此提供了從同一中介晶圓中取得具有不同貫孔連接之數量及位置的多種封裝件的製造彈性。此外，中介層元件170可形成對應每種封裝類型的尺寸，使得未使用之貫孔連接減少或消除。因為沒有需求，例如，形成每一封裝類型之一客製化基板去降低未使用之基板面積，故此方法可降低製造成本及複雜度。
此外，因為分離之中介層元件170相對封裝體114可以是小的，因此分離之中介層元件170對封裝件192之熱膨脹係數(CTE)係小的或不影響。反而，封裝體114之熱膨脹係數可調整與半導體裝置102之熱膨脹係數係較佳配合，以增加可靠度。例如，用以形成封裝體114的封膠之填入物(filler content)可被調整至使封裝體114之熱膨脹係數更接近半導體裝置102之熱膨脹係數。
第3圖繪示中介層元件170內之多種導通孔實施例之剖視圖。在一實施例中，中介層元件170定義開孔171且包括導通孔174A，導通孔174A至少部分地設於開孔171內，其中導通孔174A包括內導電機制275A。導通孔174A可以是矽穿孔(through silicon via,TSV)。導通孔174A包括內導電機制275A及外介電層282，導電機制275A從中介層元件170之上表面173及下表面172露出，外介電層282環繞內導電機制275A。外介電層282可鄰近開孔171之一側面381設置。在此實施例中，外介電層282及內導電機制275A可實質上填滿開孔171。
在另一實施例中，導通孔174B包括一內導電機制275B，其突出超過中介層170之上表面173及下表面172。在此實施例中，外介電層282亦可突出超過上表面173及下表面172。一導通層(conductive layer)383可鄰近內導電機制275B及外介電層282之突出部分設置。
在其它實施例中，一導通孔174C包括一內導電機制275C及外介電層282，內導電機制275C係環狀電鍍層。內導電機制275C可定義一開孔384。此外，內導電機制275C可被一內介電層(未繪示)填滿。
在其它實施例中，一導通孔174D包括一內導電機制275D。內導電機制275D直接地鄰近中介層元件170之基板271設置。在此實施例中，中介層元件170由非導電材料製成，非導電材料例如是玻璃。內導電機制275D可定義相似於開孔384之一開孔(未繪示)。
在其它實施例中，導通孔174A、174B、174C及174D係相似於導通孔174且執行相似之從頂部封裝件194至底部封裝件192及至導電凸塊190以分配封裝件100之外部的I/O至其它裝置(如第1圖所示)的繞線I/O功能。
中介層170之實施例係提供鄰近於半導體封裝件之上表面之重佈層(例如是第1圖之重佈層153)與鄰近於半導體封裝件之下表面之重佈層(例如是第1圖之重佈層151)之間的電性連接性的優點，可導致導通孔直徑之降低。例如，導通孔174可具有一介於約10微米(μm)與50 μm之間的直徑，例如是從約10 μm至約20 μm之間、從約20 μm至約30 μm之間，或從約30 μm至約50 μm之間。此直徑小於傳統之矽穿孔之直徑(大於75 μm)，其可以雷射鑽孔穿過封膠而形成。因為導通孔174的直徑降低，對應的擷取銲墊(capture pad)，例如是第1圖之圖案化導電層150及152的一部分可降低尺寸及間距。如此導致較高密度之重佈繞線(redistribution routing traces)之空間，例如是晶片102與中介層170之間的空間，且於執行繞線(routing)時不用增加額外的重佈層。相較於以雷射穿過封膠而鑽出尺寸較大的導通孔，每個導通孔174之較小直徑可允許較高的連接密度。此外，由於較小直徑，導通孔280可更快地被導電及/或非導電材質填滿，以避免例如是處理器的問題(processor solution)、聚合物洩漏及誘捕(entrapment)等不受歡迎的問題。
第4A至4B圖繪示依照本發明之一實施例之包括中介層470之半導體封裝件400之局部的剖視圖。半導體封裝件400及中介層470相似於第1圖之半導體封裝件192及中介層170，除了中介層470包括一導電機制440之外。如第4A圖所示，在半導體封裝件400A之一實施例中，導電機制440可設置於且沿中介層470A之下表面472A實質上側向地延伸。在此實施例中，一介電層441設於導電機制440與中介層470A之基板271之間。如第4A圖所示，在半導體封裝件400A之一實施例中，導電機制440可設於且沿中介層470B之一下表面472B實質上側向地延伸。在此實施例中，導電機制440鄰近於中介層470B之基板271，如此中介層470B應由非導電材料製成，例如是玻璃。有利地，只要導電機制440鄰近中介層470B的非導電部分，中介層470B可包括一第一部分及一第二部分，第一部份由例如是矽(silicon)之材質所形成，而第二部分由例如是玻璃或其它介電材料之非導電材料所形成。
導電機制440的一優點係導電機制440可做為重佈繞線的額外走線層，其可降低半導體封裝件400之重佈層的數量。半導體封裝件400之重佈層的數量的降低，可降低製造複雜性及製造成本。此外，由於導電機制440可被重佈層埋入，因此不會佔用半導體封裝件402之一外表面的空間。
在第4A及4B圖之實施例中，一半導體裝置(例如是第1圖之半導體裝置102)透過圖案化導電層150電性連接於上重佈層153，圖案化導電層150包括一下重佈層151、導電機制440及中介層元件470之導通孔174。下重佈層151可覆蓋導電機制440。另外，一保護層(未繪示)可設於導電機制440與下重佈層151之間。在一實施例中，導電機制440可電性連接半導體裝置102至一被動電性元件(如第5圖所示)。
如第4B圖所示，在一實施例中，介電層132(如第1圖所示)可省略上重佈層153，使圖案化導電層152鄰近中介層470B之基板271設置。在本實施例中，中介層470B由非導電材料製成，非導電材料例如是玻璃。
第5圖繪示。第5圖繪示依照本發明之一實施例的中介層470之底面的示意圖。中介層470包括數個導通孔174(例如是導通孔174A及174E)及數個導電機制440。導電機制440可形成一繞線層。在一實施例中，繞線層係在中介層470之下表面。導電機制440可連接導通孔174D至導通孔174E。在一實施例中，儘管導通孔174B可提供電性連接於圖案化導電層，例如是圖案化導電層150，導通孔174D可透過一半導體封裝件提供電性連接，該半導體封裝件例如是第4A及4B圖之半導體封裝件400。在藉由繞線橫跨中介層470至中介層470之一表面的過程中，重佈層繞線，導通孔440可允許橫跨導體上方。
在一實施例中，導電機制440可電性連接於導通孔174至一或多個本技術領域中習知技藝之一已知的被動電性元件，例如是電阻500、電感502及電容504。此些被動電性元件設於中介層470之下表面472，如同導電機制440。
第6圖繪示依照本發明一實施例之包括鄰近半導體裝置602之背面606露出之數個導通孔608的半導體裝置602的剖視圖。半導體裝置602大部分相似於第1圖之半導體裝置102，除了導通孔608之外。導通孔608相似於導通孔174。導通孔608的一優點係導通孔608形成於半導體裝置602。如此可降低或消除分離之中介層的需求，其可節省半導體封裝件的空間，例如是節省第1圖之半導體封裝件192的空間。在一實施例中，導通孔608可電性連接於半導體裝置602與重佈層，例如是第1圖之重佈層153。導通孔608可電性連接一晶片接合墊611至半導體裝置602之外部的電路，例如重佈層153之導電層152(如第1圖所示)。此外，導通孔608可電性連接半導體裝置602內之電路610至導體裝置602外之電路，例如是重佈層153之導電層152。
第7圖繪示依照本發明之實施例之半導體封裝件700之上視剖面圖。該剖視圖繪示中介層770環繞封裝體714，封裝體714包覆半導體裝置102。該剖視圖繪示中介層770之導通孔774。半導體封裝件700大部分相似於如描述第1圖時所述之半導體封裝件192，除了中介層770之外形。在本實施例中，中介層770係接觸中介層，其環繞半導體晶片102之側周緣177延伸。特別地，導通孔774及封裝體714係相似於如第1圖所示之導通孔174及封裝體114。
中介層770定義一開孔772，開孔772實質上被封裝體714填滿。封裝體714可減低或吸收(decouple)中介層770對半導體封裝件700作用的應力。在此實施例，未使用的導通孔774可維持未電性連接。
第8A圖至第8G圖繪示依照本發明一實施例之形成一半導體封裝件之一製造方法。為不使說明清楚，以下係以第1圖之封裝件192描述製造過程。然而，製造方法亦可應用於與封裝件192不同的半導體封裝件。此外，製造方法可應用於連接數個半導體封裝件之一陣列，可應用例如是切割(singulation)以形成多個分離之半導體封裝件。
第8A圖繪示一中介層晶圓(或中介層面板(interposer panel))800。中介層晶圓800可由玻璃、矽、金屬、金屬合金、聚合物或另一適當的結構材料所形成。中介層晶圓800包括導通孔804，其相似於第1至3圖之導通孔174及導通孔280。在一實施例中，導通孔804可整個延伸經過中介層晶圓800，且可突出超過一中介層870。中介層870可以是一分離、非接觸之中介層元件。有利地，導通孔804可曝露於中介層晶圓800之下表面806，但僅部分地延伸經過中介層晶圓800。中介層晶圓800之外形可以是圓形、矩形、正方形或任何本技術領域熟知此技藝者以可行製造方法所決定之外形。
接著，第8B圖繪示中介層870。中介層870可例如藉由包含本技術領域熟知此技藝者所知曉之切割方法，例如是鋸切割(saw singulation)，與中介層晶圓800隔離。分離中介層870與中介層晶圓800之一優點，係可使用一標準尺寸之中介層晶圓或面板800。可依據任何已知半導體封裝件對導通孔之數量及位置的需求，切割中介層晶圓800成為多種尺寸及外形之數個中介層。導通孔804可整個延伸經過中介層870，且可突出超過中介層870。有利地，如第8A圖所述之中介層晶圓800及導通孔804可僅部分地延伸經過中介層870。
然後，第8C圖繪示封膠結構810。在一實施例中，晶片102及一或多個中介層870，該些中介層870鄰近載板812設置。有利地，使用商業上可利用之拿取(pick)及放置(place)及/或晶片設置設備，晶片102及中介層870放置或定位於在載板上。晶片102及中介層870可藉由黏貼層814設置於載板812。在一實施例中，中介層870包括一導通孔874A，其從中介層870之下表面872露出。在另一實施例中，中介層870包括一導通孔874B，其突出超過下表面872至黏貼層814。然後，晶片102及中介層870被封膠材料(molding material)包覆以形成封膠結構810。封裝材料可環繞中介層870之一側周緣878。封膠結構810係由相似於形成第1圖之封裝114的材料所形成。封膠結構810可藉由使用數種封裝方法中任一種形成，例如是轉注成型(transfer molding)、注射成型(injection molding)。或壓縮成型(compression molding)。為了使封膠結構810在後續的切割步驟中在定位上更適當，可透過多種方法，例如是雷射標記形成定位標記(fiducial mark)於封膠結構810。
接著，第8D圖繪示封膠結構820。封膠結構820以下步驟形成：首先，從第8C圖之載板820上移除封膠結構810；然後，鄰近晶片102之主動面104、封裝體817之下表面816及每個中介層870之下表面872形成一重佈層包括重佈層151(如第1圖所示)。可藉由數種技術形成一介電材料，該些技術例如是印刷(printing)、旋塗(spinning)或噴塗(spraying)，然後圖案化形成一介電層130(如第1圖所示)。圖案化後，形成具有數個開孔之介電層130，該些開孔包括對齊主動面104及形成至少部分地曝露半導體封裝件102之晶片接合墊111之尺寸的開孔。在一實施例中，介電層更更包括數個開孔，其對齊且形成至少部分地曝露導通孔874A之尺寸。在另一實施例中，介電層包括數個開孔，導通孔874B延伸通過該開孔。形成介電層130而對介電材料的圖案化可應用數種方法之任一種完成，例如微影製程(photolithography)、化學蝕刻(chemical etching)、雷射鑽孔(laser drilling)或機械鑽孔(mechanical drilling)。且形成之開口可具有數種外形之任一種，例如是柱形或非柱形，柱形例如是圓形柱(circular cylindrical shape)、橢圓形柱(elliptic cylindrical shape)、方形柱(square cylindrical shape)或矩形柱(rectangular cylindrical shape)，而非柱形例如是錐形(cone)、漏斗(funnel)或另一錐形。開口的側面邊界亦可考量呈曲形(curved)或粗糙結構(roughly textured)。
接著使用數種技術之任一種塗佈一電性導電材料於介電層130且到達被介電層130定義之該些開孔，該些技術例如是化學氣相沈積、無電鍍法(electroless plating)、電解電鍍(electrolytic plating)、印刷、旋塗、噴塗、濺鍍(sputtering)或真空沈積法(vacuum deposition)。接著，圖案化電性導電材料以形成包括圖案化導電層150(如第1圖所示)之電性導電層。圖案化之後，圖案化導電層150、沿介電層130之特定方向側向地延伸之電性機制與曝露出介電層130之其它部分的數個電性機制之間的間距(gap)一起形成。包含於重佈層151之圖案化導電層150可電性連接至晶片接合墊111及導通孔874。電性導電層150之圖案化可由數種方法之任一種完成，該些方法包括微影製程(photolithography)、化學蝕刻(chemical etching)、雷射鑽孔(laser drilling)或機械鑽孔(mechanical drilling)。
接著使用數種技術之任一種塗佈介電材料於圖案化導電層150上，該些技術例如是印刷、旋塗或噴塗。然後，圖案化介電材料以形成包括介電層131(如第1圖所示)之介電層。圖案化後，形成具有數個開孔之介電層130，該些開孔對齊電性導電層150且包括對齊以至少部分地曝露出電性導電層150且形成以容納錫銲凸塊(solder bump)之尺寸的開孔。介電層131之圖案化可應用數種方法之任一種完成，例如微影製程、化學蝕刻、雷射鑽孔或機械鑽孔。且形成之開口可具有數種外形之任一種，例如是柱形或非柱形，柱形例如是圓形柱、橢圓形柱、方形柱或矩形柱，而非柱形例如是錐形、漏斗或另一錐形。開口的側面邊界亦可考量呈曲形或粗糙結構。
然後，第8E圖繪示封膠結構830。在一實施例中，移除中介層870之一部分以形成中介層170及封膠結構之一部分。傳統上藉由背面磨削(backgrinding)、化學平面研磨(CMP)或其它產生一實質上共面832之技術。
在第8E、8F圖之另一實施例中繪示一封裝結構840。除了執行額外的背面磨削或其它移除技術以露出半導體晶片602之背面606而導致晶片602、封裝體114及中介層170之間的一實質上共面836外，封裝結構840相似於第8E圖之封裝結構830。在一實施例中，若晶片對應於第6圖之晶片602，足夠的封膠結構被移除以曝露晶片602之背面606及導電機制610(如第6圖所示)。
然後，第8G圖繪示第2圖之半導體封裝件192。為了形成半導體封裝件192，鄰近封膠結構830(如第8E圖所示)之上表面832形成重佈層153。重佈層153之形成相似於重佈層151，且重佈層153電性連接於導電機制174。在一實施例中，接著沿虛線890執行切割，以分離該些半導體封裝件192。
綜上所述，雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100．．．堆疊封裝組件
102、402、602、702．．．半導體裝置
104．．．主動面
116、172、472、872．．．下表面
106、118、173．．．上表面
108．．．側面
111．．．晶片接合墊
114、714．．．封裝體
130、132、133．．．介電層
136、137、138、139、146、171．．．開孔
150、152．．．圖案化導電層
151、153．．．重佈層
170、470、770、870．．．中介層
174、174A、174B、608、774、874、874A、874B．．．導通孔
175．．．封裝接合墊
176．．．上接觸墊
190、193、193A、193B．．．導電凸塊
192、194．．．半導體封裝件
202．．．晶片
275、275A、275B、275C、275D．．．內導電機制
282．．．外介電層
440、610．．．導電機制
500．．．電阻
502．．．電感
504．．．電感
606．．．背面
800．．．中介層晶圓
810、820、830．．．封膠結構
814．．．黏貼層
832．．．實質上共面
890．．．虛線
第1圖繪示依照本發明之堆疊半導體組件之剖視圖。
第2圖繪示依照本發明一實施例之第1圖之半導體封裝件中A-A面的剖視圖。
第3圖繪示中介層之多種導通孔實施例的剖視圖。
第4A至4B圖繪示依照本發明之一實施例之包括中介層之半導體封裝件之局部的剖視圖。
第5圖繪示依照本發明之一實施例的中介層之一底面的示意圖。
第6圖繪示依照本發明一實施例之包括鄰近半導體裝置之背面的數個導通孔的半導體裝置的剖視圖。
第7圖繪示依照本發明之實施例之半導體封裝件之上視剖面圖。
第8A圖至第8G圖繪示依照本發明一實施例之形成半導體封裝件之一方法。
100．．．堆疊封裝組件
102．．．半導體裝置
104．．．主動面
106、118、173．．．上表面
108．．．側面
111．．．晶片接合墊
114．．．封裝體
116、172．．．下表面
130、132、133．．．介電層
136、137、138、139、146、171．．．開孔
150、152．．．圖案化導電層
151、153．．．重佈層
175．．．封裝接合墊
176．．．上接觸墊
174A、174B．．．導通孔
190、193、193A、193B．．．導電凸塊
192、194．．．半導體封裝件

Claims (17)

  1. 一種半導體封裝件，包括：至少一半導體晶片，具有一主動面；一中介層元件(interposer element)，具有一上表面及一下表面，該中介層元件具有至少一導通孔(conductive via)，該至少一導通孔延伸於該上表面與該下表面之間，該中介層元件包含一基板材料，該基板材料係金屬或玻璃，其中該中介層元件係複數個分離之中介層元件之一者，該些分離之中介層元件係環繞該半導體晶片之一側周緣；一封裝體(package body)，包覆部分之該主動晶片及部分之該中介層元件；以及一下重佈層(redistribution layer)，係電性連接該中介層元件與該半導體晶片之該主動面。
  2. 如申請專利範圍第1項所述之半導體封裝件，更包括：一上重佈層，係鄰近於該中介層元件之該上表面。
  3. 如申請專利範圍第2項所述之半導體封裝件，更包括：一電性觸點(electrical contact)，係從該半導體封裝件之一上周緣露出，其中該電性觸點係電性連接另一半導體封裝件與該上重佈層。
  4. 如申請專利範圍第1項所述之半導體封裝件，其中該基板材料係玻璃，該導通孔包括一內導電機制(conductive interconnect)，該基板材料直接包覆該內導電機制。
  5. 如申請專利範圍第1項所述之半導體封裝件，其中該基板材料係金屬，該導通孔包括一內導電機制及一外介電層，該外介電層環繞該內導通機制，且介於該基板材料與該內導電機制之間。
  6. 如申請專利範圍第5項所述之半導體封裝件，其中該內導通機制從該中介層元件之該下表面露出以電性連接於該下重佈層。
  7. 如申請專利範圍第5項所述之半導體封裝件，其中該內導電機制突出超過該中介層元件之該下表面以電性連接於該下重佈層。
  8. 如申請專利範圍第5項所述之半導體封裝件，更包括：一上重佈層，係鄰近於該中介層元件之該上表面；其中，該內導電機制係與該中介層元件之該上表面共面，以電性連接於該上重佈層。
  9. 如申請專利範圍第1項所述之半導體封裝件，其中該中介層元件包括：一繞線層(routing layer)，係沿該中介層元件之一下表面側向地延伸。
  10. 如申請專利範圍第9項所述之半導體封裝件，其中該繞線層包括：一被動電性元件(passive electrical component)，係鄰近於該中介層元件之該下表面，其中，該繞線層電性連接該被動電性元件與該至少一導通孔。
  11. 一種半導體封裝件，包括： 至少一半導體晶片，具有一主動面；一中介層元件，具有一上表面及一下表面，該中介層元件具有至少一導通孔，該至少一導通孔延伸於該上表面與該下表面之間，該中介層元件包含一基板材料，該基板材料係金屬或玻璃，其中該中介層元件係複數個分離之中介層元件之一者，該些分離之中介層元件係環繞該半導體晶片之一側周緣；一封裝體，包覆部分之該主動晶片及部分之該中介層元件；一下重佈層，電性連接該中介層元件與該半導體晶片之該主動面；以及一電性觸點，係從該半導體封裝件之一下周緣露出；其中，該下重佈層係電性連接該電性觸點與該半導體晶片之該主動面及該中介層元件，該下重佈層係鄰近該半導體晶片之該主動面設置。
  12. 如申請專利範圍第11項所述之半導體封裝件，更包括：一上重佈層，係鄰近於該中介層元件之該上表面。
  13. 如申請專利範圍第11項所述之半導體封裝件，其中該封裝體環繞各該分離之中介層元件之一側周緣延伸。
  14. 一種半導體封裝件之形成方法，包括：提供一半導體晶片，該半導體晶片具有一主動面；鄰近該半導體晶片放置一中介層元件，該中介層元件 具有一上表面及一下表面，該中介層元件具有至少一第一導通孔，該至少一第一導通孔延伸至該下表面，該中介層元件包含一基板材料，該基板材料係金屬或玻璃；以一包覆劑(encapsulant)，包覆部分之該半導體晶片及部分之該中介層元件，使該半導體晶片之該主動面、該中介層元件之該下表面及部分之該包覆劑形成一實質上共面(substantially coplanar surface)；以及形成一下重佈層於該實質上共面，該下重佈層係電性連接於該中介層元件與該半導體晶片之該主動面。
  15. 如申請專利範圍第14項所述之形成方法，更包括：移除該中介層元件之一部分，以露出該第一導通孔於該中介層元件之該上表面。
  16. 如申請專利範圍第14項所述之形成方法，其中於該包覆部分之該半導體晶片及部分之該中介層元件之該步驟包括：以該包覆劑，環繞該中介層元件之一側周緣。
  17. 如申請專利範圍第16項所述之形成方法，其中該半導體晶片定義一第二導通孔，該第二導通孔從該半導體晶片之該主動面延伸至該半導體晶片之一背面；以及，該第二導通孔係電性連接於該半導體晶片及該上重佈層。
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