TW201742203A - 整合扇出型封裝及其製造方法 - Google Patents

整合扇出型封裝及其製造方法 Download PDF

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TW201742203A
TW201742203A TW105124753A TW105124753A TW201742203A TW 201742203 A TW201742203 A TW 201742203A TW 105124753 A TW105124753 A TW 105124753A TW 105124753 A TW105124753 A TW 105124753A TW 201742203 A TW201742203 A TW 201742203A
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Taiwan
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conductive
layer
integrated circuit
vias
contact
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TW105124753A
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English (en)
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邱銘彥
張兢夫
黃信傑
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台灣積體電路製造股份有限公司
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Publication of TW201742203A publication Critical patent/TW201742203A/zh

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Abstract

一種整合扇出型封裝，其包括積體電路、絕緣包封體、多個導電通孔以及重配置線路結構。積體電路包括多個導電端子。絕緣包封體包覆積體電路的側壁。導電通孔貫穿絕緣包封體。重配置線路結構被配置於積體電路、導電通孔以及絕緣包封體上。重配置線路結構電性連接導電端子以及導電通孔。導電端子的多個第一接觸表面以及導電通孔的多個第二接觸表面與重配置線路結構接觸，且第一接觸表面以及第二接觸表面的粗糙度介於100埃到500埃之間。本發明實施例亦提供形成整合扇出型封裝的方法。

Description

整合扇出型封裝及其製造方法
本發明實施例是有關於一種半導體結構，且特別是有關於一種整合扇出型封裝。
由於不同電子元件(例如是電晶體、二極體、電阻、電容等)的積體密度持續地增進，半導體工業經歷了快速成長。大部分而言，積體密度的增進是來自於最小特徵尺寸(feature size)上不斷地縮減，這允許更多的較小元件整合到一給定區域內。較小的電子元件會需要面積比以往的封裝更小的較小封裝。半導體元件的其中一部分較小型式的封裝包括有四面扁平封裝(quad flat packages，QFPs)、接腳柵格陣列(pin grid array，PGA)封裝、球狀柵格陣列(ball grid array，BGA)封裝等等。
目前，整合扇出型封裝由於其密實度(compactness)而趨於熱門。在整合扇出型封裝中，形成在封裝膠體上的重配置線路結構的可靠度是積體電路封裝過程中重要的課題。
本揭露提供一種整合扇出型封裝及其製造方法。
本揭露提供一種整合扇出型封裝，其包括積體電路、絕緣包封體、多個導電通孔以及重配置線路結構。積體電路包括多個導電端子。絕緣包封體包覆所述積體電路的側壁。導電通孔貫穿絕緣包封體。重配置線路結構被配置於積體電路、導電通孔以及絕緣包封體上。重配置線路結構電性連接導電端子以及導電通孔。導電端子的多個第一接觸表面以及導電通孔的多個第二接觸表面與重配置線路結構接觸，且第一接觸表面以及第二接觸表面的粗糙度介於100埃到500埃之間。
本揭露提供一種形成整合扇出型封裝的方法，其包括下列步驟。提供多個導電通孔以及具有多個導電端子的積體電路。導電通孔、導電端子以及積體電路的多個側壁被絕緣材料所包覆。對絕緣材料進行機械研磨直到導電端子的多個第一接觸表面以及導電通孔的多個第二接觸表面被暴露出來，以形成絕緣包封體。在積體電路、導電通孔以及絕緣包封體的第一表面上形成重配置線路結構。重配置線路結構電性連接導電端子以及導電通孔。
本揭露提供一種形成整合扇出型封裝的方法，其包括下列步驟。提供其上配置有剝離層以及介電層的載板，其中剝離層位於載板以及介電層之間。提供積體電路以及多個在介電層上的導電通孔於介電層上，其中積體電路包括多個導電端子。導電通孔、導電端子以及積體電路的多個側壁被絕緣材料所包覆。對絕緣材料進行機械研磨直到導電端子的多個第一接觸表面以及導電通孔的多個第二接觸表面被暴露出來，以形成絕緣包封體。在積體電路、導電通孔以及絕緣包封體的第一表面上形成重配置線路結構，其中重配置線路結構電性連接導電端子以及導電通孔。載板被從介電層上剝離下來。
在前述的實施例中，整合扇出型封裝的製造成本低。此外，整合扇出型封裝具有好的可靠度以及良率。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
以下揭露內容提供用於實施所提供的標的之不同特徵的許多不同實施例或實例。以下所描述的構件及配置的具體實例是為了以簡化的方式傳達本揭露為目的。當然，這些僅僅為實例而非用以限制。舉例來說，於以下描述中，在第一特徵上方或在第一特徵上形成第二特徵可包括第二特徵與第一特徵形成為直接接觸的實施例，且亦可包括第二特徵與第一特徵之間可形成有額外特徵使得第二特徵與第一特徵可不直接接觸的實施例。此外，本揭露在各種實例中可使用相同的元件符號及/或字母來指代相同或類似的部件。元件符號的重複使用是為了簡單及清楚起見，且並不表示所欲討論的各個實施例及/或配置本身之間的關係。
另外，為了易於描述附圖中所繪示的一個構件或特徵與另一組件或特徵的關係，本文中可使用例如「在...下」、「在...下方」、「下部」、「在…上」、「在…上方」、「上部」及類似術語的空間相對術語。除了附圖中所繪示的定向之外，所述空間相對術語意欲涵蓋元件在使用或操作時的不同定向。設備可被另外定向（旋轉90度或在其他定向），而本文所用的空間相對術語相應地作出解釋。
圖1至圖11為依照一些實施例所繪示的一種形成整合扇出型封裝的製程流程，而圖12為依照一些實施例所繪示的一種堆疊式封裝結構的剖面圖。
參照圖1，提供一晶圓100包括陣列排列的多個晶粒(dies)或積體電路200。在對晶圓100進行晶圓切割製程前，晶圓100中的積體電路200彼此相連。在一些實施例中，晶圓100包括半導體基板110、形成於半導體基板110上的多個導電墊120以及鈍化層130。鈍化層130形成於半導體基板110上以部分覆蓋導電墊120，並且鈍化層130包括多個接觸開口132。換言之，在基板110上的導電墊120被鈍化層130的接觸開口132所部分暴露。舉例來說，半導體基板110可以是其中形成有主動元件(例如電晶體等)以及被動元件(例如電阻、電容器、電感器等)的矽基板；導電墊120可以是鋁墊、銅墊或其他合適的金屬墊；且鈍化層130可以是氧化矽層、氮化矽層、氮氧化矽層或由其他合適的介電材料所形成的介電層。
如圖1所示，在一些實施例中，晶圓100可更包括形成於鈍化層130上的後鈍化層(post passivation)140。後鈍化層140覆蓋鈍化層130並具有多個接觸開口142。被鈍化層130的接觸開口132所暴露的導電墊120被後鈍化層140所部分所覆蓋。換言之，導電墊120被後鈍化層140的接觸開口142所部分暴露。舉例來說，後鈍化層140可以是聚醯亞胺(polyimide, PI)層、聚苯二唑(polybenzoxazole, PBO)層、或由其他合適的聚合物所形成的介電層。
參照圖2，形成多個導電柱(conductive pillars)或導電孔(conductive vias)150於導電墊120上。在一些實施例中，導電柱或導電孔150是藉由電鍍方式形成在導電墊120上。舉例來說，首先，種子層被濺鍍於被接觸開口142所暴露出的後鈍化層140以及導電墊120上；以微影(photolithography)方式於種子層上形成用以暴露出導電墊120的圖案化光阻層(未繪示)；接著，將已形成有圖案化光阻層的晶圓100浸入電鍍溶液中，以使導電柱或導電孔150藉由電鍍的方式形成於對應導電墊120的種子層上。在完成導電柱或導電孔150的電鍍之後，剝除圖案化光阻層。之後，以導電柱或導電孔150作為硬罩幕(hard mask)，將部分未被導電柱或導電孔150所覆蓋的種子層移除，直到後鈍化層140被暴露。種子層例如是被蝕刻而移除。
在一些實施例中，導電柱或導電孔150為銅柱(copper pillars)或銅通孔(copper vias)。
參照圖3，在形成導電柱或導電孔150之後，在後鈍化層140上形成保護層160以覆蓋導電柱或導電孔150。在一些實施例中，保護層160可以是聚苯二唑層、聚醯亞胺層或其他合適的聚合物。在另一些實施例中，保護層160可以是由無機材料所形成。
參照圖4，在保護層160形成後，對晶圓100的後表面進行背面研磨製程。在進行背面研磨製程時，半導體基板110被研磨而形成具有半導體基板110’的薄化晶圓100’。
參照圖5，在進行背面研磨製程後，對薄化晶圓100’進行晶圓切割製程以使晶圓100中的積體電路200彼此分離。如圖5所示，經過切割後的各個積體電路200分別包括半導體基板110a、形成在半導體基板110a上的導電墊120、鈍化層130a、後鈍化層140a、導電柱或導電孔150以及保護層160a。導電墊120以及導電孔150的電性連接可以被視為是積體電路200的導電端子。半導體基板110a、鈍化層130a、後鈍化層140a以及保護層160a的材料與半導體基板100、鈍化層130、後鈍化層140以及保護層160的材料相似。因此，此處省略了關於半導體基板110a、鈍化層130a、後鈍化層140a以及保護層160a的詳細描述。
如圖4以及圖5所示，在進行背面研磨以及晶圓切割製程個過程中，保護層160以及160a可保護積體電路200的導電端子(例如導電墊120以及導電孔150)。此外，積體電路200的導電墊120以及導電孔150可被保護而免於被接下來進行的製程損害，例如積體電路200的轉移製程(pick-up and placing process)、模製製程(molding process)等。
參照圖6，在積體電路200被從薄化晶圓100’單體化之後，提供具有剝離層DB及介電層DI形成於其上的載板C，其中剝離層DB位於載板C以及介電層DI之間。在一些實施例中，載板C例如是玻璃基板，剝離層DB例如是形成於玻璃基板上的光熱轉換(light-to-heat conversion, LTHC)釋放層，且介電層DI例如為形成於剝離層DB上的聚苯二唑層。
在提供具有剝離層DB及介電層DI形成於其上的載板C之後，於介電層DI上形成多個導電通孔TV。在一些實施例中，多個導電通孔TV是以光刻、電鍍以及光阻移除製程所形成。舉例來說，導電通孔TV包括銅柱。
如圖6所示，在一些實施例中，可將具有導電端子(例如導電墊120以及導電孔150)以及保護層160a形成於其上的一個積體電路200轉移到介電層DI上。積體電路200藉由晶粒附著膜、黏附膏等附著或黏附在介電層DI上。在另一些實施例中，可將多個積體電路200轉移到介電層DI上，其中被轉移而設置於介電層DI上的積體電路200可排列成陣列。當被設置於介電層DI上的積體電路200被排列成陣列時，導電通孔TV可被分成多個群組。積體電路200的數目對應於導電通孔TV的群組數目。
如圖6所示，保護層160a的頂表面例如是低於導電通孔TV的頂表面，且保護層160a的頂表面例如是高於導電柱或導電孔150的頂表面。然而，本揭露並不僅限於此。在另一些實施例中，保護層160a的頂表面可以實質上對齊導電通孔TV的頂表面，且保護層160a的頂表面可高於導電柱或導電孔150的頂表面。
如圖6所示，一個或多個積體電路200可在導電通孔TV形成之後才被轉移到介電層DI上。然而，本揭露並不僅限於此。在另一些實施例中，一個或多個積體電路200可在導電通孔TV形成之前被轉移到介電層DI上。
參照圖7，於介電層DI上形成絕緣材料210以覆蓋積體電路200以及導電通孔TV。在一些實施例中，絕緣材料210是由模製製程所形成的封裝膠體。積體電路200的導電柱或導電孔150以及保護層160a被絕緣材料210所覆蓋。換言之，積體電路200的導電柱或導電孔150以及保護層160a並不會被顯露出來，且被絕緣材料210所保護。在一些實施例中，絕緣材料210包括環氧化合物或其他合適的樹脂。
參照圖8，接著，對絕緣材料210進行機械研磨直到導電柱或導電孔150 (例如是導電端子)的第一接觸表面(例如是頂表面)、導電通孔TV的第二接觸表面(例如是頂表面)以及保護層160a的頂表面被暴露出來。在絕緣材料210被機械研磨之後，絕緣包封體210’會形成於介電層DI上，且導電孔150的第一接觸表面以及導電通孔TV的第二接觸表面的粗糙度(Ra, 平均粗糙度)介於100埃到500埃之間。在一些實施例中，導電孔150的第一接觸表面以及導電通孔TV的第二接觸表面的粗糙度可介於250埃到400埃之間，例如是300埃。在一些實施例中，在絕緣材料210被機械研磨之後，導電孔150的第一接觸表面以及導電通孔TV的第二接觸表面上會形成多個研磨記號(grinding marks)。舉例來說，形成在導電孔150的第一接觸表面以及導電通孔TV的第二接觸表面上的研磨記號的深度可以介於100埃到500埃之間。在一些實施例中，研磨記號的寬度介於約300埃到1000埃之間。舉例來說，研磨記號的寬度介於約500埃到800埃之間。
在對絕緣材料210進行研磨製程期間，部分的保護層160a會被研磨而形成保護層160a’。在一些實施例中，在對絕緣材料210以及保護層160a進行研磨製程期間，部分的導電通孔TV也被研磨。
如圖8所示，絕緣包封體210’包覆積體電路200的側壁，且絕緣包封體210’被導電通孔TV所貫穿。換言之，積體電路200以及導電通孔TV嵌於絕緣包封體210’中。導電通孔TV可更包括多個相對於第二接觸表面(例如頂表面)的第三接觸表面(例如底表面)。絕緣包封體210’可包括第一表面S1以及相對於第一表面S1的第二表面S2。導電孔150的第一接觸表面以及導電通孔TV的第二接觸表面在絕緣包封體210’的第一表面S1被暴露出來，而導電通孔TV的第三接觸表面與介電層DI接觸。導電孔150的第一接觸表面以及導電通孔TV的第二接觸表面實質上與絕緣包封體210’的第一表面S1共平面。導電通孔TV的第三接觸表面實質上與絕緣包封體210’的第二表面S2共平面。值得注意的是，導電通孔TV的接觸表面、絕緣包封體210’的第一表面S1(例如頂表面)以及導電孔150的接觸表面實質上與保護層160a’的頂表面共平面。
值得注意的是，本實施例之絕緣包封體210’是經由機械研磨後形成，不需要更進一步進行化學機械研磨(chemical mechanical polishing, CMP)。因此，導電孔150的第一接觸表面、導電通孔TV的第二接觸表面、絕緣包封體210’的第一表面S1以及保護層160a’的頂表面具有足夠的粗糙度，以提升研磨表面以及後續所形成的膜層之間的附著力。
前述的研磨記號不只存在於導電孔150的第一接觸表面以及導電通孔TV的第二接觸表面上，還存在於絕緣包封體210’的第一表面S1以及保護層160a’的頂表面上。
參照圖9，在形成絕緣包封體210’ 以及保護層160a’之後，於導電通孔TV的第一接觸表面、絕緣包封體210’的第一表面S1、導電孔150的第二接觸表面以及保護層160a’的頂表面上形成與積體電路200的導電柱或導電孔150電性連接的重配置線路結構220。重配置線路結構220被形成來電性連接一個或多個位於其下的連接端子。此處，前述的連接端子可以是積體電路200的導電柱或導電孔150及/或被嵌於絕緣包封體210’中的導電通孔TV。以下將搭配圖9，針對重配置線路結構220僅行詳細之說明。
參照圖9，重配置線路結構220包括彼此交替堆疊的多個內介電層(inter-dielectric layers)222以及多個重配置導電層224，且重配置導電層224與積體電路200的導電孔150以及嵌於絕緣包封體210’的導電通孔TV電性連接。如圖9所示，在一些實施例中，導電孔150的第一接觸表面以及導電通孔TV的第二接觸表面會與重配置線路結構220接觸。導電孔150的第一接觸表面以及導電通孔TV的第二接觸表面被最底層的內介電層222所部分覆蓋。此外，最頂層的重配置導電層224包括多個接墊。在一些實施例中，前述的接墊包括用來植球(ball mount)的多個球底金屬層(under-ball metallurgy, UBM)圖案224a及/或用來設置被動元件的至少一個連接墊224b。本揭露並不限制球底金屬層圖案224a以及連接墊224b的數目。
由於研磨記號是形成於導電孔150的第一接觸表面、導電通孔TV的第二接觸表面、絕緣包封體210’的第一表面S1以及保護層160a’的頂表面上，因此前述的研磨表面以及重配置線路結構220之間的附著力可被有效地提升。因此，重配置線路結構220的製造良率以及可靠度可被提升。
請參照圖9的放大部分，最底層的內介電層222可具有多個暴露出導電通孔TV的第一接觸開口以及多個暴露出導電孔150的第二接觸開口，其中暴露出導電通孔TV的第一接觸開口的寬度A1例如介於10微米至50微米之間，且暴露出導電孔150的第二接觸開口的寬度A2例如介於10微米至20微米之間。如圖9的放大部分所示，導電通孔TV的寬度B1例如介於60微米至250微米之間，且導電孔150的寬度B2例如介於50微米至100微米之間。寬度差C1(例如第一寬度差C1)例如介於寬度A1以及寬度B1之間，且另一寬度差C2(例如第二寬度差C2)例如介於寬度A2以及寬度B2之間。在導電通孔TV以及最底層的內介電層222之間的對準誤差(mis-alignment)可被寬度差C1所補償，且在導電孔150以及最底層的內介電層222之間的對準誤差可被寬度差C2所補償。在一些實施例中，寬度差C1大於寬度差C2。舉例來說，寬度差C1例如介於20微米至120微米之間，且寬度差C2例如介於10微米至45微米之間。在另一些實施例中，寬度差C1以及寬度差C2之間的比值可以介於約0.44至約12之間。
如圖9所示，在形成重配置線路結構220後，將多個導電球230置於球底金屬層圖案224a上，並將多個被動元件240設置於連接墊224b上。在一些實施例中，導電球230可以植球製程的方式被置於球底金屬層圖案224a上，且被動元件240可設置於連接墊240上，並且藉由焊料與連接墊240電性連接。
參照圖9以及圖10，在將導電球230以及被動元件240設置於重配置線路結構220之後，將形成於絕緣包封體210’的第二表面S2上的介電層DI從剝離層DB上剝離，以使介電層DI與載板C分離。在一些實施例中，剝離層DB(例如光熱轉換釋放層)可被紫外光雷射照射而使介電層DI從載板C上剝離。如圖10所示，介電層DI接著被圖案化而形成多個接觸開口O來暴露出導電通孔TV的第三接觸表面(例如底表面)。接觸開口O的數目對應於導電通孔TV的數目。在一些實施例中，介電層DI的接觸開口O是由雷射鑽孔製程所形成。
參照圖11，在形成接觸開口O於介電層DI中之後，將多個導電球250設置於被接觸開口O所暴露出來的導電通孔TV的第三接觸表面上。並且，導電球250例如是藉由迴焊的方式與導電通孔TV的第三接觸表面連接。如圖11所示，在形成導電球230與導電球250之後，具有雙邊端子設計的積體電路200的整合扇出型封裝便已完成。
參照圖12，提供另一個封裝300。在一些實施例中，封裝300例如是記憶體或其他電子元件的封裝。如圖11所繪示，封裝300可藉由導電球250而堆疊在整合扇出型封裝上，並與其電性連接，從而形成堆疊式封裝結構(POP)。
在前述的實施例中，整合扇出型封裝的製造成本低。此外，整合扇出型封裝具有好的可靠度以及良率。
以上概述了多個實施例的特徵，使本領域具有通常知識者可更佳了解本揭露的態樣。本領域具有通常知識者應理解，其可輕易地使用本揭露作為設計或修改其他製程與結構的依據，以實行本文所介紹的實施例的相同目的及/或達到相同優點。本領域具有通常知識者還應理解，這種等效的配置並不悖離本揭露的精神與範疇，且本領域具有通常知識者在不悖離本揭露的精神與範疇的情況下可對本文做出各種改變、置換以及變更。
A1‧‧‧寬度
A2‧‧‧寬度
B1‧‧‧寬度
B2‧‧‧寬度
C‧‧‧載板
C1‧‧‧寬度差
C2‧‧‧寬度差
DB‧‧‧剝離層
DI‧‧‧介電層
O‧‧‧接觸開口
S1‧‧‧第一表面
S2‧‧‧第二表面
TV‧‧‧導電通孔
100‧‧‧晶圓
110‧‧‧半導體基板
110a‧‧‧半導體基板
120‧‧‧導電墊
130‧‧‧鈍化層
130a‧‧‧鈍化層
132‧‧‧接觸開口
140‧‧‧後鈍化層
140a‧‧‧後鈍化層
142‧‧‧接觸開口
150‧‧‧導電柱或導電孔
160‧‧‧保護層
160a‧‧‧保護層
160a’‧‧‧保護層
170‧‧‧球底金屬層圖案
172‧‧‧連接墊
200‧‧‧積體電路
210‧‧‧絕緣材料
210’‧‧‧絕緣包封體
220‧‧‧重配置線路結構
222‧‧‧內介電層
224‧‧‧重配置導電層
224a‧‧‧球底金屬層圖案
224b‧‧‧連接墊
230‧‧‧導電球
240‧‧‧被動元件
250‧‧‧導電球
300‧‧‧封裝
圖1至圖11為依照一些實施例所繪示的一種形成整合扇出型封裝的製程流程。 圖12為依照一些實施例所繪示的一種堆疊式封裝(package-on-package, POP)結構的剖面圖。
DI‧‧‧介電層
O‧‧‧接觸開口
S1‧‧‧第一表面
S2‧‧‧第二表面
TV‧‧‧導電通孔
110a‧‧‧半導體基板
120‧‧‧導電墊
130a‧‧‧鈍化層
140a‧‧‧後鈍化層
150‧‧‧導電柱或導電孔
160a’‧‧‧保護層
200‧‧‧積體電路
210’‧‧‧絕緣包封體
220‧‧‧重配置線路結構
222‧‧‧內介電層
224‧‧‧重配置導電層
224a‧‧‧球底金屬層圖案
224b‧‧‧連接墊
230‧‧‧導電球
240‧‧‧被動元件
250‧‧‧導電球
300‧‧‧封裝

Claims (1)

  1. 一種整合扇出型封裝，包括： 一積體電路，包括多個導電端子； 一絕緣包封體，包覆該積體電路的側壁； 多個導電通孔，貫穿該絕緣包封體；以及 一重配置線路結構，配置於該積體電路、該些導電通孔以及該絕緣包封體上，該重配置線路結構電性連接該些導電端子以及該些導電通孔，其中該些導電端子的多個第一接觸表面以及該些導電通孔的多個第二接觸表面與該重配置線路結構接觸，且該些第一接觸表面以及該些第二接觸表面的粗糙度介於約100埃到約500埃之間。
TW105124753A 2016-05-17 2016-08-04 整合扇出型封裝及其製造方法 TW201742203A (zh)

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