TWI711056B - 導電圖案 - Google Patents
導電圖案 Download PDFInfo
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- TWI711056B TWI711056B TW106101345A TW106101345A TWI711056B TW I711056 B TWI711056 B TW I711056B TW 106101345 A TW106101345 A TW 106101345A TW 106101345 A TW106101345 A TW 106101345A TW I711056 B TWI711056 B TW I711056B
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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Abstract
一種導電圖案,其包括:導電墊,包括圓形墊部及連接至圓形墊部的第一收斂部,第一收斂部具有一對不平行的第一邊緣,不平行的第一邊緣界定第一錐度角,且不平行的第一邊緣由圓形墊部的一對不平行的第一切線界定;以及緩衝延伸部,連接至導電墊的第一收斂部,緩衝延伸部至少包括具有一對不平行的第二邊緣的第二收斂部,不平行的第二邊緣界定第二錐度角,第一錐度角大於或等於第二錐度角。
Description
本發明的實施例是有關於一種導電圖案。
由於不同電子元件(例如是電晶體、二極體、電阻、電容等)的積體密度持續地增進,半導體工業經歷了快速成長。大部分而言,積集度的增進是來自於最小特徵尺寸(feature size)上不斷地縮減,這允許更多的較小元件能夠被整合到一預定區域內。較小的電子元件會需要比以往體積更小的封裝。較小型的半導體元件封裝包括有四面扁平封裝(quad flat packages,QFPs)、接腳柵格陣列(pin grid array,PGA)封裝、球狀柵格陣列(ball grid array,BGA)封裝等等。
目前,集成扇出型封裝件因其緊湊性(compactness)而正變得日漸流行。在集成扇出型封裝件中,以模塑化合物(molding compound)製作的重佈線路結構的可靠性得到高度關注。
依據本發明的一些實施例,提出一種導電圖案,其包括:導電墊,包括圓形墊部及連接至圓形墊部的第一收斂部,第一收斂部具有一對不平行的第一邊緣,不平行的第一邊緣界定第一錐度角,且不平行的第一邊緣由圓形墊部的一對不平行的第一切線界定;以及緩衝延伸部,連接至導電墊的第一收斂部,緩衝延伸部至少包括具有一對不平行的第二邊緣的第二收斂部,不平行的第二邊緣界定第二錐度角,第一錐度角大於或等於第二錐度角。
以下揭露內容提供用於實施所提供的標的之不同特徵的許多不同實施例或實例。以下所描述的構件及配置的具體實例是為了以簡化的方式傳達本揭露為目的。當然,這些僅僅為實例而非用以限制。舉例來說,於以下描述中,在第一特徵上方或在第一特徵上形成第二特徵可包括第二特徵與第一特徵形成為直接接觸的實施例,且亦可包括第二特徵與第一特徵之間可形成有額外特徵使得第二特徵與第一特徵可不直接接觸的實施例。此外,本揭露在各種實例中可使用相同的元件符號及/或字母來指代相同或類似的部件。元件符號的重複使用是為了簡單及清楚起見,且並不表示所欲討論的各個實施例及/或配置本身之間的關係。
另外,為了易於描述附圖中所繪示的一個構件或特徵與另一元件或特徵的關係,本文中可使用例如「在...下」、「在...下方」、「下部」、「在…上」、「在…上方」、「上部」及類似術語的空間相對術語。除了附圖中所繪示的定向之外,空間相對術語意欲涵蓋元件在使用或操作時的不同定向。設備可被另外定向(旋轉90度或在其他定向),而本文所用的空間相對術語相應地做出解釋。
圖1至圖13說明製作根據某些實施例的集成扇出型封裝件的製造流程,且圖14是說明根據某些實施例的疊層封裝(POP)結構的剖視圖。
參照圖1,提供包括排列成陣列的多個晶粒(die)或積體電路200的晶圓100。在對晶圓100進行晶圓切割(wafer dicing)製程之前,晶圓100中的積體電路200是彼此連接的。在某些實施例中,晶圓100包括半導體基底110、形成在半導體基底110上的多個導電墊120及鈍化層130。鈍化層130形成在半導體基底110之上且具有多個接觸開口132,進而使得導電墊120被鈍化層130的接觸開口132局部地暴露出。例如,半導體基底110可為矽基底,矽基底包括形成在矽基底中的主動元件(例如,電晶體等)及被動元件(例如,電阻器、電容器、電感器等);導電墊120可為鋁墊、銅墊或其他適合的金屬墊;且鈍化層130可為氧化矽層、氮化矽層、氮氧化矽層或由其他適合的介電材料形成的介電層。
如圖1中所示,在某些實施例中,晶圓100可視情況包括形成在鈍化層130之上的後鈍化(post-passivation)層140。後鈍化層140覆蓋鈍化層130且具有多個接觸開口142。被鈍化層130的接觸開口132所暴露出的導電墊120會被後鈍化層140的接觸開口142局部地暴露出。後鈍化層140可為聚醯亞胺(polyimide,PI)層、聚苯並惡唑(polybenzoxazole,PBO)層或由其他適合的聚合物形成的介電層。
參照圖2,在導電墊120上形成多個導電柱150。在某些實施例中,導電柱150是電鍍(plate)在導電墊120上。以下詳細闡述導電柱150的電鍍製程。首先,將晶種層濺鍍在後鈍化層140及被接觸開口142所暴露出的導電墊120上。接著,藉由微影(photolithography)製程在晶種層之上形成圖案化光阻(photoresist)層(圖中未示出),其中圖案化光阻層暴露出晶種層與導電墊120對應的部分。接著,將有圖案化光阻層形成於其上的晶圓100浸入至電鍍槽(plating bath)的電鍍溶液中,進而使得導電柱150電鍍在晶種層與導電墊120對應的部分上。在電鍍形成導電柱150之後,剝除圖案化光阻層。此後,利用導電柱150作為硬罩幕,並例如藉由刻蝕(etching)移除晶種層未被導電柱150所覆蓋的部分直至暴露出後鈍化層140為止。
在某些實施例中,導電柱150為電鍍形成的銅柱(plated copper pillars)。
參照圖3,在形成導電柱150之後,在後鈍化層140上形成保護層160,以覆蓋導電柱150。在某些實施例中,保護層160可為具有足以包覆及保護導電柱150的厚度的聚合物層。例如,保護層160可為聚苯並惡唑(PBO)層、聚醯亞胺(PI)層或其他適合的聚合物。在某些替代實施例中,保護層160可由無機材料製成。
參照圖4,在形成保護層160之後,對晶圓100的背面進行背面研磨(back side grinding)製程。在背面研磨製程期間,研磨半導體基底110以形成包括薄化半導體基底110’的薄化晶圓100’。
參照圖5,在進行背面研磨製程之後,對薄化晶圓100’進行晶圓切割製程,使得薄化晶圓100’中的積體電路200彼此單體化。經單體化的各個積體電路200包括半導體基底110a、形成在半導體基底110a上的導電墊120、鈍化層130a、後鈍化層140a、導電柱150及保護層160a。如圖4及圖5中所示,半導體基底110a、鈍化層130a、後鈍化層140a及保護層160a的材料及特性與前述的半導體基底110、鈍化層130、後鈍化層140及保護層160的材料及特性相同。因此,省略了對半導體基底110a、鈍化層130a、後鈍化層140a及保護層160a的詳細說明。
如圖4及圖5中所示,在背面研磨製程及晶圓切割製程期間,保護層160及160a可完善地保護積體電路200的導電柱150。另外,保護層160及160a可保護積體電路200的導電柱150不被積體電路200的拾取及放置(pick-up and placing)製程、模塑(molding)製程等後續進行的製程所損壞。
參照圖6,在積體電路200從薄化晶圓100’(在圖4中示出)被單體化之後,提供已形成有剝離(de-bonding)層DB及介電層DI於其上的載板C,其中剝離層DB位於載板C與介電層DI之間。在某些實施例中,例如,載板C是玻璃基底,剝離層DB是形成在玻璃基底上的光-熱轉換(light-to-heat conversion,LTHC)釋放層,且介電層DI是形成在剝離層DB上的聚苯並惡唑(PBO)層。
在提供已形成有剝離層DB及介電層DI於其上的載板C之後,在介電層DI上形成多個導電通孔TV。在某些實施例中,導電通孔TV是藉由光阻塗佈(photoresist coating)、微影、電鍍及光阻剝除(photoresist stripping)製程所形成。例如,導電通孔TV包括銅柱(copper post)或其他適合的金屬柱。
如圖6中所示,在某些實施例中,可將包括導電墊120、導電柱150、以及形成在其上的保護層160a的其中一個積體電路200拾取且放置在介電層DI上。將積體電路200藉由晶粒貼合膜(die attach film,DAF)、黏著膏(adhesion paste)等貼合或黏著在介電層DI上。在某些替代實施例中,可將多於一個積體電路200拾取且放置在介電層DI上,其中放置在介電層DI上的積體電路200可排列成陣列。當放置在介電層DI上的積體電路200排列成陣列時,可將導電通孔TV分成多個群組。積體電路200的數目可對應於導電通孔TV的群組的數目。
如圖6中所示,保護層160a的頂表面可低於導電通孔TV的頂表面,且保護層160a的頂表面可高於導電柱150的頂表面。然而,本發明並不限於此。在某些替代實施例中,保護層160a的頂表面可與導電通孔TV的頂表面實質上對齊,且保護層160a的頂表面可高於導電柱150的頂表面。
如圖6中所示,可在形成導電通孔TV之後才將積體電路200拾取且放置在介電層DI上。然而,本發明並不限於此。在某些替代實施例中,可在形成導電通孔TV之前便將積體電路200拾取且放置在介電層DI上。
參照圖7,在介電層DI上形成絕緣材料210以覆蓋積體電路200及導電通孔TV。在某些實施例中,絕緣材料210是藉由模塑製程所形成的模塑化合物。積體電路200的導電柱150及保護層160a被絕緣材料210所覆蓋。換句話說,積體電路200的導電柱150及保護層160a未被絕緣材料210顯露出且被絕緣材料210完善地保護。在某些實施例中,絕緣材料210包括環氧樹脂(epoxy)或其他適合的介電材料。
參照圖8,接著,研磨絕緣材料210直至暴露出導電柱150的頂表面、導電通孔TV的頂表面及保護層160a的頂表面為止。在某些實施例中,藉由機械研磨製程及/或化學機械研磨(chemical mechanical polishing,CMP)製程來研磨絕緣材料210。在研磨絕緣材料210之後,在介電層DI上形成絕緣包封體210’。在絕緣材料210的研磨製程期間,保護層160a的部分會被研磨以形成保護層160a’。在某些實施例中,在絕緣材料210及保護層160a的研磨製程期間,導電通孔TV的部分及導電柱150的部分也會被研磨。
如圖8中所示,絕緣包封體210’包覆積體電路200的側壁,且絕緣包封體210’被導電通孔TV穿透。換句話說,積體電路200及導電通孔TV嵌於絕緣包封體210’中。應注意,導電通孔TV的頂表面、絕緣包封體210’的頂表面及導電柱150的頂表面與保護層160a’的頂表面實質上共平面。
參照圖9,在形成絕緣包封體210’及保護層160a’之後,在導電通孔TV的頂表面、絕緣包封體210’的頂表面、導電柱150的頂表面及保護層160a’的頂表面上形成與積體電路200的導電柱150電連接的重佈線路結構220。所形成的重佈線路結構220與位於其下的一個或多個連接件電連接。此處,前述連接件可為積體電路200的導電柱150及/或嵌於絕緣包封體210’中的導電通孔TV。結合圖9詳細闡述重佈線路結構220。
參照圖9,重佈線路結構220包括交替堆疊的多個內層介電層(inter-dielectric layer)222及多個重佈線導電層224,且重佈線導電層224電連接至積體電路200的導電柱150及嵌於絕緣包封體210’中的導電通孔TV。在某些實施例中,導電柱150的頂表面及導電通孔TV的頂表面與重佈線路結構220接觸。導電柱150的頂表面及導電通孔TV的頂表面被最底層的內層介電層222局部地覆蓋。此外,最頂層的重佈線導電層224包括多個導電圖案P(會是於圖10A與圖10B)。
如圖10中所示,在形成重佈線路結構220之後,接著在重佈線路結構220的最頂層的重佈線導電層224上形成多個墊230。墊230包括用於球安裝(ball mount)的多個球下金屬(under-ball metallurgy,UBM)圖案230a及用於安裝被動元件的多個連接墊230b。墊230電連接至重佈線路結構220的最頂層的重佈線導電層224。換句話說,墊230藉由重佈線路結構220電連接至積體電路200的導電柱150及導電通孔TV。應注意,球下金屬圖案230a及連接墊230b的數目在本發明中並無限制。
參照圖10、圖10A及圖10B,在某一實施例中,球下金屬圖案230a下方可配置導電圖案P,並且使導電圖案P能夠電連接至球下金屬圖案230a。各個導電圖案P可包括第一導電墊CP1及連接至第一導電墊CP1的緩衝延伸部BE。第一導電墊CP1包括圓形墊部P1及連接至圓形墊部P1的第一收斂部C1。第一收斂部C1具有一對不平行的第一邊緣E1,不平行的第一邊緣E1界定第一錐度角q1,且不平行的第一邊緣E1是藉由圓形墊部P1的一對不平行的第一切線TL1界定。緩衝延伸部BE連接至第一導電墊CP1的第一收斂部C1。緩衝延伸部BE至少包括具有一對不平行的第二邊緣E2的第二收斂部P2,不平行的第二邊緣E2界定第二錐度角q2。如圖10A及圖10B中所示,圓形墊部P1例如位於球下金屬圖案230a下方且電連接至球下金屬圖案230a。
在某些實施例中,第一錐度角q1大於第二錐度角q2,且第一錐度角q1與第二錐度角q2之差為約10度至約30度。在某些替代實施例中,第一錐度角q1實質上等於第二錐度角q2。
緩衝延伸部BE可進一步包括位於不平行的第一邊緣E1與不平行的第二邊緣E2之間的一對過渡邊緣TE。如圖10A中所示,過渡邊緣TE實質上為線性邊緣,且線性邊緣相互平行。當過渡邊緣TE實質上為線性邊緣時,緩衝延伸部BE沿延伸方向DR延伸,且緩衝延伸部BE的最大寬度實質上等於不平行的第一邊緣E1之間的最小距離或不平行的第二邊緣E2之間的最大距離。此外,由緩衝延伸部BE的過渡邊緣TE與第二邊緣E2界定的夾角q3可例如介於約120度至約175度範圍內。
在某些替代實施例中,如圖10B中所示,過渡邊緣TE可為彎曲邊緣。當過渡邊緣TE為彎曲邊緣時,緩衝延伸部BE沿延伸方向DR延伸,且緩衝延伸部BE的最小寬度實質上等於不平行的第一邊緣E1之間的最小距離或不平行的第二邊緣E2之間的最大距離。
在某些其他實施例中,可省略緩衝延伸部BE的過渡邊緣TE。
在某些實施例中,導電圖案P可進一步包括經由緩衝延伸部BE連接至第一導電墊CP1的佈線RL。如圖10A及圖10B中所示,佈線RL連接至緩衝延伸部BE的第二收斂部P2。緩衝延伸部BE位於佈線RL與第一導電墊CP1之間,且佈線RL具有實質上恒定的線寬度(line width)。緩衝延伸部BE可充當第一導電墊CP1與佈線RL之間的過渡結構,以使應力最小化。
在某些實施例中,不平行的第一邊緣E1之間的最小距離對不平行的第二邊緣E2之間的最小距離(即,佈線RL的線寬度W)的比率可介於約1.1至約4範圍內。
在某些實施例中,佈線RL具有實質上恒定的線寬度W,且佈線RL具有至少一個彎折部CV。佈線RL的線寬度W可介於約1微米至約25微米範圍內。如圖10A中所示,為說明起見,僅繪示出佈線RL的兩個彎折部CV。然而,本發明並不限於此。在某些實施例中,彎折部CP(右側的一個)與緩衝延伸部BE和佈線RL的連接點之間的距離可介於約10微米至約20微米範圍內。
如圖10A及圖10B中所示,在某些實施例中,導電圖案P可進一步包括第二導電墊CP2。第二導電墊CP2藉由佈線RL及緩衝延伸部BE連接至第一導電墊CP1。第二導電墊CP2電連接至位於其下方的重佈線導電層224。在某些實施例中,第一導電墊CP1的面積大於第二導電墊CP2的面積。在某些替代實施例中,第一導電墊CP1的面積實質上等於第二導電墊CP2的面積。
參照圖11,在形成球下金屬圖案230a及連接墊230b之後,在球下金屬圖案230a上放置多個導電球240,且在連接墊230b上安裝多個被動元件250。在某些實施例中,可藉由植球(ball placement)製程在球下金屬圖案230a上放置導電球240,且可藉由焊接(soldering)或回焊(reflow)製程在連接墊230b上安裝被動元件250。在某些實施例中,例如,導電球240的高度大於被動元件250的高度。
參照圖11及圖12,在墊230上安裝導電球240及被動元件250之後,從剝離層DB剝離在絕緣包封體210’的底表面上形成的介電層DI,進而使得介電層DI從載板C上分離。在某些實施例中,可藉由UV雷射照射剝離層DB(例如,光-熱轉換釋放層),進而使得介電層DI從載板C脫落(peel)。
如圖12中所示,接著將介電層DI圖案化,進而形成多個接觸開口O以暴露出導電通孔TV的底表面。接觸開口O的數目及位置對應於導電通孔TV的數目。在某些實施例中,藉由雷射鑽孔(laser drilling)製程或其他適合的圖案化製程形成介電層DI的接觸開口O。
參照圖13,在介電層DI中形成接觸開口O之後,在導電通孔TV的被接觸開口O暴露出的底表面上放置多個導電球260。對導電球260進行回焊以使導電球260與導電通孔TV的底表面接合。如圖13中所示,在形成導電球240及導電球260之後,具有雙側端子設計(即,導電球240及260)的積體電路200的集成扇出型封裝件製作完成。
參照圖14,接著設置另一封裝件300。在某些實施例中,封裝件300例如為記憶體裝置或其他適合的半導體裝置。藉由導電球260將封裝件300堆疊在圖12中所示的集成扇出型封裝件之上並電連接至集成扇出型封裝件,進而完成疊層封裝(POP)結構的製作。
在上述實施例中,連接部P4可充當過渡部以使第一導電墊P1與佈線P3之間的應力最小化。因此,可增強導電圖案P的可靠性。
根據本發明的某些實施例,提供一種導電圖案,所述導電圖案包括:導電墊,包括圓形墊部及連接至所述圓形墊部的第一收斂部,所述第一收斂部具有一對不平行的第一邊緣,所述一對不平行的第一邊緣界定第一錐度角,且所述一對不平行的第一邊緣由所述圓形墊部的一對不平行的第一切線界定;以及緩衝延伸部,連接至所述導電墊的所述第一收斂部,所述緩衝延伸部至少包括具有一對不平行的第二邊緣的第二收斂部,所述一對不平行的第二邊緣界定第二錐度角,所述第一錐度角大於或等於所述第二錐度角。
所述的導電圖案進一步包括連接至所述第二收斂部的佈線,其中所述緩衝延伸部位於所述佈線與所述導電墊之間,且所述佈線具有恒定的線寬度。
在所述的導電圖案中,所述佈線具有至少一個彎折部。
在所述的導電圖案中,所述緩衝延伸部進一步包括位於所述一對不平行的第一邊緣與所述一對不平行的第二邊緣之間的一對過渡邊緣。
在所述的導電圖案中,所述過渡邊緣是線性邊緣且所述線性邊緣相互平行。
在所述的導電圖案中,所述緩衝延伸部沿延伸方向延伸,所述緩衝延伸部的最大寬度等於所述一對不平行的第一邊緣之間的最小距離或所述一對不平行的第二邊緣之間的最大距離。
在所述的導電圖案中,所述過渡邊緣是彎曲邊緣。
在所述的導電圖案中,所述緩衝延伸部沿延伸方向延伸,所述緩衝延伸部的最小寬度等於所述一對不平行的第一邊緣之間的最小距離或所述一對不平行的第二邊緣之間的最大距離。
根據本發明的替代實施例,提供另一種導電圖案,所述導電圖案包括:第一導電墊,包括圓形墊部及連接至所述圓形墊部的第一收斂部,所述第一收斂部具有一對不平行的第一邊緣,所述一對不平行的第一邊緣界定第一錐度角,且所述一對不平行的第一邊緣由所述圓形墊部的一對不平行的第一切線界定;緩衝延伸部,連接至所述第一導電墊的所述第一收斂部,所述緩衝延伸部至少包括具有一對不平行的第二邊緣的第二收斂部,所述一對不平行的第二邊緣界定第二錐度角,所述第一錐度角大於或等於所述第二錐度角;佈線,經由所述緩衝延伸部連接至所述第一導電墊,所述佈線連接至所述第二收斂部;以及第二導電墊,經由所述佈線及所述緩衝延伸部連接至所述第一導電墊。
在所述的導電圖案中,所述佈線具有恒定的線寬度。
在所述的導電圖案中,所述佈線具有至少一個彎折部。
在所述的導電圖案中,所述第一導電墊的面積大於或等於所述第二導電墊的面積。
在所述的導電圖案中,所述緩衝延伸部進一步包括位於所述一對不平行的第一邊緣與所述一對不平行的第二邊緣之間的一對過渡邊緣。
在所述的導電圖案中,所述過渡邊緣是線性邊緣且所述線性邊緣相互平行。
在所述的導電圖案中,所述緩衝延伸部沿延伸方向延伸,所述緩衝延伸部的最大寬度等於所述一對不平行的第一邊緣之間的最小距離或所述一對不平行的第二邊緣之間的最大距離。
在所述的導電圖案中,所述過渡邊緣是彎曲邊緣。
在所述的導電圖案中,所述緩衝延伸部沿延伸方向延伸,所述緩衝延伸部的最小寬度等於所述一對不平行的第一邊緣之間的最小距離或所述一對不平行的第二邊緣之間的最大距離。
根據本發明的又一些替代實施例,提供一種集成扇出型封裝件,所述集成扇出型封裝件包括:積體電路;絕緣包封體,包覆所述積體電路;重佈線路結構,位於所述絕緣包封體及所述積體電路上,所述重佈線路結構包括多個內層介電層及多個重佈線導電層,所述內層介電層與所述重佈線導電層交替堆疊,其中所述最頂層的重佈線導電層包括至少一個導電圖案,且所述至少一個導電圖案包括:導電墊,包括圓形墊部及連接至所述圓形墊部的第一收斂部,所述第一收斂部具有一對不平行的第一邊緣,所述一對不平行的第一邊緣界定第一錐度角,且所述一對不平行的第一邊緣由所述圓形墊部的一對不平行的第一切線界定;以及緩衝延伸部,連接至所述導電墊的所述第一收斂部,所述緩衝延伸部至少包括具有一對不平行的第二邊緣的第二收斂部,所述一對不平行的第二邊緣界定第二錐度角,所述第一錐度角大於或等於所述第二錐度角。
在所述集成扇出型封裝件中,所述緩衝延伸部進一步包括位於所述一對不平行的第一邊緣與所述一對不平行的第二邊緣之間的一對過渡邊緣,所述過渡邊緣是線性邊緣,且所述線性邊緣相互平行。
在所述集成扇出型封裝件中,所述緩衝延伸部進一步包括位於所述一對不平行的第一邊緣與所述一對不平行的第二邊緣之間的一對過渡邊緣,且所述過渡邊緣是彎曲邊緣。
以上概述了多個實施例的特徵,使本領域具有通常知識者可更佳瞭解本揭露的態樣。本領域具有通常知識者應理解,其可輕易地使用本揭露作為設計或修改其他製程與結構的依據,以實行本文所介紹的實施例的相同目的及/或達到相同優點。本領域具有通常知識者還應理解,這種等效的配置並不悖離本揭露的精神與範疇,且本領域具有通常知識者在不悖離本揭露的精神與範疇的情況下可對本文做出各種改變、置換以及變更。
100‧‧‧晶圓100’‧‧‧薄化晶圓110、110’、110a‧‧‧半導體基底120‧‧‧導電墊130、130a‧‧‧鈍化層132、142‧‧‧接觸開口140、140a‧‧‧後鈍化層150‧‧‧導電柱160、160a、160a’‧‧‧保護層200‧‧‧積體電路210‧‧‧絕緣材料210’‧‧‧絕緣包封體220‧‧‧重佈線路結構222‧‧‧內層介電層224‧‧‧重佈線導電層230‧‧‧墊230a‧‧‧球下金屬圖案230b‧‧‧連接墊240、260‧‧‧導電球250‧‧‧被動元件300‧‧‧封裝件BE‧‧‧緩衝延伸部C‧‧‧載板C1‧‧‧第一收斂部CP1‧‧‧第一導電墊CP2‧‧‧第二導電墊CV‧‧‧彎折部DB‧‧‧剝離層DI‧‧‧介電層DR‧‧‧延伸方向E1‧‧‧第一邊緣E2‧‧‧第二邊緣O‧‧‧接觸開口P‧‧‧導電圖案P1‧‧‧圓形墊部P2‧‧‧第二收斂部RL‧‧‧佈線TE‧‧‧過渡邊緣TL1‧‧‧第一切線TV‧‧‧導電通孔W‧‧‧線寬度q1‧‧‧第一錐度角q2‧‧‧第二錐度角q3‧‧‧夾角
圖1至圖13說明製作根據某些實施例的集成扇出型封裝件的製造流程。 圖14是說明根據某些實施例的疊層封裝(package-on-package,POP)結構的剖視圖。
230a‧‧‧球下金屬圖案
BE‧‧‧緩衝延伸部
C1‧‧‧第一收斂部
CP1‧‧‧第一導電墊
CP2‧‧‧第二導電墊
CV‧‧‧彎折部
DR‧‧‧延伸方向
E1‧‧‧第一邊緣
E2‧‧‧第二邊緣
P‧‧‧導電圖案
P1‧‧‧圓形墊部
P2‧‧‧第二收斂部
RL‧‧‧佈線
TE‧‧‧過渡邊緣
TL1‧‧‧第一切線
W‧‧‧線寬度
θ1‧‧‧第一錐度角
θ2‧‧‧第二錐度角
θ3‧‧‧夾角
Claims (10)
- 一種導電圖案,包括:導電墊,包括圓形墊部及連接至所述圓形墊部的第一收斂部,所述第一收斂部具有一對不平行的第一邊緣,所述一對不平行的第一邊緣界定第一錐度角,且所述一對不平行的第一邊緣由所述圓形墊部的一對不平行的第一切線界定;以及緩衝延伸部,連接至所述導電墊的所述第一收斂部,所述緩衝延伸部包括具有一對不平行的第二邊緣以及位於所述一對不平行的第一邊緣與所述一對不平行的第二邊緣之間的一對過渡邊緣的第二收斂部,其中所述一對不平行的第二邊緣界定第二錐度角,且所述第一錐度角大於或等於所述第二錐度角,所述過渡邊緣是彎曲邊緣,且所述彎曲邊緣是所述緩衝延伸部的凹狀邊緣。
- 如申請專利範圍第1項所述之導電圖案,進一步包括連接至所述第二收斂部的佈線,其中所述緩衝延伸部位於所述佈線與所述導電墊之間,且所述佈線具有恒定的線寬度。
- 如申請專利範圍第1項所述之導電圖案,其中所述緩衝延伸部沿延伸方向延伸,所述緩衝延伸部的最小寬度等於所述一對不平行的第一邊緣之間的最小距離或所述一對不平行的第二邊緣之間的最大距離。
- 一種導電圖案,包括:第一導電墊,包括圓形墊部及連接至所述圓形墊部的第一收 斂部,所述第一收斂部具有一對不平行的第一邊緣,所述一對不平行的第一邊緣界定第一錐度角,且所述一對不平行的第一邊緣由所述圓形墊部的一對不平行的切線界定;緩衝延伸部,連接至所述第一導電墊的所述第一收斂部,所述緩衝延伸部至少包括具有一對不平行的第二邊緣的第二收斂部,所述一對不平行的第二邊緣界定第二錐度角,所述第一錐度角大於或等於所述第二錐度角;佈線,經由所述緩衝延伸部連接至所述第一導電墊,所述佈線連接至所述第二收斂部;以及第二導電墊,經由所述佈線及所述緩衝延伸部連接至所述第一導電墊,其中所述第一導電墊與所述第二導電墊之間的最小距離小於沿著所述緩衝延伸部及所述佈線從所述第一導電墊至所述第二導電墊的路徑長度。
- 如申請專利範圍第4項所述之導電圖案,其中所述緩衝延伸部進一步包括位於所述一對不平行的第一邊緣與所述一對不平行的第二邊緣之間的一對過渡邊緣。
- 如申請專利範圍第5項所述之導電圖案,其中所述過渡邊緣是線性邊緣且所述線性邊緣相互平行。
- 如申請專利範圍第5項所述之導電圖案,其中所述過渡邊緣是彎曲邊緣。
- 一種集成扇出型封裝件,包括: 積體電路;絕緣包封體,包覆所述積體電路;重佈線路結構,位於所述絕緣包封體及所述積體電路上,所述重佈線路結構包括多個內層介電層及多個重佈線導電層,所述內層介電層與所述重佈線導電層交替堆疊,其中所述最頂層的重佈線導電層包括至少一個導電圖案,且所述至少一個導電圖案包括:導電墊,包括圓形墊部及連接至所述圓形墊部的第一收斂部,所述第一收斂部具有一對不平行的第一邊緣,所述一對不平行的第一邊緣界定第一錐度角,且所述一對不平行的第一邊緣由所述圓形墊部的一對不平行的切線界定;以及緩衝延伸部,連接至所述導電墊的所述第一收斂部,所述緩衝延伸部包括具有一對不平行的第二邊緣以及位於所述一對不平行的第一邊緣與所述一對不平行的第二邊緣之間的一對過渡邊緣的第二收斂部,所述一對不平行的第二邊緣界定第二錐度角,且所述第一錐度角大於或等於所述第二錐度角,其中所述過渡邊緣是彎曲邊緣,且所述彎曲邊緣是所述緩衝延伸部的凹狀邊緣。
- 如申請專利範圍第8項所述之集成扇出型封裝件,其中所述至少一個導電圖案包括進一步包括連接至所述第二收斂部的佈線,其中所述緩衝延伸部位於所述佈線與所述導電墊之間,且所述佈線具有恒定的線寬度。
- 如申請專利範圍第8項所述之集成扇出型封裝件,其中所述緩衝延伸部沿延伸方向延伸,所述緩衝延伸部的最小寬度等於所述一對不平行的第一邊緣之間的最小距離或所述一對不平行的第二邊緣之間的最大距離。
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