TWI704384B - 晶圓級接合主動式光子中介層及其製造方法 - Google Patents

晶圓級接合主動式光子中介層及其製造方法 Download PDF

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TWI704384B
TWI704384B TW107107158A TW107107158A TWI704384B TW I704384 B TWI704384 B TW I704384B TW 107107158 A TW107107158 A TW 107107158A TW 107107158 A TW107107158 A TW 107107158A TW I704384 B TWI704384 B TW I704384B
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dielectric stack
photonic
channel
substrate
interposer
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TW107107158A
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TW201910832A (zh
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道格拉斯 庫柏
道格拉斯 拉土利普
杰拉爾德 利克
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紐約州立大學研究基金會
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    • H01L31/02002Arrangements for conducting electric current to or from the device in operations
    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
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    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
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    • G02B6/12Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/12002Three-dimensional structures
    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
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    • G02B6/13Integrated optical circuits characterised by the manufacturing method
    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
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    • G02B6/13Integrated optical circuits characterised by the manufacturing method
    • G02B6/131Integrated optical circuits characterised by the manufacturing method by using epitaxial growth
    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24Coupling light guides
    • G02B6/42Coupling light guides with opto-electronic elements
    • G02B6/4201Packages, e.g. shape, construction, internal or external details
    • G02B6/4219Mechanical fixtures for holding or positioning the elements relative to each other in the couplings; Alignment methods for the elements, e.g. measuring or observing methods especially used therefor
    • G02B6/4228Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements
    • G02B6/4232Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements using the surface tension of fluid solder to align the elements, e.g. solder bump techniques
    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24Coupling light guides
    • G02B6/42Coupling light guides with opto-electronic elements
    • G02B6/43Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
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    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
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    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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    • H01L21/4814Conductive parts
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    • H01L21/486Via connections through the substrate with or without pins
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    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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    • H01L25/167Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
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    • H01L27/1259Multistep manufacturing methods
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    • H01L31/02016Circuit arrangements of general character for the devices
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    • GPHYSICS
    • G02OPTICS
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    • G02B2006/12035Materials
    • G02B2006/12038Glass (SiO2 based materials)
    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS OR APPARATUS
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    • G02B2006/12035Materials
    • G02B2006/12061Silicon
    • GPHYSICS
    • G02OPTICS
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    • G02B6/00Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
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    • G02B2006/12083Constructional arrangements
    • G02B2006/121Channel; buried or the like
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    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS OR APPARATUS
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    • G02B2006/12133Functions
    • G02B2006/12138Sensor
    • GPHYSICS
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    • G02B6/10Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
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    • G02B2006/12133Functions
    • G02B2006/12147Coupler
    • GPHYSICS
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    • G02B6/10Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
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    • G02B2006/12166Manufacturing methods
    • G02B2006/12176Etching
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    • G02OPTICS
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    • G02B6/10Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B2006/12166Manufacturing methods
    • G02B2006/12178Epitaxial growth
    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS OR APPARATUS
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    • G02B6/12004Combinations of two or more optical elements
    • GPHYSICS
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    • G02B6/122Basic optical elements, e.g. light-guiding paths
    • GPHYSICS
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    • G02B6/122Basic optical elements, e.g. light-guiding paths
    • G02B6/1223Basic optical elements, e.g. light-guiding paths high refractive index type, i.e. high-contrast waveguides
    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS OR APPARATUS
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    • G02B6/13Integrated optical circuits characterised by the manufacturing method
    • G02B6/132Integrated optical circuits characterised by the manufacturing method by deposition of thin films
    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS OR APPARATUS
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    • G02B6/134Integrated optical circuits characterised by the manufacturing method by substitution by dopant atoms
    • G02B6/1347Integrated optical circuits characterised by the manufacturing method by substitution by dopant atoms using ion implantation
    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS OR APPARATUS
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    • G02B6/136Integrated optical circuits characterised by the manufacturing method by etching
    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24Coupling light guides
    • G02B6/42Coupling light guides with opto-electronic elements
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    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
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    • H01L2224/03001Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
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Abstract

本說明書中說明一種方法,包含:在具有一第一基板之一第一晶圓之上建立一中介層基礎結構,其中該中介層基礎結構的建立係包括製造為延伸通過該第一基板的複數個穿透通道及在該第一基板之上所形成之一中介層基礎介電堆疊內製造一個或多個金屬化層;在具有一第二基板之一第二晶圓之上建立一光子結構,其中該光子結構的建立係包括在該第二基板之上所形成之一光子裝置介電堆疊內製造一個或多個光子裝置;以及將該光子結構接合至該中介層基礎結構以界定具有該中介層基礎結構的一中介層及在該光子裝置介電堆疊內所製造的一個或多個光子裝置。

Description

晶圓級接合主動式光子中介層及其製造方法
[相關申請案的交互參照]本申請案請求於2017年4月27日提交的發明名稱為「晶圓級接合主動式光子中介層」的美國臨時申請案第62/490,665號的優先權,該申請案的全部內容通過引用併入本說明書中。本申請案亦請求於2018年2月8日提交的發明名稱為「晶圓級接合主動式光子中介層」的美國臨時申請案第15/891,847號的優先權,該申請案的全部內容通過引用併入本說明書中。此外,本申請案亦請求於2018年2月9日提交的發明名稱為「晶圓級接合主動式光子中介層」的國際申請案第PCT/US18/17558號的優先權,該申請案的全部內容通過引用併入本說明書中。前述之全部內容通過引用併入本說明書中的於2018年2月8日提交的發明名稱為「晶圓級接合主動式光子中介層」的美國非臨時申請案第15/891,847號請求前述之於2017年4月27日提交的發明名稱為「晶圓級接合主動式光子中介層」的美國臨時申請案第62/490,665號的優先權,該申請案的全部內容通過引用併入本說明書中。前述之全部內容通過引用併入本說明書中的於2018年2月9日提交的發明名稱為「晶圓級接合主動式光子中介層」的國際申請案第PCT/US18/17558號請求於2018年2月8日提交的發明名稱為「晶圓級接合主動式光子中介層」的美國非臨時申請案第15/891,847號的優先權,該申請案的全部內容通過引用併入本說明書中,並請求前述之於2017年4月27日提交的發明名稱為「晶圓級接合主動式光子中介層」的美國臨時申請案第62/490,665號的優先權,該申請案的全部內容通過引用併入本說明書中。
[政府權利聲明]本發明是在美國國防部(DOD)的政府資助下完成的,授權合同號為FA8650-15-2-5220。政府可能在本發明中享有某些權利。
本發明一般而言關於光子學,且尤其是關於光子結構及其製造方法。
市面上銷售的光子積體元件係製造於晶圓上,如塊體矽或絕緣層上覆矽晶圓。市面上銷售的預製光子積體電路晶片可包括用於在預製光子積體電路晶片之不同區域之間傳輸光學信號的多數個波導。市面上銷售的波導係呈矩形或脊狀幾何並以矽(單晶或多晶)或氮化矽製造。市面上銷售的光子積體電路晶片係可用於具有安置在印刷電路板之上的光子積體電路晶片的系統上。
透過提供一種光子結構,在一個方面,克服習知技術的缺點,並提供額外的好處。
在本說明書中說明一種方法,包含:在一第一晶圓之上建立一中介層基礎結構,其中該中介層基礎結構的建立係包括製造為延伸通過該第一基板的複數個穿透通道及在一中介層基礎介電堆疊內製造一個或多個金屬化層;在一第二晶圓之上建立一光子結構,其中該光子結構的建立係包括在一光子裝置介電堆疊內製造一個或多個光子裝置;以及將該光子結構接合至該中介層基礎結構以界定具有該中介層基礎結構的一中介層及一個或多個光子裝置。在本說明書中說明一種光電系統,包含:一基板;一中介層介電堆疊,形成於該基板上,該中介層介電堆疊包括一中介層基礎介電堆疊、及一光子裝置介電堆疊、及將該光子裝置介電堆疊整體接合至該中介層基礎介電堆疊的一接合層。
更多的特徵與好處係透過本發明之技術而實現。
10:光電系統
100:基板
102:介電層
104:介電層
106:介電層
108:介電層
110:介電層
112:介電層
116:穿透通道
118:金屬化層
120:金屬化層
122:通道
126:介電堆疊
140:金屬化層
200:基板
202:介電層
204:介電層
206:介電堆疊
210:波導
212:波導
214:波導
220:金屬化層
222:金屬化層
224:通道
226:通道
230:構造
238:構造
240:光檢測器
300:中介層
302:介電層
304:介電層
306:接合層
320:介電堆疊
324:介電層
326:介電層
332:通道
334:金屬化層
336:構造
400:晶片
410:黏性層
420:晶圓
502:介電層
504:介電層
508:重新分布層
510:凸塊下金屬化構造
512:軟焊凸塊
本發明之一個或多個方面係分別包含並清楚地指出於本說明書之結論處的申請專利範圍中的專利請求項以作為範例。結合附圖,通過以下詳細說明,本發明的上述及其他目的、特徵及好處將會變得更加明白,其中:圖1係具有包括其內有製造及界定一個或多個光子裝置之一中介層介電堆疊之一中介層的光電系統的側剖面圖;圖2說明在具有晶圓基板之塊體晶圓之上建立一中介層基礎之後的處於製造步驟之中間階段的光電系統;圖3係說明在建立具有內部製造有並界定一個或多個光子裝置的光子結構介電堆疊之光子結構之後的處於一部分階段的光電系統橫斷面側視圖,且其中該製造步驟係使用一絕緣層上覆矽(SOI)晶圓來執行;圖4係說明顯示圖2之中介層基礎結構係與圖3之光子結構對齊的光電系統製造步驟的橫斷面側視圖;圖5係說明圖3中顯示之光子結構係接合至圖2之中介層基礎結構的橫斷面側視圖;圖6係在從光子結構移除基板之後的如圖5中顯示的處於製造步驟之一部分階段的光電系統的橫斷面側視圖;圖7係在進一步圖樣成形以界定連接於多數個接合裝置層之間的連接層間及層內通道及(多數個)金屬化層與提供電連接至具有中介層結構之所製造中介層背側之後的處於製造步驟之一中間階段的如圖6中顯示的光電系統的橫斷面側視圖; 圖8係在進一步圖樣成形以界定凸塊下金屬化構造之後的處於製造步驟之中間階段的如圖7中顯示的光電系統的橫斷面側視圖;圖9說明在將積體電路晶片金屬軟焊結合至如圖8中顯示所製造之凸塊下金屬化構造之後的處於製造步驟之中間階段的如圖8中顯示的光電系統的橫斷面側視圖;圖10係說明在使用黏合劑、環氧、或其他永久性有機聚合物將操作晶圓結合至如圖9中顯示的結構之後的處於製造步驟之中間階段的如圖9中顯示的光電系統的橫斷面側視圖;圖11係說明在移除界定中介層基礎之基板的材料之後的如圖10中顯示的光電系統的橫斷面側視圖;圖12係在沉積介電層之後的如圖11中顯示的光電系統的橫斷面側視圖;圖13係在圖樣成形以界定中介層背側重新分布層之後的處於製造步驟之中間階段的如圖12中顯示的光電系統的橫斷面側視圖;圖14係說明在沉積可為介電鈍化層之介電層之後的處於製造步驟之中間階段的如圖13中顯示的光電系統的橫斷面側視圖;以及圖15係在進一步圖樣成形以界定凸塊下金屬化構造與在該些凸塊下金屬化構造內製造軟焊凸塊之後的如圖14中顯示的光電系統的橫斷面側視圖。
以下將參考附圖中所說明之非限制範例更全面地解說本發明之多數個方面及其之一些特徵、好處及細節。對習知材料、製造工具、處理技術等的說明均予以省略以免本發明因過度詳述,反而使重點無法凸顯。然而,應 該理解的是,所有的細節說明及提到的特殊範例均僅為了說明之用途而給出,並非為了限制之用途。對於此項技術具有通常知識者由本發明將可明白,在所含發明概念的精神及/或範圍內可有各種取代、修改、添加、及/或配置。
在圖1中,顯示具有可包括一個或多個可將光子信號轉換成電子信號之主動光子裝置之主動光子中介層300的光電系統10。光子中介層300可包括由基板100所界定的中介層基礎。
中介層300可包括具有基板100及中介層基礎介電堆疊126之介電層基礎。在中介層基礎介電堆疊126內可製造有一個或多個金屬化層,例如金屬化層118、金屬化層120以及垂直延伸的通道122。中介層基礎可支持能夠延伸通過基板100之厚度的穿透通道116。在一項具體實施例中,穿透通道116可藉由完全(整個)延伸通過基板100之厚度而延伸通過基板100之厚度。在一項具體實施例中,穿透通道116可藉由部分延伸通過基板100之厚度而延伸通過基板100之厚度。基板100可由例如矽、元素矽、藍寶石、或玻璃形成。在基板100之上可製造有用於將電子信號散布至穿透通道116及由穿透通道116散布出電子信號的背側重新分布層508。
中介層300亦可包括光子裝置介電堆疊206,其中可製造有並界定一個或多個光子裝置,例如一個或多個波導210、一個或多個波導214、及一個或多個光檢測器240。光子裝置介電堆疊206可支持一個或多個可延伸通過光子裝置介電堆疊206之厚度的穿透通道332。在一項具體實施例中,穿透通道332可藉由完全(整個)延伸通過光子裝置介電堆疊206而延伸通過光子裝置介電堆疊206。在一項具體實施例中,穿透通道332可藉由延伸通過一個或多個光子裝置之底部及頂部高度而延伸通過光子裝置介電堆疊206。在一項具體實施例中,穿透通道332可藉由延伸通過複數個光子裝置之底部及頂部高度而延伸通過光子裝置介電堆疊206。在一項具體實施例中,穿透通道332可藉由部分延伸通過光 子裝置介電堆疊206而延伸通過光子裝置介電堆疊206。在光子裝置介電堆疊206內可製造有一個或多個金屬化層,例如金屬化層220、金屬化層222以及垂直延伸的通道226。如同在本說明書中所說明的,金屬化層水平地界定延伸線路以乘載一個或多個控制、邏輯及/或動力信號。
在一個方面中,延伸通過光子裝置介電堆疊206之穿透通道332之通道可分別關聯於各自的延伸通過基板100之厚度的穿透通道116。有利地,穿透通道332可製成大小顯著小於穿透通道116,因而在光子裝置介電堆疊206中釋放出空間,進而使得在光子裝置介電堆疊206中可製造額外及/或較大的光子裝置。穿透通道116可藉由橋接方式而連接至關聯穿透通道332。中介層300可包括將中介層基礎介電堆疊126接合至光子裝置介電堆疊206的接合層306。支持在基板100之上,中介層300可包括含有中介層基礎介電堆疊126、接合層306、及光子裝置介電堆疊206的中介層介電堆疊320。
如圖1中所顯示的中介層300之特色在於可使背側電連接至前側,例如因為有複數個穿透通道116之穿透通道延伸通過基礎中介層基板100並分別與各自的延伸通過光子裝置介電堆疊206之複數個穿透通道332之穿透通道相關聯。如圖1中所顯示的中介層300之特色在於可連通例如,一個或多個控制、邏輯、及/或動力信號的水平分布的背側及前側線路。中介層300之背側可包括一個或多個重新分布層,例如界定背側線路的重新分布層508。中介層300之前側可包括一個或多個金屬化層,例如界定前側線路的金屬化層334。
光電系統10可包括以襯墊形式顯示於具體實施例中的多數個與延伸通過基板100之垂直延伸穿透通道116電通信的凸塊下金屬化構造510。在凸塊下金屬化構造510之上可形成中介層300之軟焊凸塊512。
圖2說明可包括基板100及中介層基礎介電堆疊126之中介層基礎結構的製造。基板100可支持穿透通道116,且在基板100為矽基板的情況中,穿 透通道116可稱作穿透矽通道(TSV)。在一項具體實施例中,基板100可由塊體矽晶圓提供。關於垂直延伸的穿透通道116之形成,可使基板100經受蝕刻,例如反應離子蝕刻(RIE),然後使產生的溝槽以導電材料進行填充。圖2之結構可經圖樣成形而包括多個介電層,如由基板100所支持的介電層102、104、106、108、110、及112,並界定中介層基礎介電堆疊126。在中介層基礎介電堆疊126內可圖樣成形有多個金屬化層,如金屬化層118及金屬化層120。可在中介層基礎介電堆疊126內製造垂直延伸的穿透通道116以在如在圖1中所說明的在所製造的光子中介層300之前與背側之上的多數個金屬化層之間提供電連接。在一些具體實施例中,不同介電層102、104、106、108、110、及112的材料可以相異。例如,介電層102可用作圖樣成形穿透通道116的硬遮罩並可經選擇而使其作為應遮罩的功能發揮最佳化。如介電層104、108、及112的介電層可分別在各自的金屬化層或其他導電材料構造之上沉積並可經選擇而抑制導電材料遷移。如介電層104及106的剩餘介電層可由與界定中介層基礎介電堆疊126之剩餘介電層之介電材料不同的介電材料形成。在一項具體實施例中,介電層104及106可由原矽酸四乙酯(TEOS)或其他合適的SiOx衍生物形成。
圖3說明具有內部可製造有並界定如波導210之一個或多個波導、波導214之一個或多個波導、或一個或多個光檢測器240的一個或多個光子裝置之光子介電堆疊206之光子結構的製造。如圖3所顯示之光子結構可使用絕緣層上覆矽(SOI)晶圓來製造。此SOI晶圓可預先製造而包括形成於基板上之絕緣層及形成於絕緣層上之薄矽層。圖3說明在圖樣成形之後SOI晶圓之剩餘元件。也就是說,基板200可為SOI晶圓之基板,介電層202可為SOI晶圓之絕緣層,而如圖3所示之波導210可在圖樣成形此層以界定波導210之後由SOI晶圓之矽層之剩餘部分界定。
參考圖3,在介電層204上可形成一個或多個介電層204,在一項具體實施例中介電層204可由SOI晶圓之絕緣層提供以界定光子裝置介電堆疊206。在介電堆疊206中,可圖樣成形有由不同材料形成之波導。例如,波導210可由矽形成,而波導214可由如氮化矽SiN之不同材料形成。一些應用可偏好使用矽波導,而其他應用可偏好氮化矽波導。提供不同材料之波導可強化圖3中所示之結構的效能與靈活性。在介電堆疊206中,可在不同高度形成有圖樣成形波導。例如,可由矽形成之波導210可形成於第一高度,而可由氮化物形成之波導214可如顯示的一般分別形成於第二、第三、及第四高度。
參考在圖3之中間製造階段視圖中顯示之額外特徵,光電系統10可包括與光子裝置介電堆疊206整體地形成的一個或多個光子裝置。在一些具體實施例中,可磊晶成長形成如光檢測器240之光子裝置的例如單晶矽、多晶矽、鍺之材料。本說明書中的具體實施例發現,雖然厚的矽層可能較適合磊晶成長,但產生的光子裝置卻可能在穿透厚的矽層時出現光損失。在一項具體實施例中,為能適合磊晶成長材料的磊晶成長,可在絕緣層上提供具有矽種晶層(矽模板)的結構。種晶層可為結晶種晶層。為能提供具有矽種晶層之結構,可選擇(在塊體矽基板上具有氧化物薄層及在氧化物上具有矽薄層的)絕緣層上覆矽(SOI)晶圓。在使用SOI晶圓以製造中介層300的一項具體實施例中,基板200可由SOI晶圓之塊體矽基板提供。
如圖3中所顯示,在光子裝置介電堆疊206內所製造之一個或多個光子裝置可包括由波導材料層所界定之波導214。在一項具體實施例中,波導214的製造可藉由沉積材料以形成波導材料層,遮罩及蝕刻處理以移除波導材料層之不需要的區域,以及在波導材料層之剩餘部分之上沉積介電層。界定波導214之波導材料層可包括,例如單晶矽、多晶矽、非晶矽、氮化矽、或氮氧化矽。在一項具體實施例中,光子裝置介電堆疊206可製造而在基板200之上的高度並 與基板200保持間隔地包括絕緣層上覆矽介面。舉例來說,例如在由矽形成之基板200之上磊晶成長的在基板200之頂高度之上的厚矽層可經受藉由局部或非局部植入氧(SIMOX)處理而分離以界定薄矽層及在薄矽層之下的埋入氧化層。
如圖3中所示,在光子裝置介電堆疊206內由不同材料製造的波導可用以發揮不同功能。例如,可選擇由矽形成之波導來製造在如光檢測器或調變器之主動裝置中所包括的波導。介電波導(例如,由氮化矽所形成的介電波導)可經調適而可將光學信號傳播至較遠的距離。在強調電流傳導特性與光傳導特性之平衡的應用中,可選擇其他如非晶矽之材料。波導的圖樣成形可包括界定波導之材料的圖樣成形,以及具有與波導之材料的折射率相異之折射率的波導周圍材料的圖樣成形。波導210及波導214之圖樣成形可包括圖樣成形以界定不同的交替幾何構造。
藉由適當的製造方法,由不同波導材料之波導所提供或具有不同波導材料之波導的光子裝置可製造於光子裝置介電堆疊206的任何高度。在一項具體實施例中,可在光子裝置介電堆疊206的基板上位置製造磊晶成長光子裝置,並可在光子裝置介電堆疊206的基板之上的高度形成由沉積材料形成之光子裝置,例如由沉積的氮化矽或氮氧化矽形成之光子裝置。光子裝置介電堆疊206可製造而藉由在不同高度之波導間的漸消耦合在不同高度之間傳導光。
可執行各種處理以修改可製成各種光子裝置之材料層之晶粒結構。在一項具體實施例中,材料層可由多結晶矽(多晶矽)形成。在一項具體實施例中,可執行離子植入以修改材料層之矽晶體結構。透過修改,可將多晶矽材料轉型成非晶矽材料。離子植入種類可包括矽、氬(例如,Ar或Ar+)、氙(例如,Xe或Xe+)、及鍺中的一個或多個。在另一方面,可執行,例如再結晶退火處理之退火處理以進一步改良材料層之晶粒結構。在一項具體實施例中,無論有或無離子植入,材料層均可經過退火以修改晶粒結構。
為能強化在光子裝置介電堆疊206中整體地形成之光子結構的效能,光子裝置介電堆疊206可包括可降低整體地製造之光子裝置與基板200之間的耦合的特徵。在一項具體實施例中,基板200可在圖3中所示內有光子裝置整體地形成之結構的區域中包括深溝絕緣特徵。
在光子裝置介電堆疊206內亦可圖樣成形有金屬化層220及金屬化層222。亦可圖樣成形有垂直延伸的通道224以在金屬化層220與波導210之間提供電通信。亦可圖樣成形有垂直延伸的通道226以在金屬化層220與金屬化層222之間提供電通信。關於光檢測器240,光檢測器240可包括可由在,例如鍺填充溝渠之溝渠中沉積之光子敏感材料所界定之構造230。光子敏感材料可將光子轉化成電子,並因此可將光子基礎信號轉化成電基礎信號。就光檢測器240而言,由通道224所界定之傳導路徑可用以將電壓輸入至波導210中。具有在構造238之高度之上的金屬化層220的傳導路徑可用於電信號檢測,其中電信號可基於透過波導210之光子信號輸送而輸出供光檢測器240進行檢測。
如同本說明書中所說明的,光子裝置介電堆疊206可經圖樣成形以界定一個或多個光子裝置,以便能在介電堆疊206內製造一個或多個光子裝置。可例如,根據波導210及/或波導214,圖樣成形光子裝置介電堆疊206之一個或多個層以界定一個或多個波導,如此便可在介電堆疊206內整體地製造一個或多個波導。可例如,根據光檢測器240,圖樣成形光子裝置介電堆疊206之一個或多個層以界定一個或多個光檢測器,如此便可在介電堆疊206內整體地製造一個或多個光檢測器。可圖樣成形光子裝置介電堆疊206之一個或多個層以界定一個或多個光柵耦合器,如此便可在介電堆疊206內整體地製造一個或多個光柵耦合器。可圖樣成形光子裝置介電堆疊206之一個或多個層以界定一個或多個光柵耦合器,如此便可在介電堆疊206內整體地製造一個或多個光柵耦合器。可圖樣成形光子裝置介電堆疊206之一個或多個層以界定一個或多個調變器,如此便可 在介電堆疊206內整體地製造一個或多個調變器。可圖樣成形光子裝置介電堆疊206之一個或多個層以界定一個或多個極化器,如此便可在介電堆疊206內整體地製造一個或多個極化器。可圖樣成形光子裝置介電堆疊206之一個或多個層以界定一個或多個分波器,如此便可在介電堆疊206內整體地製造一個或多個分波器。可圖樣成形光子裝置介電堆疊206之一個或多個層以界定一個或多個諧振器,如此便可在介電堆疊206內整體地製造一個或多個諧振器。
金屬化層220與金屬化層222可水平地界定延伸線路。由金屬化層220與222所界定之線路可水平地延伸通過光子裝置介電堆疊206之多數個區域。金屬化層220與222之形成一般而言可藉由分別沉積一個或多個中介層材料層到各個金屬化層220與222的至少頂高度,蝕刻以界定用以接收傳導材料的溝渠,以傳導材料填充空腔,以及隨後進行平坦化處理而分別至各個金屬化層220與222的頂高度。金屬化層220與222之形成一般而言亦可藉由沉積多數個相同厚度金屬化層,以及隨後進行遮罩與蝕刻處理而從不需要的區域移除層材料。金屬化層220與222可由金屬或其他傳導材料形成。由金屬化層222所界定之水平延伸線路可電連接至一個或多個垂直延伸通道226以便能將一個或多個控制、邏輯及/或動力信號垂直地及水平地分布至內部製造有一個或多個光子裝置之光子裝置介電堆疊206的不同區域。由金屬化層220所界定之水平延伸線路可電連接至一個或多個垂直延伸通道226及/或垂直延伸通道224以便能將一個或多個電控制、邏輯及/或動力信號垂直地及水平地分布在光子裝置介電堆疊206的不同區域之間。由金屬化層222所界定之線路可電連接至一個或多個垂直延伸通道226以便能將一個或多個電控制、邏輯及/或動力信號垂直地及水平地分布在光子裝置介電堆疊206的不同區域之間。
在圖4中顯示,建構如參考圖3所說明的光子結構對準於建構如參考圖2所說明的中介層基礎結構。現參考圖4,說明氧化物接合熱處理。可採用 低溫氧化物熔融接合。低溫氧化物熔融接合可在例如300℃或更低的低溫下執行。執行低溫氧化物熔融接合可如圖4中顯示沉積由二氧化矽形成之介電層。由二氧化矽形成之介電層302可沉積於中介層基礎介電堆疊126之上,而由二氧化矽形成之介電層304可沉積於光子裝置介電堆疊206之上。在沉積介電層302與304之前,可例如使用化學機械平坦化(CMP)對沉積介電層302與304的下表面進行拋光處理以界定平滑表面,進而因提升凡得瓦力的活化而有利於良好的接觸。介電層302與304之表面在經過沉積與平滑處理之後,可經處置而界定適當的表面化學以在原子層級上提升此二層之間的接合。
參考圖5,圖5說明在如圖2中顯示之光子中介層基礎結構與如圖3中顯示之光子結構之間的接合。如圖4中所說明的,透過使用低溫氧化物熔融接合對此二結構進行接合處理,可使此二結構一起形成一個整體並可在中介層基礎介電堆疊126與光子裝置介電堆疊206之間界定接合層306。使用介電層302與304的圖2之中介層基礎結構與圖3之光子結構的接合可透過退火處理而完成以使介電層302與304在退火後形成接合層306,此接合層306在一項具體實施例中可視為接合介電層,而在一項具體實施例中可由低溫氧化物熔融接合介電層提供。在一項具體實施例中,基板100可由塊體矽晶圓之基板提供,且基板200可由SOI晶圓之基板提供,以及在一項具體實施例中,每一晶圓可由300毫米晶圓提供,如圖5中所說明的一般,可使用如300毫米晶圓接合之晶圓接合以完成中介層基礎結構對光子結構的接合。
如同參考圖5所說明之接合可執行而將基礎中介層基板100(可由塊體晶圓提供)及基板200(可由SOI晶圓基板提供)之厚度維持在它們的完全厚度,例如具有約775微米之厚度。因此,參考圖5所說明的接合可在低晶圓破損風險的情況下執行並可在無須使用操作晶圓的情況下實施。
圖6說明移除基板200之後的如圖5中所示之光電系統,其在中介層300中經界定而具有基板100與中介層介電堆疊320,其中的中介層介電堆疊320可包括中介層基礎介電堆疊126、接合層306、及光子裝置介電堆疊206。可使用各種處理以移除基板200。例如,可使用拋光處理來移除大部分基板200的原始厚度,此拋光處理可停止在,例如與光子裝置介電堆疊206之頂高度離約10微米的預定距離處。基板200有,例如10微米厚度之相對較薄厚度部分剩餘,其中基板200係由矽形成。可例如透過反應離子蝕刻(RIE)來移除基板200之剩餘部分。反應離子蝕刻(RIE)對矽(其中基板200係由矽形成)可具有選擇性,因此可移除基板200之矽材料而不會移除光子裝置介電堆疊206之介電材料。
圖7說明在圖案成形之後形成垂直延伸穿透通道332與金屬化層334的圖6之光電系統。介電層324可在光子裝置介電堆疊206之上使用金屬鑲嵌製造處理形成以製造垂直延伸通道332與金屬化層334。溝渠特徵可使用,例如反應離子蝕刻(RIE)而在介電層324與光子裝置介電堆疊206中形成,反應離子蝕刻(RIE)對特定介電、聚合物遮罩膜、或底層金屬材料具有選擇性,因此可藉由反應離子蝕刻(RIE)移除材料以形成所需尺寸的特徵。形成的溝渠隨後可以例如銅之傳導材料填充而形成垂直延伸的穿透通道332與金屬化層334。在基板100係由矽形成的情況下,可完全地延伸通過或實質上完全地延伸通過基板100的垂直延伸穿透通道116可視為穿透通道並可視為穿透矽通道(TSV)。在光子裝置介電堆疊206包括一個或多個氧化物基礎介電層的情況下,可完全地延伸通過或實質上完全地延伸通過光子裝置介電堆疊206的垂直延伸穿透通道332可視為穿透通道並可視為穿透氧化物通道(TOV)。直徑可比穿透通道116或穿透通道332小的通道122、通道224與通道226可視為接觸通道,或者可在通道122、通道224與通道226的起迄處高度在介電堆疊126或206之高度範圍內的情況下視為內部堆疊通道。
關於如圖3中所示之左側穿透通道332,左側穿透通道332可延伸通過接合層306,且可電連接至製造於中介層基礎介電堆疊126中的金屬化層140。關於如圖3中所示之左側穿透通道332,左側穿透通道332可從製造於中介層基礎介電堆疊126中之金屬化層140延伸通過接合層306,通過複數個光子裝置介電堆疊206之層,並可結束於製造於光子裝置介電堆疊206之頂層處的金屬化層334。左側穿透通道332可延伸通過光子裝置介電堆疊206之多數個層。左側穿透通道332可延伸通過光子裝置介電堆疊206之多數個層,並因此可延伸通過製造於光子裝置介電堆疊206之不同高度處的複數個光子裝置之頂及底高度,例如通過波導212、光檢測器240及波導210之頂及底高度。關於如圖3中所示之右側穿透通道332,右側穿透通道332可從製造於光子裝置介電堆疊206中之金屬化層222延伸通過光子裝置介電堆疊206之複數個層,並可結束於製造於光子裝置介電堆疊206之頂層的金屬化層334。可如在圖7中所示之具體實施例中界定帶狀(鈎狀)連接的金屬化層334可提供從,例如界定在如圖7中所示之基板100之下的背側之下的區域的中介層300之背側至光子裝置介電堆疊206內所界定之任何裝置的傳導路徑。
如同在圖7之中間製造階段視圖中顯示,可界定提供帶狀(鈎狀)連接的傳導路徑以便能將來自中介層300之背側的輸入電壓輸入至光檢測器240中,其中所經過的傳導路徑經界定為由重新分布層508(背側)連接至延伸通過基板100之穿透通道116,連接至延伸通過光子裝置介電堆疊206的關聯垂直延伸穿透通道332,連接至金屬化層334(前側),連接至垂直延伸的穿透通道332,連接至金屬化層222,連接至通道226,連接至可將輸入電壓提供至光檢測器240之金屬化層220。連接垂直延伸穿透通道116及垂直延伸穿透通道332之橋接可由連接至垂直延伸穿透通道116之金屬化層118提供,其中金屬化層118連接至通道122,通道122連接至金屬化層120,金屬化層120再連接至垂直延伸穿透通道 332。光電系統10可包括多數個此類橋接,例如在一項具體實施例中,複數個垂直延伸穿透通道116之個別穿透通道116可分別包括各自的橋接,每一個別橋接將垂直延伸穿透通道116分別連接至延伸通過光子裝置介電堆疊206的各自的垂直延伸穿透通道332。金屬化層118、垂直延伸通道122、及金屬化層120可與中介層基礎介電堆疊126製造並界定為整體。如同圖7中所示,在穿透通道332延伸通過,例如波導214、波導210或光檢測器240之一個或多個光子裝置之底及頂高度的部分,穿透通道332可視為光子結構穿透通道。
參考光子裝置介電堆疊206,介電堆疊206之介電層可包括不同的材料。例如,介電層202可如同本說明書中所說明的由起始SOI晶圓之熱氧化物層提供。光子裝置介電堆疊206之介電層可經選擇而使波導效能最佳化,例如在一項具體實施例中,波導周圍的披覆層可由氧化矽烷提供。沉積於金屬化層之上的光子裝置介電堆疊206之介電層可經選擇以阻擋傳導材料的遷移。光子裝置介電堆疊206之剩餘層可由例如原矽酸四乙酯(TEOS)或其他合適的SiOx衍生物之材料形成。
圖8說明在圖樣成形以界定凸塊下金屬化構造336之後的圖7之光電系統10。在顯示的具體實施例中以襯墊提供的凸塊下金屬化構造336可經由包括沉積介電層326,及進一步圖樣成形以界定凸塊下金屬化構造336的處理來製造。在圖8中所描繪的階段中,中介層介電堆疊320包含在一項具體實施例中可由TEOS形成的介電層326。
圖9說明在黏結積體電路晶片400之後的光電系統10,在一項具體實施例中積體電路晶片400可由CMOS邏輯晶片提供。CMOS邏輯晶片400如同參考圖8中所說明的一般可包括與金屬化構造336對應的凸塊下金屬化構造。積體電路晶片400可藉由將積體電路晶片400倒裝晶片接合至凸塊下金屬化構造336而黏結至凸塊下金屬化構造,其中可使用介電層326來製造構造336。積體電路 晶片400之黏結可藉由在積體電路晶片400與介電層326之間的介面處施加環氧樹脂底部填充(未顯示)來增補。
圖10說明在黏結操作晶圓420之後如圖9中所示的光電系統10。操作晶圓420可使用黏性層410黏結至圖9中所示之結構。如圖10中所示,黏性層410可分布在積體電路晶片周圍並在介電層326之上,且操作晶圓420可黏著至黏性層410。操作晶圓420讓中介層300之背側在基板100薄化且不再能夠提供結構完整性以支持黏結裝置層之後仍可製造額外特徵。參考圖11將進一步說明在一項具體實施例中的製造處理。黏性層410可具有永久黏性或暫時黏性。在黏性層410為永久黏性層410的情況中,黏性層410可一直保持黏著於介電層326,直到完成如圖1顯示一般的所製造的中介層300。
圖11說明經額外處理而界定中介層背側特徵的如10中所示的光電系統10。參考圖11,基礎中介層基板100的材料可經移除而露出垂直延伸的穿透通道116之部分,這些垂直延伸的穿透通道116在圖11中所描繪的露出之前是結束於基板100內的。移除基板100之材料的執行可例如藉由拋光至標定最終高度之上的預定高度,且隨後進一步移除的執行可使用對基板100之材料具選擇性的反應離子蝕刻(RIE),以便能對基板100之材料選擇性移除。
圖12說明在沉積介電層502之後的如圖11中顯示的光電系統10,其中介電層502在一項具體實施例中可由TEOS形成。介電層502可經沉積及隨後平坦化而界定如圖12中顯示的平滑表面。
圖13說明在進一步圖樣成形以製造傳導背側重新分布層508之後的如圖12中顯示的光電系統10。可界定水平延伸重新分布線路的重新分布層508可提供以扇出由垂直延伸穿透通道116所界定的接觸點。重新分布層508的製造可藉由使用金屬鑲嵌處理,例如使用對介電層502之材料具選擇性的RIE來蝕刻介電層502,以選擇性移除介電層502之材料,且隨後以傳導材料填充界定重新 分布層之所界定的溝渠。參考圖11至13,可拋光基板100以露出穿透通道116之傳導材料並可執行額外的圖樣成形以形成重新分布層508(圖13)。例如,在圖12中顯示的階段中,在拋光平坦化至穿透通道116之底高度的基板之後,可在基板100之上沉積介電層502,接著再沉積重新分布層508,然後進行遮罩及蝕刻處理以移除重新分布層508之不需要的材料,進而界定重新分布層線路。在一項具體實施例中,可施加並以傳導材料填充光阻模板以形成重新分布層508。
圖14說明在沉積可為介電鈍化層的介電層504且隨後圖樣成形介電層504以界定溝渠而曝露重新分布層508之後的如圖13中顯示的光電系統10,其中曝露重新分布層508是為了準備並有利於選擇性施加凸塊下金屬化襯墊。參考圖14,其中有說明沉積介電層504,隨後如同在圖15中所說明的一般,在用於容納由凸塊下金屬化襯墊所提供之凸塊下金屬化構造的區域中凹進處理介電層504。
圖15說明在進一步圖樣成形以特別地在介電層504之曝露區域中界定凸塊下金屬化構造510而提供電連接至重新分布層508之後的如圖14中顯示的光電系統10。在製造凸塊下金屬化構造510之時,可分別在各自的凸塊下金屬化構造510內形成軟焊凸塊512。
製造如圖1中顯示的所製造中介層300時,相對於光子結構(圖3),可分開地製造中介層基礎結構(圖2)。中介層基礎結構可使用具有第一基板100之第一晶圓來製造,而光子結構(圖3)可使用具有第二基板200之第二晶圓來製造。在分別製造中介層基礎結構(圖2)與光子結構(圖3)之後,可使用低溫氧化物熔融接合處理將此二個晶圓組建結構接合在一起。在執行低溫氧化物接合處理之時,可在中介層基礎結構與光子結構之間,且具體而言在一項具體實施例中在中介層基礎介電堆疊126與光子裝置介電堆疊206之間界定接合層306。在進一步製造處理之後產生的如圖1中顯示的結果中介層300可賦予背 側至前側的電連接,如例如由分別與各自的延伸通過光子裝置介電堆疊206之穿透通道332相關聯的延伸通過基礎中介層基板100之穿透通道116所提供的背側至前側的電連接。
具有中介層300之如圖1中顯示的光電系統10可連接至下部結構,例如藉由將中介層300之軟焊凸塊512連接至下部結構之UMB構造(未顯示)。圖1之光電系統10可黏結的下部結構可例如由印刷電路板提供,或替代性地由例如球柵陣列或中介層來提供。
在替代性具體實施例中,中介層300可使用單一晶圓來完整地製造。例如,可製造如圖2中顯示之具有中介層基礎結構之組件的結構。接著,可在如圖2中顯示的結構頂部之上建構具有一個或多個光子裝置組件的結構。最後,可製造大型穿透通道而延伸通過具有例如一個或多個光子裝置之多數個光子特徵的中介層以提供背側至前側的電連接。儘管所描述的替代性方法可具有好處,然而在本說明書中說明的具體實施例亦揭露所描述的替代性具體實施例之方法具有的問題。例如,根據替代性具體實施例之可延伸通過如基板100之基礎中介層基板並通過光子裝置之高度的大型穿透通道預計將可占用光子裝置建構區域的顯著實際面積,從而限制可製造光子裝置的數目及大小。
在本說明書中參考圖1所說明的一個方面,可提供作為光子結構穿透通道的垂直延伸穿透通道332在一項具體實施例中大小可經比例調整而相當於對應延伸通過基礎中介層基板100的垂直延伸穿透通道116之大小的部分。在一項具體實施例中,可提供作為光子結構穿透通道的垂直延伸穿透通道332大小可經比例調整而相當於對應延伸通過基礎中介層基板100的穿透通道116之大小的0.5或更小。在一項具體實施例中,可提供作為光子結構穿透通道的垂直延伸穿透通道332大小可經比例調整而相當於對應延伸通過基礎中介層基板100的穿透通道116之大小的0.25或更小。在一項具體實施例中,可提供作為光子結構 穿透通道的垂直延伸穿透通道332大小可經比例調整而相當於對應延伸通過基礎中介層基板100的穿透通道116之大小的0.10或更小。在本段落上述的大小均指直徑、高度或體積的一個或多個大小。
在一個範例中,穿透通道332具有的尺寸可為直徑約1.0微米、高度約7.0微米,而穿透通道116具有的尺寸可為直徑約10微米、高度約100微米。在一項具體實施例中,垂直延伸穿透通道116與垂直延伸穿透通道332的尺寸可以是相異的,但可具有相同的長徑比,例如各自具有10x1長徑比,例如垂直延伸穿透通道332的尺寸大小可以是約0.7微米x7.0微米,且垂直延伸穿透通道116的尺寸大小可以是約10.0微米x100微米。讓穿透通道332的尺寸較小有利於在光子裝置介電堆疊206內製造額外的且較大型的光子裝置。讓穿透通道332運載一個或多個控制、邏輯及/或動力信號而非接觸如通道226之通道可有助於避免例如與不需要的電壓降及雜散電容產生有關的各種電氣問題。
在本說明書中說明的製造方法可有利於提供許多組具有不同基板的中介層300。使用本說明書中的方法,第一組一個或多個中介層可製造成具有第一材料之基板,以及第二組一個或多個中介層可製造成具有基板。在本說明書中有說明,在界定第一基板之第一晶圓之上建立中介層基礎結構;在界定第二基板之第二晶圓之上建立光子結構;以及將光子結構接合至中介層基礎結構以界定具有中介層基礎結構的中介層及在光子裝置介電堆疊內所製造的一個或多個光子裝置。在一項具體實施例中,可修改此方法,而使中介層基礎結構的建立為可重覆,以便能使用具有材料與第一晶圓之基板材料相異之基板的第二第一晶圓來建立第二基礎結構。可透過反覆建立光子結構以使用額外的第二晶圓建立第二光子結構來進一步修改方法。可藉由將第二光子結構接合至第二中介層基礎結構進一步修改方法。
本說明書中所使用的術語僅用於說明特殊具體實施例之目的,而非意圖進行限制。如同本說明書中使用的,單數形式「一」、「一個」及「該」也意欲包括複數形式,除非上下文中有另外清楚指明。進一步將理解的是,術語「包含」(以及所有形式的包含,如「含」與「蘊含」)、「具有」(以及所有形式的具有,如「有」與「存有」)、「包括」(以及所有形式的包括,如「囊括」與「含括」)、以及「含有」(以及所有形式的含有,如「內含」與「內容」)為開放式連綴動詞。因此,「包含」、「具有」、「包括」、或「含有」一個或多個步驟或元件的方法或裝置擁有一個或多個步驟或元件,但並不限於僅擁有此一個或多個步驟或元件。同樣地,「包含」、「具有」、「包括」、或「含有」一個或多個特徵的方法之步驟或裝置之元件擁有此一個或多個特徵,但並不僅限於此一個或多個特徵。術語「由...所界定」包括元件部分地由...所界定的關係,以及元件全部地由...所界定的關係。本說明書中的數字識別詞,例如「第一」及「第二」為隨機選定以指示不同元件的術語,而非指示元件的順序。此外,以特定方式設定的系統方法或設備為以至少此方法設定,但亦可以未列出的方法來設定。此外,在說明時為具有特定數目之元件的系統方法或設備在實際操作時可具有少於或多於此特定數目之元件。
在下方的申請專利範圍中,所有手段或步驟功能用語的對應結構、材料、作用、及等效物,如果有的話,均意欲包括用於結合如特別聲明的其他請求元件以執行此功能的任何結構、材料、或作用。對本發明的說明描述目的在於解說與描述,而不是為了要詳盡說明或限制在揭示形式下的本發明。對於此項技術具有通常知識者將明白,本發明可有許多修改與變更,而不致背離本發明的範疇與精神。具體實施例的選定與說明係為了能夠最清楚地說明本發明及實際操作應用之一個或多個方面的原理,並且讓其他對於此項技術具有 通常知識者能夠理解本發明之一個或多個方面在各種不同的具體實施例中可進行各種不同的修改以合乎所希望的特殊用途。
10‧‧‧光電系統
100‧‧‧基板
102‧‧‧介電層
104‧‧‧介電層
106‧‧‧介電層
108‧‧‧介電層
110‧‧‧介電層
112‧‧‧介電層
116‧‧‧穿透通道
118‧‧‧金屬化層
120‧‧‧金屬化層
122‧‧‧通道
126‧‧‧介電堆疊
206‧‧‧介電堆疊
210‧‧‧波導
214‧‧‧波導
220‧‧‧金屬化層
222‧‧‧金屬化層
224‧‧‧通道
226‧‧‧通道
238‧‧‧構造
240‧‧‧光檢測器
300‧‧‧中介層
306‧‧‧接合層
320‧‧‧介電堆疊
324‧‧‧介電層
326‧‧‧介電層
332‧‧‧通道
334‧‧‧金屬化層
400‧‧‧晶片
502‧‧‧介電層
504‧‧‧介電層
508‧‧‧重新分布層
510‧‧‧凸塊下金屬化構造
512‧‧‧軟焊凸塊

Claims (42)

  1. 一種製造光電系統的方法,包含:在具有一第一基板之一第一晶圓之上建立一中介層基礎結構,其中該中介層基礎結構的建立係包括製造為延伸通過該第一基板的複數個穿透通道及在該第一基板之上所形成之一中介層基礎介電堆疊內製造一個或多個金屬化層;在具有一第二基板之一第二晶圓之上建立一光子結構,其中該光子結構的建立係包括在該第二基板之上所形成之一光子裝置介電堆疊內製造一個或多個光子裝置;以及將該光子結構接合至該中介層基礎結構以界定具有該中介層基礎結構及在該光子裝置介電堆疊內所製造的一個或多個該光子裝置的一中介層。
  2. 如請求項1所述之方法,其中該接合包括使用一低溫氧化接合處理。
  3. 如請求項1所述之方法,其中該接合包括使用一低溫氧化熔融接合處理,其包括一拋光階段、一活化階段及一退火階段。
  4. 如請求項1所述之方法,其中該第一晶圓係具有半導體或絕緣性質之一晶圓。
  5. 如請求項1所述之方法,其中該第二晶圓係一絕緣層上覆矽(SOI)晶圓。
  6. 如請求項1所述之方法,其中該第一晶圓係一塊體矽晶圓及其中該第二晶圓係一SOI晶圓。
  7. 如請求項1所述之方法,其中該方法包括接續該接合步驟之後自該第一基板移除材料以露出該複數個穿透通道之多數個穿透通道而使該複數個穿透通道之多數個該穿透通道完全延伸通過該第一基板。
  8. 如請求項1所述之方法,其中該製造為延伸通過該第一基板的複數個穿透通道係包括執行該製造而使該複數個穿透通道之多數個穿透通道在該第一基板內延伸至使該複數個穿透通道之多數個該穿透通道在執行移除該第一基板之材料以露出該複數個穿透通道時完全延伸通過該第一基板的深度。
  9. 如請求項1所述之方法,其中在該第二晶圓之上的該光子結構的建立係包括在一光子裝置介電堆疊內製造選自係由一波導及一光檢測器組成之群組的一個或多個光子裝置。
  10. 如請求項1所述之方法,其中在該第二晶圓之上的該光子結構的建立係包括在該光子裝置介電堆疊內製造一第一材料之一第一波導及一第二材料之一第二波導。
  11. 如請求項1所述之方法,其中在該第二晶圓之上的該光子結構的建立係包括在一光子裝置介電堆疊內製造選自係由一波導、一光檢測器、一光柵耦合器、一調變器、一極化器、一分波器及一諧振器組成之群組的一個或多個光子裝置。
  12. 如請求項1所述之方法,其中在該第二晶圓之上的該光子結構的建立係包括在一光子裝置介電堆疊內製造一第一材料之一第一波導及一第二材料之一第二波導,其中該在一第二晶圓上建立一光子結構包括在一光子裝置介電堆疊內製造該第一波導於一第一高度上及該第二波導於一第二高度上。
  13. 如請求項1所述之方法,其中該方法包括形成穿透該光子裝置介電堆疊之複數個光子結構穿透通道。
  14. 如請求項1所述之方法,其中該方法包括形成穿透該光子裝置介電堆疊之複數個光子結構穿透通道,及使用個別橋接以將該複數個光子結構穿透通道之多數個光子結構穿透通道連接至該複數個穿透通道之多數個穿透通道,該些個別橋接具有界定在該中介層基礎介電堆疊之內的特徵。
  15. 如請求項1所述之方法,其中在該第二晶圓之上的該光子結構的建立係包括在一光子裝置介電堆疊內製造一第一材料之一第一波導及一第二材料之一第二波導,其中在該第二晶圓之上的該光子結構的建立係包括在一光子裝置介電堆疊內製造該第一波導於一第一高度上及該第二波導於一第二高度上,及其中在該第二晶圓之上的該光子結構的建立係包括在該光子裝置介電堆疊內製造包括光敏材料之一光檢測器。
  16. 如請求項1所述之方法,其中該方法包括反覆建立中介層基礎結構於另一晶圓上而建立一第二中介層基礎結構,該另一晶圓具有與該第一晶圓之一基板材料為不同的基板材料;反覆建立該光子結構以使用一額外第二晶圓建立一第二光子結構,及將該第二光子結構接合至該第二中介層基礎結構。
  17. 如請求項1所述之方法,其中該接合係界定一接合層,該接合層位在該中介層基礎介電堆疊及該光子裝置介電堆疊之間,其中該方法係經執行而使該複數個穿透通道之一穿透通道連接至關聯的一垂直延伸光子結構穿透通道,以及該方法係經執行而使該垂直延伸光子結構穿透通道延伸通過該光子裝置介電堆疊及該接合層。
  18. 如請求項1所述之方法,其中該方法包括形成具有一重新分布層的一導電路徑,該重新分布層連接至延伸通過該第一基板的該複數個穿透通道之該穿透通道,其中的穿透通道係連接至關聯的一垂直延伸光子結構穿透通道,其中該方法係經執行而使該垂直延伸光子結構穿透通道延伸通過該光子裝置介電,其中該方法包括於該第一基板之一前側之上形成該中介層基礎介電堆疊,以及於該第一基板之一背側之上形成該重新分布層。
  19. 如請求項1所述之方法,其中該方法包括形成提供有一帶狀連接之一導電路徑,該帶狀連接由包括連接至延伸通過該第一基板之該複數個穿透通道之該穿透通道之一重新分布層的一導電路徑所界定,其中的穿透通道係 連接至延伸通過該光子裝置介電堆疊之關聯的一第一垂直延伸光子結構穿透通道,其中該方法係經執行而使該第一垂直延伸光子結構穿透通道連接至一第一金屬化層,其中的第一金屬化層係連接至一第二垂直延伸光子結構穿透通道,其中的第二垂直延伸光子結構穿透通道係連接至一第二金屬化層,其中該第二金屬化層係比該第一金屬化層位於一較低高度。
  20. 如請求項1所述之方法,其中該方法包括形成具有一重新分布層的一導電路徑,該重新分布層連接至延伸通過該第一基板的該複數個穿透通道之該穿透通道,其中的穿透通道係藉由橋接連接至關聯的該垂直延伸光子結構穿透通道,其中該方法包括於該第一基板之一前側之上形成該中介層基礎介電堆疊,其中該方法包括於該第一基板之一背側之上形成該重新分布層,其中該橋接包括形成在該中介層基礎介電堆疊中的特徵。
  21. 如請求項1所述之方法,其中該方法包括形成具有一重新分布層的一導電路徑,該重新分布層連接至延伸通過該第一基板的該複數個穿透通道之該穿透通道,其中的穿透通道係藉由橋接連接至關聯的該垂直延伸光子結構穿透通道,其中該中介層基礎介電堆疊係形成於該第一基板之一前側之上,其中該重新分布層係形成於該第一基板之一背側之上,其中該橋接包括形成在該中介層基礎介電堆疊中的特徵,其中該方法包括形成該橋接以包括連接至該複數個穿透通道之該穿透通道的該中介層基礎介電堆疊中所形成的一第一金屬化層,連接至該第一金屬化層的該中介層基礎介電堆疊中所形成的一接觸通道,連接至該接觸通道的該中介層基礎介電堆疊中所形成的一第二金屬化層,其中的第二金屬化層係連接至關聯的該垂直延伸光子結構穿透通道。
  22. 如請求項1所述之方法,其中該將該光子結構接合至該中介層基礎結構包括執行該接合以界定在該中介層基礎結構與該光子結構介電堆疊,其中該方法包括形成具有一重新分布層的一導電路徑,該重新分布層連接至延 伸通過該第一基板的該複數個穿透通道之該穿透通道,其中的穿透通道係藉由橋接連接至關聯的該垂直延伸光子結構穿透通道,其中該垂直延伸光子結構穿透通道延伸通過將該中介層基礎介電堆疊與該光子裝置介電堆疊連接的該接合層,其中該方法包括於該第一基板之一前側之上形成該中介層基礎介電堆疊,以及於該第一基板之一背側之上形成該重新分布層,其中該方法包括形成界定該中介層基礎介電堆疊中之該橋接的一金屬化層。
  23. 一種光電系統,包含:一基板;一中介層介電堆疊,形成於該基板上,該中介層介電堆疊包括一中介層基礎介電堆疊、一光子裝置介電堆疊、及將該光子裝置介電堆疊整體接合至該中介層基礎介電堆疊的一接合層;一個或多個穿透通道,延伸通過該基板;一個或多個金屬化層,製造於該中介層基礎介電堆疊中;以及一個或多個光子裝置,製造於該光子裝置介電堆疊中,其中該一個或多個穿透通道之一穿透通道連接至關聯的一垂直延伸光子結構穿透通道,該垂直延伸光子結構穿透通道延伸通過該光子裝置介電堆疊及該接合層。
  24. 如請求項23所述之光電系統,其中該一個或多個光子裝置包括一波導。
  25. 如請求項23所述之光電系統,其中該一個或多個光子裝置包括一光檢測器。
  26. 如請求項23所述之光電系統,其中該一個或多個光子裝置包括由一第一材料所形成之一第一波導及由一第二材料所形成之一第二波導。
  27. 如請求項23所述之光電系統,其中該一個或多個光子裝置包括形成於一第一高度上之一第一波導及形成於一第二高度上之一第二波導。
  28. 如請求項23所述之光電系統,其中該一個或多個光子裝置包括於一第一高度上之由一第一材料所形成之一第一波導及於一第二高度上之由一第二材料所形成之一第二波導。
  29. 如請求項23所述之光電系統,其中該基板係由一半導體或絕緣基板所形成。
  30. 如請求項23所述之光電系統,其中該光電系統包括形成於該基板之上的一背側金屬重新分布層。
  31. 如請求項23所述之光電系統,其中該光電系統包括形成於該光子裝置介電堆疊之一高度之上的多數個前側構造,該些前側構造承接一CMOS邏輯積體電路晶片。
  32. 如請求項23所述之光電系統,其中該光電系統包括在該光電系統之一背側之上形成的多數個背側構造,該些背側構造有利於將該光電系統焊接至選自係由一球柵陣列、一印刷電路板、及一中介層組成之群組的一下部結構。
  33. 如請求項23所述之光電系統,其中該光電系統包括提供一帶狀連接之一導電路徑,該帶狀連接由包括連接至穿透該基板而延伸之一穿透通道之一重新分布層的一導電路徑所界定,其中的穿透通道係連接至延伸通過該光子裝置介電堆疊及該接合層之關聯的該垂直延伸光子結構穿透通道,其中的垂直延伸光子結構穿透通道係連接至一第一金屬化層,其中的第一金屬化層係連接至一第二垂直延伸光子結構穿透通道,其中的第二垂直延伸光子結構穿透通道係連接至一第二金屬化層,其中該第二金屬化層係比該第一金屬化層位於一較低高度。
  34. 如請求項23所述之光電系統,其中該一個或多個穿透通道之一穿透通道係連接至關聯的該垂直延伸光子結構穿透通道,該垂直延伸光子結構穿透通道延伸通過該光子裝置介電堆疊及該接合層。
  35. 如請求項23所述之光電系統,其中該一個或多個穿透通道之一穿透通道係藉由一橋接連接至關聯的該垂直延伸光子結構穿透通道,該垂直延伸光子結構穿透通道延伸通過該光子裝置介電堆疊及該接合層。
  36. 如請求項23所述之光電系統,其中該一個或多個穿透通道之一穿透通道係藉由一橋接連接至關聯的該垂直延伸光子結構穿透通道,該垂直延伸光子結構穿透通道延伸通過該光子裝置介電堆疊及該接合層,該橋接具有製造於該中介層基礎介電堆疊中的多數個特徵,且其中該垂直延伸光子結構穿透通道係該穿透通道之大小的0.5倍或更小。
  37. 如請求項23所述之光電系統,其中該光電系統包括具有一重新分布層的一導電路徑,該重新分布層連接至延伸通過該基板的該一個或多個穿透通道之該穿透通道,其中的穿透通道係連接至關聯的該垂直延伸光子結構穿透通道,其中該中介層基礎介電堆疊形成於該基板之一前側之上,其中該重新分布層形成於該基板之一背側之上。
  38. 如請求項23所述之光電系統,其中該光電系統包括具有一重新分布層的一導電路徑,該重新分布層連接至延伸通過該基板的該一個或多個穿透通道之該穿透通道,其中的穿透通道係藉由橋接連接至關聯的該垂直延伸光子結構穿透通道,其中該中介層基礎介電堆疊形成於該基板之一前側之上,其中該重新分布層形成於該基板之一背側之上,其中該橋接包括形成在該中介層基礎介電堆疊中的特徵。
  39. 如請求項23所述之光電系統,其中該光電系統包括具有一重新分布層的一導電路徑,該重新分布層連接至延伸通過該基板的該一個或多個穿 透通道之該穿透通道,其中的穿透通道係藉由橋接連接至關聯的該垂直延伸光子結構穿透通道,其中該中介層基礎介電堆疊形成於該基板之一前側之上,其中該重新分布層形成於該基板之一背側之上,其中該橋接包括形成在該中介層基礎介電堆疊中的特徵,其中該橋接包括連接至該一個或多個穿透通道之該穿透通道的該中介層基礎介電堆疊中所形成的一第一金屬化層,連接至該第一金屬化層的該中介層基礎介電堆疊中所形成的一接觸通道,連接至該接觸通道的該中介層基礎介電堆疊中所形成的一第二金屬化層,其中的第二金屬化層係連接至關聯的該垂直延伸光子結構穿透通道。
  40. 如請求項23所述之光電系統,其中該光電系統包括具有一重新分布層的一導電路徑,該重新分布層連接至延伸通過該基板的該一個或多個穿透通道之該穿透通道,其中的穿透通道係藉由橋接連接至關聯的該垂直延伸光子結構穿透通道,其中該中介層基礎介電堆疊形成於該基板之一前側之上,其中該重新分布層形成於該基板之一背側之上,其中該橋接包括形成在該中介層基礎介電堆疊中的該金屬化層。
  41. 一種光電系統,包含:一基板;一中介層介電堆疊,形成於該基板上,該中介層介電堆疊包括一中介層基礎介電堆疊、一光子裝置介電堆疊、及將該光子裝置介電堆疊整體接合至該中介層基礎介電堆疊的一接合層;一個或多個穿透通道,延伸通過該基板;一個或多個金屬化層,製造於該中介層基礎介電堆疊中;以及一個或多個光子裝置,製造於該光子裝置介電堆疊中,其中該一個或多個穿透通道之一穿透通道藉由橋接連接至關聯的一垂直延伸光子結構穿透通道,該垂直延伸光子結構穿透通道延伸通過該光子裝置介電 堆疊,其中該橋接界定在該中介層基礎介電堆疊中,以及其中該橋接包括直徑小於該穿透通道的一垂直延伸接觸通道。
  42. 一種光電系統,包含:一基板;一中介層介電堆疊,形成於該基板上,該中介層介電堆疊包括一中介層基礎介電堆疊、一光子裝置介電堆疊、及將該光子裝置介電堆疊整體接合至該中介層基礎介電堆疊的一接合層;一個或多個穿透通道,延伸通過該基板;一個或多個金屬化層,製造於該中介層基礎介電堆疊中;以及一個或多個光子裝置,製造於該光子裝置介電堆疊中,其中該光電系統包括提供有一帶狀連接之一導電路徑,該帶狀連接由包括連接至延伸通過該基板之一穿透通道所界定,其中的穿透通道係連接至延伸通過該光子裝置介電堆疊之關聯的一第一垂直延伸光子結構穿透通道,其中的第一垂直延伸光子結構穿透通道係連接至一第一金屬化層,其中的第一金屬化層係連接至一第二垂直延伸光子結構穿透通道,其中的第二垂直延伸光子結構穿透通道係連接至一第二金屬化層,其中該第二金屬化層係比該第一金屬化層位於一較低高度。
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