CN110892301A - 晶圆规模键合的有源光子中介层 - Google Patents

晶圆规模键合的有源光子中介层 Download PDF

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Publication number
CN110892301A
CN110892301A CN201880030723.2A CN201880030723A CN110892301A CN 110892301 A CN110892301 A CN 110892301A CN 201880030723 A CN201880030723 A CN 201880030723A CN 110892301 A CN110892301 A CN 110892301A
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Prior art keywords
photonic
dielectric stack
substrate
interposer
wafer
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CN201880030723.2A
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道格拉斯·库尔博
小道格拉斯·拉图利佩
杰拉尔德·利克
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Research Foundation of State University of New York
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Research Foundation of State University of New York
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Abstract

本文阐述了一种方法，所述方法包括：在具有第一基板的第一晶圆上构建中介层基础结构，其中构建中介层基础结构包括：制造延伸穿过第一基板的多个贯穿过孔，并且在形成在第一基板上的中介层基础介电堆叠内制造一个或多个金属化层；在具有第二基板的第二晶圆上构建光子结构，其中构建光子结构包括：在形成在第二基板上的光子器件介电堆叠内制造一个或多个光子器件；以及将光子结构键合至中介层基础结构，以限定具有中介层基础结构以及在光子器件介电堆叠内制造的一个或多个光子器件的中介层。

Description

晶圆规模键合的有源光子中介层
相关申请的交叉引用
本申请要求于2017年4月27日提交的、题为“Wafer Scale Bonded ActivePhotonics Interposer”的美国临时申请No.:62/490,665的优先权，该申请通过引用其全部而并入本文。本申请还要求于2018年2月8日提交的、题为“Wafer Scale Bonded ActivePhotonics Interposer”的美国非临时申请No.15/891,847的优先权，该申请通过引用其全部而并入本文。上述于2018年2月8日提交的、题为“Wafer Scale Bonded ActivePhotonics Interposer”、通过引用其全部而并入本文的美国非临时申请No.15/891,847要求了上述于2017年4月27日提交的、题为“Wafer Scale Bonded Active PhotonicsInterposer”、通过引用其全部而并入本文的美国临时申请No.:62/490,665的优先权。
政府权利声明
本发明是在美国国防部(Department of Defense,DoD)的政府支持下、根据授予合约编号FA8650-15-2-5220进行的。政府可以对本发明拥有特定的权利。
技术领域
本公开总体上涉及光子学，并且尤其涉及光子结构和制造工艺。
背景技术
商购可得的光子集成电路是在诸如体硅(bulk silicon)或绝缘体上硅(silicon-on-insulator)之类的晶圆上制造的。商购可得的预制光子集成电路芯片可以包括用于在预制光子集成电路芯片的不同区域之间传输光信号的波导。商购可得的波导为矩形或脊形几何形状，并且由硅(单晶硅或多晶硅)或者氮化硅制成。商购可得的光子集成电路芯片可以在具有设置在印刷电路板上的光子集成电路芯片的系统上获得。
发明内容
通过在一个方面提供的一种光子结构，克服了现有技术的缺点，并且提供了附加的优点。
本文阐述了一种方法，所述方法包括：在第一晶圆上构建中介层(interposer)基础结构，其中构建中介层基础结构包括：制造延伸穿过基板的多个贯穿过孔(through via)并且在中介层基础介电堆叠(dielectric stack)内制造一个或多个金属化层；在第二晶圆上构建光子结构，其中构建光子结构包括：在光子器件介电堆叠内制造一个或多个光子器件；以及将所述光子结构键合(bond)至所述中介层基础结构以限定具有所述中介层基础结构和一个或多个光子器件的中介层。本文阐述了一种光电系统，所述光电系统包括：基板；形成在所述基板上的中介层介电堆叠，所述中介层介电堆叠包括基础中介层堆叠、以及光子器件介电堆叠、以及键合层介电堆叠，所述键合层介电堆叠将所述光子器件介电堆叠键合至所述基础中介层介电堆叠。
通过本公开的技术实现了附加的特征和优点。
附图说明
本公开的一个或多个方面作为示例在随说明书所附的权利要求书中被特别地指出并清楚地要求保护。根据以下结合随附附图所进行的详细描述，本公开的前述和其他目的、特性和优点显而易见，在附图中：
图1是具有中介层的光电系统的剖面侧视图，所述中介层包括中介层介电堆叠，在所述中介层介电堆叠中制造并限定了一个或多个光子器件；
图2例示了光电系统，所述光电系统处于在具有晶圆基板的体晶圆(bulk wafer)上构建中介层基础之后的中间制造阶段；
图3是例示了光电系统的截面侧视图，所述光电系统处于构建光子结构之后的局部制造阶段，所述光子结构具有光子结构介电堆叠，在所述光子结构介电堆叠中成一体地制造并限定了一个或多个光子器件，并且其中所述构建是使用绝缘体上硅(silicon overon insulator,SOI)晶圆来进行的；
图4是例示了光电系统的制造的截面侧视图，其示出了图2的中介层基础结构与图3的光子结构对准；
图5是例示了图3所示的光子结构键合至图2的中介层基础结构的截面侧视图；
图6是如图5所示的光电系统处于在从光子结构去除基板之后的局部制造阶段的截面侧视图；
图7是如图6所示的光电系统处于以下操作之后的中间制造阶段的截面侧视图，所述操作为：进一步进行图案化以限定层间和层内过孔和金属化层(一个或多个)以用于键合的器件层之间的连接，并提供至具有中介层基板的制造的中介层的背面的电连接；
图8是如图7所示的光电系统处于在进一步进行图案化以限定凸块下金属化成型件(formation)之后的中间制造阶段的截面侧视图；
图9例示了如图8所示的光电系统处于将集成电路芯片的金属焊料附接至如图8所示制备的凸块下金属化形成体之后的中间制造阶段的截面侧视图；
图10是例示了如图9所示的光电系统处于使用粘合剂、环氧树脂或其他永久性有机聚合物将操作晶圆(handle wafer)附接至如图9所示的结构之后的中间制造阶段的截面侧视图；
图11是例示了如图10所示的光电系统在去除限定中介层基础的基板的材料之后的截面侧视图；
图12是如图11所示的光电系统在沉积介电层之后的截面侧视图；
图13是如图12所示的光电系统处于进行图案化以限定中介层背面再分布层之后的中间制造阶段的截面侧视图；
图14是例示了如图13所示的光电系统处于在对可以是介电钝化层的介电层进行沉积之后的中间制造阶段的截面侧视图；以及
图15是如图14所示的光电系统在进一步进行图案化以限定凸块下金属化成型件并在所述凸块下金属化成型件内制造焊料凸块之后的截面侧视图。
具体实施方式
下面参照在随附附图中例示的非限制性示例，更全面地说明本公开的各个方面及其某些特性、优点和细节。省略了对公知的材料、制造工具、加工技术等的描述，以便不会不必要地使本公开的细节模糊。然而，应当理解，详细描述和具体示例虽然指示了本公开的各个方面，但是仅是以例示的方式给出的，而不是以限制的方式给出的。根据本公开，在基本发明概念的精神和/或范围内的各种替换、修改、添加和/或布置对于本领域的技术人员来说将显而易见。
在图1中，示出了光电系统10，所述光电系统具有有源光子中介层300，所述有源光子中介层可以包括一个或多个有源光子器件，所述有源光子器件可以将光子信号转换为电信号。光子中介层300可以包括由基板100限定的中介层基础。
中介层300可以包括中介层基础，所述中介层基础具有基板100和中介层基础介电堆叠126。可以在中介层基础介电堆叠126内制造一个或多个金属化层，例如金属化层118、金属化层122以及竖向延伸的过孔122。中介层基础可以支撑贯穿过孔116，所述贯穿过孔可以延伸穿过基板100的厚度。在一种实施方式中，贯穿过孔116可以通过全部地(完全地)延伸穿过基板100的厚度来延伸穿过基板100的厚度。在一种实施方式中，贯穿过孔116可以通过部分地延伸穿过基板100的厚度来延伸穿过基板100的厚度。基板100可以由例如硅(Si)、蓝宝石或玻璃形成。在基板100上，可以制造背面再分布层508，以用于向贯穿过孔116辐射(fan out)电信号或从贯穿过孔116辐射电信号。
中介层300还可以包括光子器件介电堆叠206，在所述光子器件介电堆叠中可以制造并限定一个或多个光子器件，例如一个或多个波导210、一个或多个波导214以及一个或多个光电探测器240。光子器件介电堆叠206可以支撑一个或多个贯穿过孔332，所述贯穿过孔可以延伸穿过光子器件介电堆叠206的厚度。在一种实施方式中，贯穿过孔332可以通过全部地(完全地)延伸穿过光子器件介电堆叠206来延伸穿过光子器件介电堆叠206。在一种实施方式中，贯穿过孔332可以通过延伸穿过一个或多个光子器件的底部高度(elevation)和顶部高度来延伸穿过光子器件介电堆叠206。在一种实施方式中，贯穿过孔332可以通过延伸穿过多个光子器件的底部高度和顶部高度来延伸穿过光子器件介电堆叠202。在一种实施方式中，贯穿过孔332可以通过部分地延伸穿过光子器件介电堆叠206来延伸穿过光子器件介电堆叠206。可以在光子器件介电堆叠206内制造一个或多个金属化层，例如金属化层220、金属化层222以及竖向延伸的过孔226。如本文所阐述的金属化层限定水平延伸的线以承载控制信号、逻辑信号和/或功率信号中的一者或多者。
在一个方面，延伸穿过光子器件介电堆叠206的贯穿过孔332的过孔可以与延伸穿过基板100的厚度的相应的贯穿过孔116相关联。有利地，贯穿过孔332的尺寸可以显著小于贯穿过孔116的尺寸，从而释放光子器件介电堆叠206中的基板面，允许在光子器件介电堆叠206中制造附加的和/或更大的光子器件。贯穿过孔116可以通过桥连接来连接至相关联的贯穿过孔332。中介层300可以包括键合层306，所述键合层将中介层基础介电堆叠126键合至光子器件介电堆叠206。支撑在基板100上的中介层300可以包括中介层介电堆叠320，所述中介层介电堆叠包括中介层基础介电堆叠126、键合层306和光子器件介电堆叠206。
如图1所示的中介层300的特征可以为：背面至正面的电连接，例如，由多个贯穿过孔116中的贯穿过孔提供，所述贯穿过孔延伸穿过基础中介层基板100并与延伸穿过光子器件介电堆叠206的多个贯穿过孔332中的相应的贯穿过孔相关联。如图1所示的中介层300的特征可以为：背面和正面布线，例如用于水平分布控制信号、逻辑信号和/或功率信号中的一者或多者。中介层300的背面可以包括一个或多个再分布层，例如再分布层508，用于限定背面布线。中介层300的正面可以包括一个或多个金属化层，例如金属化层334，用于限定正面布线。
光电系统10可以包括凸块下金属化成型件510，在该实施方式中提供为由焊盘示出，所述焊盘与延伸穿过基板100的竖向延伸的贯穿过孔116电通信。中介层300的焊料凸块512可以形成在凸块下金属化焊盘510上。
图2例示了制造可以包括基板100和中介层基础介电堆叠126的中介层基础结构。基板100可以支撑贯穿过孔116，在基板100是硅基板的情况下，所述贯穿过孔可以被称为穿硅孔(through silicon via,TSV)。在一种实施方式中，基板100可以由体硅晶圆提供。为了形成竖向延伸的贯穿过孔116，基板100可以经受刻蚀，例如反应离子刻蚀(reactive ionetching,RIE)，并且所产生的沟槽可以填充有导电性材料。图2的结构可以被图案化以包括多个介电层，诸如介电层102、104、106、108、110和112，这些介电层由基板100支撑并限定中介层基础介电堆叠126。在中介层基础介电堆叠126内，可以有图案化的多个金属化层，诸如金属化层118和金属化层120。竖向延伸的贯穿过孔116可以在中介层基础介电堆叠126内制造，以在如图1所示出的制造的光子中介层300的正面和背面上的金属化层之间提供电连接。在一些实施方式中，不同的介电层102、104、106、108、110和112的材料可以是不同的。例如，介电层102可以用作对贯穿过孔116进行图案化的硬掩模，并且可以被选择用于优化其作为硬掩模的功能。诸如介电层104、108和112之类的介电层可以沉积在相应的金属化层或其他导电性材料成型件之上，并且可以被选择为抑制导电性材料迁移。诸如层104和106之类的剩余介电层可以由除了限定中介层基础介电堆叠126的剩余介电层的介电材料之外的介电材料形成。在一种实施方式中，介电层104和106可以由正硅酸乙酯(tetraethylorthosilicate,TEOS)或其他适当的SiOx衍生物形成。
图3例示了制造具有光子介电堆叠206的光子结构，在所述光子介电堆叠中可以制造并限定一个或多个光子器件，诸如波导210中的一个或多个波导、波导214中的一个或多个波导、或者一个或多个光电探测器240。可以使用绝缘体上硅(SOI)晶圆来制造如图3所示的光子结构。这种SOI晶圆可以被预制造成包括形成在基板上的绝缘体和形成在所述绝缘体上的薄的硅层。图3例示了在进行图案化之后SOI晶圆的剩余元件。也就是说，基板200可以是SOI晶圆的基板，介电层202可以是SOI晶圆的绝缘体层，并且如图3所示的波导210可以由以下限定：在对SOI晶圆的硅层进行图案化以限定波导210之后的该层的剩余部分。
参照图3，可以在介电层204上形成一个或多个介电层204，在一种实施方式中，该介电层可以由SOI晶圆的绝缘体层提供，以限定光子器件介电堆叠206。在介电堆叠206中，可以存在由不同材料形成的图案化波导。例如，波导210可以由硅形成，而波导214可以由诸如氮化硅SiN之类的不同的材料形成。一些应用可能偏爱使用硅波导，而其他应用可能偏爱使用氮化硅波导。提供由不同材料构成的波导可以增强图3所示的结构的性能和灵活性/柔性。在介电堆叠206中，可以有在不同的高度处形成的图案化波导。例如，如所示出的，可由硅形成的波导210可以形成在第一高度处，并且可由氮化物形成的波导214可以分别形成在第二高度、第三高度和第四高度处。
参照在图3的中间制造阶段视图中所示的附加特征，光电系统10可以包括与光子器件介电堆叠206成一体地形成的一个或多个光子器件。在一些实施方式中，形成光子器件(诸如光电探测器240)的材料，例如单晶硅、多晶硅、锗，可以外延生长。本文的实施方式认识到，虽然厚的硅层可以适应外延生长，但是所产生的光子器件可能通过厚的硅层呈现光损失。在一种实施方式中，为了适应外延生长材料的外延生长，可以提供在绝缘体上具有硅(硅模板)的籽晶层的结构。籽晶层可以是结晶籽晶层。为了提供具有硅的籽晶层的结构，可以选择绝缘体上硅(SOI)晶圆(在体硅基板上具有薄的氧化物层并且在氧化物上具有薄的硅层)。在SOI晶圆被用于制造中介层300的一种实施方式中，基板200可以由SOI晶圆的体硅基板提供。
如图3所示，在光子器件介电堆叠206内制造的一个或多个光子器件可以包括由波导材料层限定的波导214。在一种实施方式中，可以通过以下来制造波导214：沉积材料形成波导材料层，进行掩蔽和刻蚀以去除波导材料层的不需要的区域并且在波导材料层的剩余部分上沉积介电层。限定波导214的波导材料层可以包括例如单晶硅、多晶硅、非晶硅、氮化硅或氧化硅。在一种实施方式中，光子器件介电堆叠206可以被制造成包括在基板200之上且与基板200隔开的高度处的绝缘体介面上的硅。例如，基板200的顶部高度上方的厚的硅层，其例如在由硅形成的基板200上外延生长，可以通过以下而经受隔离：局部或非局部注入氧(SIMOX)处理以限定薄的硅层和在薄的硅层之下的隐埋氧化物层。
在如图3所示的光子器件介电堆叠206内的由不同材料制成的波导可以用于实现不同功能。例如，可以选择由硅形成的波导来制造包括在诸如光电探测器或调制器之类的有源器件中的波导。介电波导(例如由氮化硅形成)可以适用于将光信号传输到更远的距离。可以选择其他材料，诸如非晶硅，以用于强调电流传导特性与光传导特性的平衡的应用。对波导进行图案化可以包括：对限定波导的材料进行图案化，以及对波导周围的具有与构成波导的材料的折射指数不同的折射指数的材料进行图案化。对波导210和波导214进行图案化可以包括：进行图案化以限定不同的可替代几何形状。
利用适当的制造方法，可以在光子器件介电堆叠206的任何高度处制造由不同波导材料制成的波导提供的光子器件或者具有由不同波导材料构成的波导的光子器件。在一种实施方式中，外延生长的光子器件可以在光子器件介电堆叠206的基板上制造，并且由沉积的材料形成的光子器件，例如由沉积的氮化硅或氮氧化硅形成的光子器件，可以在光子器件介电堆叠206的上部基板高度处形成。光子器件介电堆叠206可以被制造成通过在不同高度处的波导之间的倏逝耦合来在各种高度之间传导光。
可以执行各种处理来修改可以制造各种光子器件的材料层的晶粒结构。在一种实施方式中，材料层可以由多晶的硅(多晶硅)形成。在一种实施方式中，可以执行离子注入以修改材料层的硅晶体结构。通过修改，多晶硅材料可以转变为非晶态多晶硅材料。离子注入种类可以包括硅、氩(例如Ar或Ar+)、氙(例如Xe或Xe+)或锗中的一者或多者。在另一方面，可以执行退火处理，例如再结晶退火处理，以进一步改善材料层的晶粒结构。在一种实施方式中，无论有无离子注入，材料层都可以经受退火以修改晶粒结构。
为了增强成一体地形成在光子器件介电堆叠206中的光子器件的性能，光子器件介电堆叠206可以包括用于减少成一体地制造的光子器件与基板200之间的耦合的特征。在一种实施方式中，基板200可以包括在图3所示的结构的成一体地形成有光子器件的区域中的深沟槽分离特征。
在光子介电堆叠206内进行图案化的，还可以有金属化层220和金属化层222。还可以存在图案化的竖向延伸的过孔224，其在金属化层220与波导210之间提供电通信。还可以存在图案化的竖向延伸的过孔226，其在金属化层220与金属化层222之间提供电通信。关于光电探测器240，光电探测器240可以包括成型件230，所述成型件230可以由设置在沟槽例如锗填充沟槽中的光子敏感材料限定。光子敏感材料可以将光子转换成电子，并且相应的可以将基于光子的信号转换成基于电的信号。参照光电探测器240，由过孔224限定的传导路径可以用于将电压输入到波导210中。在成型件238的高度上方具有金属化层220的传导路径可以用于电信号检测，其中，电信号可以基于通过波导210传输的光子信号输出以由光电探测器240检测。
如本文所阐述的，光子器件介电堆叠206可以被图案化以限定一个或多个光子器件，使得在介电堆叠20内制造一个或多个光子器件。光子介电堆叠206的一个或多个层可以被图案化以限定一个或多个波导，例如，根据波导210和/或波导214，使得在介电堆叠206内成一体地制造一个或多个波导。光子器件介电堆叠206的一个或多个层可以被图案化以限定一个或多个光电探测器，例如根据光电探测器240，使得在介电堆叠206内成一体地制造一个或多个光电探测器。光子器件介电堆叠206的一个或多个层可以被图案化以限定一个或多个光栅耦合器，使得在介电堆叠206内成一体地制造一个或多个光栅耦合器。光子器件介电堆叠206的一个或多个层可以被图案化以限定一个或多个光栅耦合器，使得在介电堆叠206内成一体地制造一个或多个光栅耦合器。光子器件介电堆叠206的一个或多个层可以被图案化以限定一个或多个调制器，使得在介电堆叠206内成一体地制造一个或多个调制器。光子器件介电堆叠206的一个或多个层可以被图案化以限定一个或多个偏振器，使得在介电堆叠206内成一体地制造一个或多个偏振器。光子器件介电堆叠206的一个或多个层可以被图案化以限定一个或多个分离器，使得在介电堆叠206内成一体地制造一个或多个分离器。光子器件介电堆叠206的一个或多个层可以被图案化以限定一个或多个谐振器，使得在介电堆叠206内成一体地制造一个或多个谐振器。
金属化层220和金属化层222可以限定水平延伸线。由金属化层220和222限定的线可以水平地延伸穿过光子器件介电堆叠206的区域。金属化层220和222通常可以通过以下形成：将一个或多个中介层材料层沉积至相应的金属化层220和222的至少顶部高度处，进行刻蚀以限定用于容纳导电性材料的沟槽，用导电性材料填充空腔，并且然后平面化至相应的金属化层220和222的顶部高度。金属化层220和222通常还可以通过以下形成：沉积均匀厚度的金属化层，并且然后进行掩蔽和刻蚀以从不需要的区域去除层材料。金属化层220和222可以由金属或其他导电性材料形成。由金属化层222限定的水平延伸线可以电连接至一个或多个竖向延伸的过孔226，以竖向地和水平地将控制信号、逻辑信号和/或功率信号中的一者或多者分配至制造有一个或多个光子器件的光子器件介电堆叠206的不同区域。由金属化层220限定的水平延伸线可以电连接至竖向延伸的过孔226和/或竖向延伸的过孔224中的一个或多个，以在光子器件介电堆叠206的不同区域之间竖向地和水平地分配电控制信号、逻辑信号和/或功率信号中的一者或多者。由金属化层222限定的线可以电连接至竖向延伸的过孔226中的一个或多个，以在光子器件介电堆叠206的不同区域之间竖向地和水平地分配电控制信号、逻辑信号和/或功率信号中的一者或多者。
在图4中，示出了如参照图3的描述构建的光子结构，其与如参照图2的描述构建的中介层基础结构对准。参照图4，描述了氧化物键合热处理。可以利用低温氧化物熔融键合。低温氧化物熔融键合可以在较低的温度下进行，例如在300℃或更低的温度下进行。为了实现低温氧化物熔融键合，可以如图4所示的沉积由二氧化硅形成的介电层。可以在中介层基础介电堆叠126上沉积由二氧化硅形成的介电层302，并且可以在光子器件介电堆叠206上沉积由二氧化硅形成的介电层304。在沉积层302和304之前，可以对它们各自的下表面进行抛光，例如，使用化学机械平面化(chemical mechanical planarization,CMP)进行抛光，以限定平滑表面来促进高质量接触，从而促进范德瓦尔斯(van der waals)力的激活。在对它们进行沉积和平滑之后，层302和层304的表面可以被处理以限定适当的表面化学性质，来促进原子水平的两个层之间的键合。
参照图5，图5例示了在如图2所示的光子中介层基础结构与如图3所示的光子结构之间进行键合。在如图4中所示的使用低温氧化物熔融键合来对该结构进行键合时，相应的结构可以成一体地形成在一起，并且可以在中介层基础介电堆叠126与光子器件介电堆叠206之间限定键合层306。可以通过退火处理来完成对图2的基础中介层结构与图3的光子结构进行键合以及对介电层302和304的使用，所述退火处理用于对层302和304进行退火，以形成键合层306，在一种实施方式中，所述键合层可以被视为键合介电层，并且在一种实施方式中，所述键合层可以由低温氧化物熔融键合介电层提供。在一种实施方式中，基板100可以由体硅晶圆的基板提供，并且基板200可以由SOI晶圆的基板提供，并且在一种实施方式中，各个晶圆可以由300毫米的晶圆提供，诸如300毫米晶圆键合器之类的晶圆键合器可以用于完成如图5所例示的将基础中介层结构键合至光子结构。
如参照图5所述的键合可以在基础中介层基板100(其可以由体晶圆提供)和基板200(其可以由SOI晶圆基板提供)的厚度保持为它们的全厚度(例如具有约775微米的厚度)的情况下进行。因而，参照图5所阐述的键合能够以较低的晶圆破损风险进行，并且可以在不使用操作晶圆的情况下实施。
图6例示了在去除基板200之后的如图5所示的光电系统，用以限定具有基板100和中介层介电堆叠320的中介层300，该中介层介电堆叠320可以包括中介层基础介电堆叠126、键合层306和光子器件介电堆叠206。为了去除基板200，可以使用各种处理工艺。例如，可以通过使用可以在距光子器件介电堆叠206的顶部高度预定距离(例如约10微米)处停止的研磨工艺来消除基板200的大部分原始厚度。在基板200是由硅形成的情况下，剩余基板200的相对薄(例如10微米)的厚度部分。基板200的剩余部分可以例如经由反应离子刻蚀(RIE)来去除。反应离子刻蚀(RIE)可以选择性地对硅(在基板200由硅形成的情况下)进行，使得可以去除基板200的硅材料，而不会去除光子器件介电堆叠206的介电材料。
图7例示了在进行图案化以形成竖向延伸的贯穿过孔332和金属化层334之后的图6的光电系统。为了制造竖向延伸的贯穿过孔332和金属化层334，可以使用镶嵌制造工艺在光子器件介电堆叠206上形成介电层324。可以通过以下操作来在介电层324和光子器件介电堆叠206中形成沟槽特征：使用对例如特定介电、聚合物掩膜或下面的金属材料具有选择性的反应离子刻蚀(RIE)，使得通过反应离子刻蚀(RIE)去除材料以形成具有期望尺寸的特征。然后，可以用导电性材料(例如铜)填充所形成的沟槽，以形成竖向延伸的贯穿过孔332和金属化层334。可以完全地延伸穿过或者基本上完全地延伸穿过基板100的竖向延伸的贯穿过孔116可以被视为贯穿过孔，并且在基板100是由硅形成的情况下可以被视为穿硅孔(TSV)。可以完全地延伸穿过或者基本上完全地延伸穿过光子器件介电堆叠206的竖向延伸的贯穿过孔332可以被视为贯穿过孔，并且在光子器件介电堆叠206包括一个或多个基于氧化物的介电层的情况下可以被视为穿氧化物孔(through oxide via,TOV)。直径可以比贯穿过孔116或贯穿过孔332的直径小的过孔122、过孔224和过孔226可以被视为接触过孔，或者在它们开始且终止于介电堆叠126或206的高度内的高度处的情况下，它们被视为堆叠内过孔。
关于如图3所示的左侧贯穿过孔332，左侧贯穿过孔332可以延伸穿过键合层306，并且可以电连接至在中介层基础介电堆叠126中制造的金属化层140。关于如图3所示的左侧贯穿过孔332，左侧贯穿过孔332可以从在中介层基础介电堆叠126中制造的金属化层140延伸穿过键合层306、穿过光子器件介电堆叠206的多个层，并且可以终止于在光子器件介电堆叠206的顶层处制造的金属化层334处。左侧贯穿过孔332可以延伸穿过光子器件介电堆叠206的多个层。左侧贯穿过孔332可以延伸穿过光子器件介电堆叠206的多个层，并且从而可以延伸穿过在光子器件介电堆叠206的各种高度处制造的多个光子器件的顶部高度和底部高度，例如，穿过波导212、光电探测器240和波导210的顶部高度和底部高度。关于如图3所示的右侧贯穿过孔332，右侧贯穿过孔332可以从在光子器件介电堆叠206中制造的金属化层222延伸穿过光子器件介电堆叠206的多个层，并且可以终止于在光子器件介电堆叠206的顶层处制造的金属化层334处。在如图7所示的实施方式中，可以限定带(钩)连接的金属化层334可以提供从中介层300的背面(例如，如图7所示，限定在基板100之下的背面之下的区域)到限定在光子器件介电堆叠206内的任何器件的传导路径。
如图7的中间制造阶段视图所示，可以限定提供带(钩)连接的传导路径，使得来自中介层300的背面的输入电压可以通过由以下限定的传导路径输入到光电检测器240中：再分布层508(背面)，连接至延伸穿过基板100的贯穿过孔116，连接至延伸穿过光子器件介电堆叠206的相关联的竖向延伸的贯穿过孔332，连接至金属化层334(正面)，连接至竖向延伸的贯穿过孔332，连接至金属化层222，连接至过孔226，连接至金属化层220，所述金属化层220可以向光电检测器240提供输入电压。连接竖向延伸的贯穿过孔116与竖向延伸的贯穿过孔332的桥连接可以由以下提供：金属化层118，其连接至竖向延伸的贯穿过孔116，所述金属化层118连接至过孔122，所述过孔122连接至金属化层120，所述金属化层120连接至竖向延伸的贯穿过孔332。光电系统100可以包括这种桥连接中的多个桥连接，例如，在一种实施方式中，多个竖向延伸的贯穿过孔116中的各个贯穿过孔116可以包括相应的桥连接，每个相应的桥连接将竖向延伸的贯穿过孔116连接至延伸穿过光子器件介电堆叠206的相应的竖向延伸的贯穿过孔332。金属化层118、竖向延伸的过孔122和金属化层120可以与中介层基础介电堆叠126成一体地制造并限定。在贯穿过孔332延伸穿过一个或多个光子器件(例如，波导214、波导210或光电探测器240)的底部高度和顶部高度的情况下，如图7中所示，贯穿过孔332可以被视为光子结构贯穿过孔。
参照光子器件介电堆叠206，限定堆叠206的介电层可以包括不同的材料。例如，层202可以由如本文所阐述的起始SOI晶圆的热氧化层提供。可以选择光子器件介电堆叠206的介电层以优化波导性能，例如，在一种实施方式中，波导周围的覆层可以由硅烷氧化物提供。可以选择光子器件介电堆叠206的沉积在金属化层上的介电层以抵抗导电性材料的迁移。光子器件介电堆叠206的剩余层可以由如下材料形成：诸如正硅酸乙酯(TEOS)或其他适当的SiOx衍生物。
图8例示了在进行图案化以限定凸块下金属化成型件336之后的图7的光电系统10。由该实施方式中所示的焊盘提供的凸块下金属化成型件336可以通过如下工艺来制造：所述工艺包括沉积介电层326，并且进一步进行图案化以限定凸块下金属化成型件336。在图8描绘的阶段中，中介层介电堆叠320包括介电层326，在一种实施方式中，介电层326可以由TEOS形成。
图9例示了在附接集成电路芯片400之后的光电系统10，在一种实施方式中，所述集成电路芯片400可以由CMOS逻辑芯片提供。CMOS逻辑芯片400可以包括对应于如参照图8所阐述的金属化成型件336的凸块下金属化成型件。集成电路芯片400可以通过将集成电路芯片400倒装芯片键合至凸块下金属化成型件336而附接至凸块下金属化成型件336，所述成型件336可以使用介电层326来制造。可以通过在集成电路芯片400与介电层326之间的介面处施加环氧树脂底部填充物(未示出)来补充集成电路芯片400的附接。
图10例示了在附接操作晶圆420之后的如图9所示的光电系统10。操作晶圆420可以使用粘合层410附接至图9中所示的结构。粘合层410可以分布在集成电路芯片400周围以及介电层326上，如图10所示，并且操作晶圆420可以粘附至粘合层410。操作晶圆420允许：在基板100被薄化并且不再能够为支撑所附接的器件层提供结构完整性之后，在中介层300的背面上制造附加特征。参照图11进一步描述了一种实施方式中的制造工艺。粘合层410可以是永久粘合或临时粘合的。在粘合层410是永久粘合层410的情况下，粘合层410可以保持粘合至介电层326，直到完成如图1所示的制造的中介层300。
图11例示了如图10所示的光电系统10，其利用附加工艺来限定中介层背面特征。参照图11，可以去除基础中介层基板100的材料以露出竖向延伸的贯穿过孔116的一部分，该竖向延伸的贯穿过孔116在图11所描绘的露出之前终止于基板100内。可以例如通过以下操作来执行去除基板100的材料：研磨到指定最终高度上方的预定高度，并且然后可以使用反应离子刻蚀(RIE)来执行进一步的去除，所述反应离子刻蚀(RIE)对基板100的材料选择性地进行，使得选择性地去除基板100的材料。
图12例示了在沉积介电层502之后的如图11所示的光电系统10，在一种实施方式中，所述介电层502可以由TEOS形成。可以沉积介电层502，并且然后将所述介电层502平面化以限定平滑表面，如图12所示。
图13例示了在进一步进行图案化以制造导电性背面再分布层508之后的如图12所示的光电系统10。可以提供能够限定水平延伸的再分布布线的再分布层508，以分散(fanout)由竖向延伸的贯穿过孔116所限定的接触部。再分布层508可以通过使用镶嵌工艺来制造，例如，通过对介电层502的材料选择性的使用RIE来对介电层502进行刻蚀，以选择性地去除介电层502的材料，并且然后用限定再分布层508的导电性材料填充所限定的沟槽。参照图11-图13，基板100可以被研磨以露出贯穿过孔116的导电性材料，并且可执行附加的图案化以形成再分布层508(图13)。例如，在图12所示的阶段中，在对平面化至贯穿过孔116的底部高度的基板进行研磨之后，可以将介电层502沉积在基板100上，接着沉积再分布层508，进行掩蔽并刻蚀以去除再分布层508的不需要的材料，以限定再分布层布线。在一种实施方式中，可以应用光刻胶模版并填充导电性材料，以形成再分布层508。
图14例示了在进行以下操作之后的如图13所示的光电系统10，所述操作为：对可以是介电钝化层的介电层504进行沉积，并且然后对介电层504进行图案化以限定沟槽而暴露再分布层508，用于准备并且促进凸块下金属化焊盘的选择性应用。参照图14，例示了沉积介电层504，然后使该介电层504在用于容纳由如图15所示的凸块下金属化焊盘提供的凸块下金属化成型件的区域中凹陷。
图15例示了在以下操作之后的如图14所示的光电系统10，所述操作为：进一步进行图案化，以限定具体是在介电层504的暴露区域中的凸块下金属化成型件510，以提供至再分布层508的电连接。在制造凸块下金属化成型件510时，可以在相应的凸块下金属化成型件510内形成焊料凸块512。
为了制造如图1所示的制造的中介层300，可以相对于光子结构(图3)单独地制造中介层基础结构(图2)。可以使用具有第一基板100的第一晶圆来制造中介层基础结构，并且可以使用具有第二基板200的第二晶圆来制造光子结构(图3)。在单独地制造了中介层基础结构(图2)和光子结构(图3)之后，可以使用低温氧化物熔融键合工艺来将两个晶圆构建的结构键合在一起。在执行低温氧化物键合工艺时，可以在中介层基础结构与光子结构之间限定键合层306，并且在一种实施方式中，具体地是在中介层基础介电堆叠126与光子器件介电堆叠206之间限定键合层306。在进一步的制造工艺之后所产生的如图1中所示的所产生的中介层300的特征可以为：背面至正面的电连接，例如，由延伸穿过基础中介层基板100的贯穿过孔116与延伸穿过光子器件介电堆叠206的相应的贯穿过孔332相关联而提供。
具有中介层300的如图1所示的光电系统10可以连接至下层结构，例如通过中介层300的焊料凸块512连接至下层结构(未示出)的UBM成型件。可以与图1的光电系统10附接的下层结构可以通过例如印刷电路板来提供，或者可以替代地例如通过球栅阵列或中介层来提供。
在替代实施方式中，中介层300可以完全地使用单个晶圆来制造。例如，可以制造具有如图2所示的中介层基础结构的部件的结构。然后，可以在如图2所示的结构的顶部上构建具有一个或多个光子器件部件的结构。最后，可以制造大规模贯穿过孔来延伸穿过具有光子特征(例如一个或多个光子器件)的中介层，以提供背面至正面的电连接。虽然所描述的替代方法可以具有优点，但是本文中的实施方式认识到所描述的替代实施方式的方法存在问题。例如，预期到根据替代实施方式将延伸穿过基础中介层基板(诸如基础100)并穿过光子器件的高度的大规模贯穿过孔将会消耗光子器件构建区域的大量基板面，从而限制能够制造的光子器件的数量和尺寸。
在本文参照图1所阐述的一个方面中，竖向延伸的贯穿过孔332(其可以提供为光子结构贯穿过孔)的尺寸可以是具有某种比例关系的，在一种实施方式中，该尺寸为延伸穿过基础中介层基板100的对应的竖向延伸的贯穿过孔116的尺寸的一小部分。在一种实施方式中，竖向延伸的贯穿过孔332(其可以提供为光子结构贯穿过孔)的尺寸可以是具有某种比例关系的，该尺寸为延伸穿过基础中介层基板100的对应的贯穿过孔116的尺寸的0.5或者更小。在一种实施方式中，竖向延伸的贯穿过孔332(其可以提供为光子结构贯穿过孔)的尺寸可以是具有某种比例关系的，该尺寸为延伸穿过基础中介层基板100的对应的贯穿过孔116的尺寸的0.25或者更小。在一种实施方式中，竖向延伸的贯穿过孔332(其可以提供为光子结构的贯穿过孔)的尺寸可以是具有某种比例关系的，该尺寸为延伸穿过基础中介层基板100的对应的贯穿过孔116的尺寸的0.10或更者更小。在本段中以上阐述的尺寸是指直径、高或体积中的一者或多者。
在一个示例中，贯穿过孔332可以具有约1.0微米直径乘以7.0微米高的尺寸，并且贯穿过孔116可以具有约10微米直径乘以100微米高的尺寸。在一种实施方式中，竖向延伸的贯穿过孔116和竖向延伸的贯穿过孔332的尺寸可以是不同的，但是可以具有共同的纵横比，例如，各自可以具有10x1的纵横比，例如，竖向延伸的贯穿过孔332可以被设计为约0.7微米x 7.0微米的尺寸，并且竖向延伸的贯穿过孔116可以被设计为约10.0微米x 100微米的尺寸。将贯穿过孔332的尺寸设置得更小促进在光子器件介电堆叠206内制造附加的和更大规模的光子器件。设置贯穿过孔332而不是诸如过孔226之类的接触过孔来承载控制信号、逻辑信号和/或功率信号中的一者或多者，可以帮助避免各种电气问题，诸如涉及不期望的压降和杂散电容生成。
本文所阐述的制造方法可以促进提供具有不同的基板的成组的中介层300。使用本文的方法，可以制造具有由第一材料制成的基板的第一组一个或多个中介层，并且可以制造具有基板的第二组一个或多个中介层。本文阐述了：在限定第一基板的第一晶圆上构建中介层基础结构；在限定第二基板的第二晶圆上构建光子结构；并且将光子结构键合至中介层基础结构来限定具有中介层基础结构和在光子器件介电堆叠内制造的一个或多个光子器件的中介层。在一种实施方式中，可以修改该方法，使得可以重复构建中介层基础结构，以使用第二个第一晶圆来构建第二基础结构，所述第二个第一晶圆具有由不同于第一晶圆的基板材料的材料构成的基板。可以通过重复构建光子结构，以使用另外的第二晶圆来构建第二光子结构来进一步修改所述方法。通过将第二光子结构键合至第二基础中介层结构可以进一步修改所述方法。
本文中使用的术语仅用于描述特定实施方式，并且不旨在是限制性的。除非上下文另有明确指示，否则如本文所使用的，单数形式“一”、“一种”和“该”旨在也包括复数形式。进一步将理解，术语“包括(comprise)”(以及包括的任何形式，诸如“包括有”和“包括了”)、“具有(have)”(以及具有的任何形式，诸如“具”和“有”)、“包含(include)”(以及包含的任何形式，诸如“包含有”和“包含了”)和“含有(contain)”(以及含有的任何形式，诸如“含”和“包含”)是开放式的连缀动词。因此，“包括”、“具有”、“包含”或“含有”一个或多个步骤或者元素的方法或器件拥有该一个或多个步骤或元素，但是不限于仅拥有该一个或多个步骤或元素。类似地，“包括”、“具有”、“包含”或“含有”一个或多个特征的器件的元素或方法的步骤拥有该一个或多个特征，但是不限于仅拥有该一个或多个特征。术语“由…限定”的形式涵盖元素部分地由…限定的关系以及元素完全地由…限定的关系。本文的数字标识符例如“第一”和“第二”是任意性术语，用于指定不同的元素，而不指定元素的顺序。此外，以某种方式配置的系统方法或设备至少以该方式进行配置，但是也能够以未列出的方式进行配置。此外，被阐述为具有特定数量的元素的系统方法或设备能够以比所述特定数量更少或者更多数量的元素来进行实施。
在随附权利要求书中的对应的结构、材料、动作和所有方法或步骤加功能元素的等效物(如果有的话)旨在包括：用于与如具体要求保护的其他要求保护的元素相结合来执行功能的任何结构、材料或动作。本发明的描述是为了说明和描述的目的而提出的，但是不旨在是穷尽性的或者将本发明限制为所公开的形式。在不脱离本发明的范围和精神的情况下，许多修改和变型对于本领域的普通技术人员将会是显而易见的。选择并描述的实施方式是为了最好地解释本发明的一个或多个方面的理念和实际应用，以及使本领域的其他普通技术人员能够理解本发明的一个或多个方面，以针对各种实施方式进行对于所考虑的特定用途适用的各种修改。

Claims (30)

1.一种方法，所述方法包括：
在具有第一基板的第一晶圆上构建中介层基础结构，其中，构建中介层基础结构包括：制造延伸穿过所述第一基板的多个贯穿过孔，以及在形成于所述第一基板上的中介层基础介电堆叠内制造一个或多个金属化层；
在具有第二基板的第二晶圆上构建光子结构，其中，构建光子结构包括：在形成于所述第二基板上的光子器件介电堆叠内制造一个或多个光子器件；以及
将所述光子结构键合至所述中介层基础结构以限定中介层，所述中介层具有所述中介层基础结构和在所述光子器件介电堆叠内制造的一个或多个光子器件。
2.根据权利要求1所述的方法，其中，所述键合包括：使用低温氧化物键合工艺。
3.根据权利要求1所述的方法，其中，所述键合包括：使用低温氧化物熔融键合工艺，所述低温氧化物熔融键合工艺包括抛光阶段、激活阶段和退火阶段。
4.根据权利要求1所述的方法，其中，所述第一晶圆是具有半导体特性或绝缘特性的晶圆。
5.根据权利要求1所述的方法，其中，所述第二晶圆是绝缘体上硅(SOI)晶圆。
6.根据权利要求1所述的方法，其中，所述第一晶圆是体硅晶圆，并且其中，所述第二晶圆是SOI晶圆。
7.根据权利要求1所述的方法，其中，所述方法包括：在进行键合之后，从所述第一基板去除材料以露出所述多个贯穿过孔中的贯穿过孔，使得所述贯穿过孔完全地延伸穿过所述第一基板。
8.根据权利要求1所述的方法，其中，制造延伸穿过所述第一基板的多个贯穿过孔包括：执行所述制造，使得所述多个贯穿过孔中的贯穿过孔在所述第一基板内延伸至一定深度，从而使得在执行去除所述第一基板的材料以露出所述多个贯穿过孔时，所述贯穿过孔完全地延伸穿过所述第一基板。
9.根据权利要求1所述的方法，其中，在第二晶圆上构建光子结构包括：在光子器件介电堆叠内制造一个或多个光子器件，所述一个或多个光子器件选自由波导和光电探测器组成的组。
10.根据权利要求1所述的方法，其中，在第二晶圆上构建光子结构包括：在光子器件内制造由第一材料构成的第一波导和由第二材料构成的第二波导。
11.根据权利要求1所述的方法，其中，在第二晶圆上构建光子结构包括：在光子器件介电堆叠内制造一个或多个光子器件，所述一个或多个光子器件选自由波导、光电探测器、光栅耦合器、调制器、偏振器、分离器和谐振器组成的组。
12.根据权利要求1所述的方法，其中，在第二晶圆上构建光子结构包括：在光子器件介电堆叠内制造由第一材料构成的第一波导和由第二材料构成的第二波导，其中，在第二晶圆上构建光子结构包括：在光子器件介电堆叠内在第一高度处制造所述第一波导、并且在第二高度处制造所述第二波导。
13.根据权利要求1所述的方法，其中，所述方法包括：形成穿过所述光子器件介电堆叠的多个光子结构贯穿过孔。
14.根据权利要求1所述的方法，其中，所述方法包括：形成穿过所述光子器件介电堆叠的多个光子结构贯穿过孔，以及使用相应的桥连接将所述多个光子结构贯穿过孔中的光子结构贯穿过孔连接至所述多个贯穿过孔中的贯穿过孔，所述相应的桥连接具有在所述中介层基础介电堆叠内限定的特征。
15.根据权利要求1所述的方法，其中，在第二晶圆上构建光子结构包括：在光子器件介电堆叠内制造由第一材料构成的第一波导和由第二材料构成的第二波导，其中，在第二晶圆上构建光子结构包括：在光子器件介电堆叠内在第一高度处制造所述第一波导、并且在第二高度处制造所述第二波导，并且其中，所述在第二晶圆上构建光子结构包括：在所述光子器件介电堆叠内制造包括光敏材料的光电探测器。
16.根据权利要求1所述的方法，其中，所述方法包括：重复进行在第一晶圆上构建中介层基础结构，以使用第二个第一晶圆来构建第二中介层基础结构，所述第二个第一晶圆具有由与所述第一晶圆的基板材料不同的材料构成的基板；重复进行构建光子结构以使用另外的第二晶圆来构建第二光子结构；以及将所述第二光子结构键合至所述第二中介层基础结构。
17.一种光电系统，所述光电系统包括：
基板；
中介层介电堆叠，所述中介层介电堆叠形成在所述基板上，所述中介层介电堆叠包括：基础中介层介电堆叠、光子器件介电堆叠和键合层，所述键合层将所述光子器件介电堆叠成一体地键合至所述基础中介层介电堆叠；
一个或多个贯穿过孔，所述一个或多个贯穿过孔延伸穿过所述基板；
一个或多个金属化层，所述一个或多个金属化层被制造在所述基础中介层介电堆叠中；以及
一个或多个光子器件，所述一个或多个光子器件被制造在所述光子器件介电堆叠中。
18.根据权利要求17所述的光电系统，其中，所述一个或多个光子器件包括波导。
19.根据权利要求17所述的光电系统，其中，所述一个或多个光子器件包括光电探测器。
20.根据权利要求17所述的光电系统，其中，所述一个或多个光子器件包括由第一材料形成的第一波导和由第二材料形成的第二波导。
21.根据权利要求17所述的光电系统，其中，所述一个或多个光子器件包括：在第一高度处形成的第一波导，在第二高度处形成的第二波导。
22.根据权利要求17所述的光电系统，其中，所述一个或多个光子器件包括：在第一高度处由第一材料形成的第一波导，和在第二高度处由第二材料形成的第二波导。
23.根据权利要求17所述的光电系统，其中，所述基板是由半导体基板或绝缘基板形成的。
24.根据权利要求17所述的光电系统，其中，所述光电系统包括形成在所述基板上的背面金属再分布层。
25.根据权利要求17所述的光电系统，其中，所述光电系统包括在所述光子介电堆叠的高度上方形成的正面成型件，所述正面成型件容纳CMOS逻辑集成电路芯片。
26.根据权利要求17所述的光电系统，其中，所述光电系统包括在所述中介层的背面上形成的背面成型件，所述背面成型件便利于将所述中介层焊接键合至下层结构，所述下层结构选自由球栅阵列、印刷电路板和中介层组成的组。
27.根据权利要求17所述的光电系统，其中，所述光电系统包括提供带式连接的传导路径，所述带式连接由包括再分布层的传导路径限定，所述再分布层连接至延伸穿过所述基板的贯穿过孔，所述贯穿过孔连接至延伸穿过所述光子器件介电堆叠的相关联的第一竖向延伸的光子结构贯穿过孔，所述第一竖向延伸的光子结构贯穿过孔连接至第一金属化层，所述第一金属化层连接至第二竖向延伸的光子结构贯穿过孔，所述第二竖向延伸的光子结构贯穿过孔连接至第二金属化层，其中，所述第二金属化层位于比所述第一金属化层低的高度处。
28.根据权利要求17所述的光电系统，其中，所述一个或多个贯穿过孔中的贯穿过孔连接至相关联的竖向延伸的光子结构贯穿过孔，所述竖向延伸的光子结构贯穿过孔延伸穿过所述光子器件介电堆叠。
29.根据权利要求17所述的光电系统，其中，所述一个或多个贯穿过孔中的贯穿过孔通过桥连接而连接至相关联的竖向延伸的光子结构贯穿过孔，所述竖向延伸的光子结构贯穿过孔延伸穿过所述光子器件介电堆叠。
30.根据权利要求17所述的光电系统，其中，所述一个或多个贯穿过孔中的贯穿过孔通过桥连接而连接至相关联的竖向延伸的光子结构贯穿过孔，所述竖向延伸的光子结构贯穿过孔延伸穿过所述光子器件介电堆叠，所述桥连接具有在所述基础中介层介电堆叠中制造的特征，并且其中，所述竖向延伸的光子结构贯穿过孔的尺寸为所述贯穿过孔的尺寸的0.5倍或更小。
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