CN108461411B - 封装结构 - Google Patents

封装结构 Download PDF

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Publication number
CN108461411B
CN108461411B CN201710092831.XA CN201710092831A CN108461411B CN 108461411 B CN108461411 B CN 108461411B CN 201710092831 A CN201710092831 A CN 201710092831A CN 108461411 B CN108461411 B CN 108461411B
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polymer layer
opening
top surface
layer
package structure
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CN108461411A (zh
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刘臻衡
张永富
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Winbond Electronics Corp
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Winbond Electronics Corp
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Priority to CN201710092831.XA priority Critical patent/CN108461411B/zh
Priority to US15/853,979 priority patent/US10366941B2/en
Publication of CN108461411A publication Critical patent/CN108461411A/zh
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Abstract

本发明提供一种封装结构，包括：基底、金属垫、第一聚合物层、第二聚合物层、重分布层以及第三聚合物层。金属垫位于基底上。第一聚合物层位于基底上。第一聚合物层具有第一开口。第一开口暴露出所述金属垫的部分顶面。第二聚合物层位于第一聚合物层上。第二聚合物层具有第二开口。第二开口暴露出金属垫的部分顶面以及第一聚合物层的第一顶面。重分布层覆盖金属垫的部分顶面上，并延伸至第一聚合物层的部分第一顶面上以及第二聚合物层上。第三聚合物层位于重分布层上。

Description

封装结构
技术领域
本发明涉及一种半导体结构，尤其涉及一种封装结构。
背景技术
近年来，由于各种电子构件(例如晶体管、二极管、电阻器、电容器等)的积集度不断提升，半导体工业因而快速成长。这种集成度的提升，大多是因为最小特征尺寸的持续缩小，使得更多的构件整合在一特定的区域中。
相较于先前的封装结构，这些尺寸较小的电子构件具有较小的面积，因而需要较小的封装结构。举例来说，半导体芯片(semiconductor chip)或晶粒(die)具有越来越多的输入/输出(I/O)焊垫，重分布层(redistribution layer，RDL)可将半导体芯片或晶粒的原始I/O焊垫的位置重新布局于半导体芯片或晶粒的周围。然后，通过打线接合或是覆晶接合的方式，将RDL焊垫与导线架(leadframe)或是线路板电性连接。
一般而言，在进行RDL处理后，原始输入/输出(I/O)垫会外露于聚酰亚胺层，以便进行芯片探针测试(chip probing，CP)，以下称为测试焊垫。但所述测试焊垫在经过RDL处理后，其开口会缩小，进而影响RDL后的芯片探针测试良率。
发明内容
本发明提供一种封装结构，其可增加测试焊垫的平坦部的宽度，以提升芯片探针测试良率。
本发明提供一种封装结构，包括：基底、金属垫、第一聚合物层、第二聚合物层以及重分布层。金属垫位于基底上。第一聚合物层位于基底上。第一聚合物层具有第一开口。第一开口暴露出所述金属垫的部分顶面。第二聚合物层位于第一聚合物层上。第二聚合物层具有第二开口。第二开口暴露出金属垫的部分顶面以及第一聚合物层的第一顶面。重分布层覆盖金属垫的部分顶面上，并延伸至第一聚合物层的部分第一顶面上以及第二聚合物层上。
在本发明的一实施例中，所述封装结构还包括钝化层，位于所述基底与所述第一聚合物层之间。
在本发明的一实施例中，所述封装结构还包括第三聚合物层位于重分布层上。第三聚合物层具有第三开口。第三开口暴露出重分布层的部分顶面。
在本发明的一实施例中，所述第二开口大于所述第一开口。
在本发明的一实施例中，所述重分布层直接接触所述第一聚合物层的所述部分第一顶面。
在本发明的一实施例中，所述重分布层包括对应于所述金属垫的测试焊垫。所述测试焊垫平坦部与延伸部。平坦部位于所述第一开口的底面。延伸部从所述平坦部的一侧延伸至所述第一开口的侧壁与所述第一聚合物层的所述部分第一顶面。
在本发明的一实施例中，所述延伸部的底面与侧壁之间的夹角介于10度至90度之间。
在本发明的一实施例中，所述平坦部的宽度介于15微米至70微米之间。
在本发明的一实施例中，所述延伸部的数量为两个，所述两个延伸部从所述平坦部的两侧分别延伸至所述第一开口的所述两侧壁与所述第一聚合物层的所述部分第一顶面。
在本发明的一实施例中，所述基底具有第一区与第二区。金属垫位于第一区的基底上。第一聚合物层、第二聚合物层以及重分布层依序位于第一区与第二区的基底上。重分布层自金属垫的部分顶面上延伸至第一聚合物层的部分第一顶面上以及第二区的第二聚合物层上。
在本发明的一实施例中，所述封装结构还包括第三聚合物层位于重分布层上。第三聚合物层具有第三开口与第四开口。第三开口暴露出第一区的重分布层的部分顶面。第四开口暴露出第二区的重分布层的部分顶面。
在本发明的一实施例中，所述第三开口对应于所述金属垫，以进行芯片探针测试。
在本发明的一实施例中，所述封装结构还包括熔丝结构位于所述第一区与所述第二区之间的所述基底中。
基于上述，本发明通过减少测试焊垫的延伸部下方的聚合物层的厚度，以增加测试焊垫的平坦部的宽度。相较于现有的芯片探针测试区域，本发明具有较大的芯片探针测试区域，其可增加下针时的操作裕度，并进而提升芯片探针测试良率。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1是依照本发明的一实施例的一种封装结构的上视图；
图2A是依照本发明的第一实施例的一种封装结构的第三聚合物层的平面图；
图2B是图2A的剖面示意图；
图2C是图2B的封装结构的部分放大图；
图3A是依照本发明的第二实施例的一种封装结构的第一聚合物层的平面图；
图3B是图3A的剖面示意图；
图4是依照本发明的第三实施例的一种封装结构的剖面示意图。
具体实施方式
参照本实施例的附图以更全面地阐述本发明。然而，本发明也可以各种不同的形式体现，而不应限于本文中所述的实施例。附图中的层与区域的厚度会为了清楚起见而放大。相同或相似的标号表示相同或相似的元件，以下段落将不再一一赘述。
图1是依照本发明的一实施例的一种封装结构的上视图。为图面清楚起见，在图1中仅显示出基底、测试焊垫、RDL焊垫以及迹线。
请参照图1，测试焊垫109可通过迹线(trace)113与RDL焊垫111电性连接。在一实施例中，由图1可知，测试焊垫109可位于基底100(或整个封装结构)的中心，而RDL焊垫111则位于基底100的两侧。但本发明不以此为限，在其他实施例中，测试焊垫109也可位于基底100的两侧或一侧。只要具有测试焊垫109的区域(例如图2B的第一区R1)与具有RDL焊垫111的区域(例如图2B的第二区R2)相距一距离，即为本发明的范畴。在一些实施例中，测试焊垫109(或RDL焊垫111)与迹线113可位于相同层。在替代实施例中，测试焊垫109(或RDL焊垫111)与迹线113可位于不同层。
图2A是依照本发明的第一实施例的一种封装结构的第三聚合物层的平面图。图2B是图2A的剖面示意图。图2C是图2B的封装结构的部分放大图。
请参照图2A与图2B，第一实施例的封装结构包括：基底100、金属垫102、钝化层104、第一聚合物层106、第二聚合物层108、重分布层110以及第三聚合物层112。在本实施例中，所述封装结构可以是一种封装的半导体芯片，其可通过凸块或是打线以与其他基板、芯片等接合。
详细地说，基底100具有第一区R1与第二区R2。第一区R1与第二区R2相距一距离，所述距离可依设计需求来调整。在一实施例中，第一区R1具有测试焊垫109，其可用以进行芯片探针测试(CP)。在另一实施例中，第二区R2具有RDL焊垫111，其可通过打线接合或是覆晶接合的方式电性连接至外部构件(例如是导线架或是其他线路板等)。第一区R1的测试焊垫109通过迹线(trace)113与第二区R2的RDL焊垫111电性连接。在一实施例中，基底100包括半导体材料、绝缘体材料、导体材料或上述材料的任意组合，且基底100包括单层结构或多层结构。举例来说，基底100可由选自于Si、Ge、SiGe、GaP、GaAs、SiC、SiGeC、InAs与InP所组成的族群中的至少一种半导体材料形成。此外，也可使用绝缘体上硅(silicon oninsulator，SOI)基底。基底100可由多层材料组成，例如Si/SiGe、Si/SiC。但基底100的材料并不以此为限。在一实施例中，基底100可具有半导体元件于其中，例如逻辑元件、存储元件或其组合。
金属垫102位于第一区R1的基底100上。金属垫102的材料包括金属材料。所述金属材料可例如是铜、铝、金、银、镍、钯或其组合。虽然图2A与图2B中仅显示一个金属垫102，但本发明不限于此。在其他实施例中，金属垫102的数量可依需求来调整。在一实施例中，金属垫102可与基底100中的半导体元件(未显示)电性连接。
钝化层104与第一聚合物层106依序形成于第一区R1与第二区R2的基底100上，使得钝化层104位于基底100与第一聚合物层106之间。钝化层104的材料包括氮化硅，其厚度可介于3微米(μm)至10μm之间。第一聚合物层106的材料包括聚酰亚胺(polyimide，PI)、苯并环丁烯(benzocyclobutene，BCB)、聚苯并恶唑(polybenzooxazole，PBO)或任何其他适合的材料。第一聚合物层106的厚度可介于3μm至10μm之间。在一实施例中，第一聚合物层106可保护基底100或是钝化层104的表面并降低基底100或是钝化层104的应力。
第一聚合物层106具有第一开口O1。第一开口O1暴露出金属垫102的部分顶面102a。在一实施例中，经暴露的金属垫102的部分顶面102a的宽度A可介于30μm至100μm之间。
第二聚合物层108位于第一聚合物层106上。第二聚合物层108具有第二开口O2。第二开口O2暴露出金属垫102的部分顶面102a以及第一聚合物层106的顶面106a、顶面106b、顶面106c。在一实施例中，第二开口O2大于第一开口O1。如图2B所示，第二开口O2位于第一开口O1上且第二开口O2与第一开口O1连通，以形成一上宽下窄的开口。所述上宽下窄的开口的侧壁为阶梯状侧壁。在一实施例中，第二聚合物层108的材料包括聚酰亚胺、苯并环丁烯、聚苯并恶唑或任何其他适合的材料。第二聚合物层108的厚度可介于3μm至10μm之间。在一实施例中，第二聚合物层108可使得其下方的导电层(如图4的熔丝结构114)与后续形成的重分布层110电性绝缘，以避免电性短路。在替代实施例中，第二聚合物层108可用以当作缓冲层(buffer layer)，以增加第一聚合物层106与后续形成的重分布层110的附着力。
重分布层110覆盖金属垫102的部分顶面102a上，并延伸至第一聚合物层106的部分顶面106a、顶面106b上以及第二聚合物层108上。换言之，重分布层110共形地形成在所述阶梯状侧壁上，并延伸至第二区R2。在一实施例中，重分布层110直接接触金属垫102的部分顶面102a，且直接接触第一聚合物层106的一部分顶面106a、顶面106b，而未接触第一聚合物层106的另一部分顶面106c。如图2B所示，对应于金属垫102的部分重分布层110可视为测试焊垫109；外露于后续形成的第四开口O4的部分重分布层110可视为RDL焊垫111；测试焊垫109与RDL焊垫111之间的部分重分布层110可视为迹线113。迹线113自第一区R1延伸至第二区R2，以电性连接第一区R1的测试焊垫109与第二区R2的RDL焊垫111。因此，本实施例可通过迹线113将第一区R1的测试焊垫109重新配置到第二区R2的RDL焊垫111，再通过打线接合或是覆晶接合的方式，将RDL焊垫111电性连接至外部构件(例如是导线架或是其他线路板等)。在一实施例中，重分布层110可包括金属材料。所述金属材料可例如是铜、铝、金、银、镍、钯或其组合。
第三聚合物层112位于重分布层110上，且覆盖重分布层110与第二聚合物层108的侧壁。第三聚合物层112具有第三开口O3与第四开口O4。第三开口O3对应于金属垫102且暴露出第一区R1的测试焊垫109的顶面。第四开口O4暴露出第二区R2的RDL焊垫111的顶面。在一实施例中，第三聚合物层112的材料包括聚酰亚胺、苯并环丁烯、聚苯并恶唑或任何其他适合的材料。第三聚合物层112的厚度可介于3μm至10μm之间。在一些实施例中，第一聚合物层106、第二聚合物层108以及第三聚合物层112的材料可彼此不同。在替代实施例中，第一聚合物层106、第二聚合物层108以及第三聚合物层112的材料可以相同。在一实施例中，第三开口O3的宽度C可介于35μm至150μm之间；第四开口O4的宽度D可介于30μm至150μm之间。另外，第一实施例的封装结构还包括密封环(seal ring)120，其配置在基底100的侧壁。
请参照图2C，测试焊垫109(部分重分布层110)包括平坦部109a与两个延伸部109b。平坦部109a位于第一开口O1的底面。两个延伸部109b的一个从平坦部109a的一侧延伸至第一开口O1的一侧壁、第一聚合物层106的部分顶面106a以及第二聚合物层108的侧壁与顶面。另一方面，两个延伸部109b的另一个从平坦部109a的另一侧延伸至第一开口O1的另一侧壁与第一聚合物层106的部分顶面106b，且未延伸至第一聚合物层106的部分顶面106c。两个延伸部109b的另一个与第二开口O2(或第二聚合物层108)之间具有一空隙，使得第三聚合物层112可填入所述空隙中。也就是说，部分第三聚合物层112位于两个延伸部109b的另一个与第二聚合物层108之间。但本发明不以此为限，在替代实施例中，测试焊垫109’(如图4所示)也可具有单侧的延伸部109b。单侧的延伸部109b连接平坦部109a的一侧，并延伸至第二区R2的第二聚合物层108上。
值得注意的是，如图2B与图2C所示，本实施例可省略延伸部109b下方的第二聚合物层108，其使得延伸部109b下方的钝化层104与第一聚合物层106的总和厚度T介于6μm至15μm之间，并使得延伸部109b的底面与侧壁之间的夹角θ介于10度至90度之间。另外，延伸部109b直接接触第一聚合物层106的侧壁与部分顶面106a、顶面106b，其可增加平坦部109a与金属垫102之间的接触面积。所述接触面积可视为芯片探针测试区域，也就是说，在所述区域中进行芯片探针测试，其不会因为接触不良而导致测试失败。因此，相较于现有的芯片探针测试区域，本发明具有较大的芯片探针测试区域，其可增加下针时的操作裕度，进而提升芯片探针测试良率。在一实施例中，平坦部109a的宽度B(也即芯片探针测试区域)可介于15μm至90μm之间。在替代实施例中，平坦部109a的宽度B与金属垫102的宽度A之间的比值(也即B/A)介于15：30至90：100之间。
图3A是依照本发明的第二实施例的一种封装结构的第一聚合物层的平面图。图3B是图3A的剖面示意图。
请参照图3A与图3B，基本上第二实施例的封装结构与第一实施例的封装结构相似，其不同之处在于：第二实施例的封装结构包括熔丝结构114。熔丝结构114位于第一区R1与第二区R2之间的基底100中。具体来说，如图3B所示，钝化层104与第一聚合物层106中具有第五开口O5。第五开口O5对应熔丝结构114且暴露出熔丝结构114的表面。而后续形成的第二聚合物层108填入第五开口O5中，以与熔丝结构114接触。在一实施例中，第二聚合物层108可电性绝缘熔丝结构114(或是其他导电层)与迹线113(也即部分重分布层110)，以避免电性短路。在一实施例中，熔丝结构114可用以进行熔丝修复(fuse repair)。举例来说，当基底100中具有存储元件时(以下称为存储器芯片)，存储器芯片通常包括预设的过量存储胞(pre-designed excess memory cells)。对所述存储器芯片进行芯片探针测试时，可量测出可用的(functional)存储胞以及有缺陷的(defective)存储胞。因此，可利用激光烧熔所述存储器芯片中的熔丝结构，来分隔可用的存储胞以及有缺陷的存储胞，并以过量的存储胞取代有缺陷的存储胞。如此一来，所述存储器芯片便可维持预设的可用的存储胞数量。
图4是依照本发明的第三实施例的一种封装结构的剖面示意图。
请参照图4，基本上第三实施例的封装结构与第二实施例的封装结构相似，其不同之处在于：第三实施例的封装结构的测试焊垫109’只具有单侧的延伸部109b。也就是说，延伸部109b从平坦部109a的一侧延伸至第一聚合物层106的侧壁与部分顶面106a以及第二聚合物层108的侧壁与顶面。突出部109c可视为平坦部109a的一部分，其从平坦部109a的另一侧延伸至第三聚合物层112与钝化层104之间。突出部109c与第一聚合物层106之间具有一空隙，使得第三聚合物层112填入所述空隙中。在本实施例中，测试焊垫109’可位于封装结构(或芯片)的边缘部分，因此，测试焊垫109’不具有另一个延伸部。从图4可知，靠近突出部109c(也即封装结构的边缘部分)的一侧不具有第二聚合物层108。在一实施例中，延伸部109b具有相对于平坦部109a的顶面或底面的倾斜的侧壁；而突出部109c的顶面则与平坦部109a的顶面实质上共平面。
综上所述，本发明通过减少测试焊垫的延伸部下方的聚合物层的厚度，以增加测试焊垫的平坦部的宽度。相较于现有的芯片探针测试区域，本发明具有较大的芯片探针测试区域，其可增加下针时的操作裕度，并进而提升芯片探针测试良率。
虽然本发明已以实施例揭示如上，然其并非用以限定本发明，任何所属技术领域中技术人员，在不脱离本发明的精神和范围内，当可作些许的更改与润饰，故本发明的保护范围当视权利要求所界定的为准。

Claims (11)

1.一种封装结构，其特征在于，包括：
基底；
金属垫，位于所述基底上；
第一聚合物层，位于所述基底上，所述第一聚合物层具有第一开口，所述第一开口暴露出所述金属垫的部分顶面；
第二聚合物层，位于所述第一聚合物层上，所述第二聚合物层具有第二开口，所述第二开口暴露出所述金属垫的所述部分顶面以及所述第一聚合物层的第一顶面；
重分布层，覆盖所述金属垫的所述部分顶面上，并延伸至所述第一聚合物层的部分第一顶面上以及所述第二聚合物层上；以及
第三聚合物层，位于所述重分布层上，所述第三聚合物层具有第三开口，所述第三开口暴露出所述重分布层的部分顶面，其中所述第三开口对应于所述金属垫，并且所述第三开口比所述第二开口小，所述第三开口比所述第一开口大。
2.根据权利要求1所述的封装结构，其特征在于，还包括钝化层，位于所述基底与所述第一聚合物层之间。
3.根据权利要求1所述的封装结构，其特征在于，所述重分布层直接接触所述第一聚合物层的所述部分第一顶面，且所述重分布层未完全覆盖所述第二开口。
4.根据权利要求1所述的封装结构，其特征在于，所述重分布层包括对应于所述金属垫的测试焊垫，所述测试焊垫包括：
平坦部，位于所述第一开口的底面；以及
延伸部，从所述平坦部的一侧延伸至所述第一开口的侧壁与所述第一聚合物层的所述部分第一顶面。
5.根据权利要求4所述的封装结构，其特征在于，所述延伸部的底面与侧壁之间的夹角介于10度至90度之间。
6.根据权利要求4所述的封装结构，其特征在于，所述平坦部的宽度介于15微米至70微米之间。
7.根据权利要求4所述的封装结构，其特征在于，所述延伸部的数量为两个，所述两个延伸部从所述平坦部的两侧分别延伸至所述第一开口的所述两侧壁与所述第一聚合物层的所述部分第一顶面。
8.根据权利要求4所述的封装结构，其特征在于，所述基底具有第一区与第二区，
所述金属垫位于所述第一区的所述基底上，
所述第一聚合物层、所述第二聚合物层以及所述重分布层依序位于所述第一区与所述第二区的所述基底上，所述重分布层自所述金属垫的所述部分顶面上延伸至所述第一聚合物层的所述部分第一顶面上以及所述第二区的所述第二聚合物层上。
9.根据权利要求8所述的封装结构，其特征在于，还包括第三聚合物层位于所述重分布层上，所述第三聚合物层具有第三开口与第四开口，所述第三开口暴露出所述第一区的所述重分布层的部分顶面，所述第四开口暴露出所述第二区的所述重分布层的部分顶面。
10.根据权利要求9所述的封装结构，其特征在于，所述第三开口对应于所述金属垫，以进行芯片探针测试。
11.根据权利要求8所述的封装结构，其特征在于，还包括熔丝结构位于所述第一区与所述第二区之间的所述基底中。
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