TW200629438A - Chip structure with bumps and testing pads - Google Patents

Chip structure with bumps and testing pads

Info

Publication number
TW200629438A
TW200629438A TW094103006A TW94103006A TW200629438A TW 200629438 A TW200629438 A TW 200629438A TW 094103006 A TW094103006 A TW 094103006A TW 94103006 A TW94103006 A TW 94103006A TW 200629438 A TW200629438 A TW 200629438A
Authority
TW
Taiwan
Prior art keywords
layers
semiconductor substrate
bump
passivation layer
pad
Prior art date
Application number
TW094103006A
Other languages
Chinese (zh)
Other versions
TWI250598B (en
Inventor
Nick Kuo
Chiu-Ming Chou
Chien-Kang Chou
Chu-Fu Lin
Original Assignee
Megic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Megic Corp filed Critical Megic Corp
Priority to TW094103006A priority Critical patent/TWI250598B/en
Application granted granted Critical
Publication of TWI250598B publication Critical patent/TWI250598B/en
Publication of TW200629438A publication Critical patent/TW200629438A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

A chip structure comprising a semiconductor substrate, a plurality of dielectric layers, a plurality of circuit layers, a passivation layer, a metal layer and at least a bump. The semiconductor substrate has a plurality of electronic devices positioned on a surface layer of the semiconductor substrate. The dielectric layers are sequentially stacked on the semiconductor substrate and have a plurality of via holes. The circuit layers are disposed on one of the dielectric layers, wherein the circuit layers are electrically connected with each other through the via holes and are electrically connected to the electronic devices. The passivation layer is disposed over the circuit layers and the dielectric layers, wherein the passivation layer comprises an opening that exposes one of the metal layers. The metal layer is disposed over the passivation layer, wherein the metal layer comprises at least a bump pad and at least a testing pad, the bump pad electrically connecting with the testing pad. The bump is disposed on the bump pad.
TW094103006A 2005-02-01 2005-02-01 Chip structure with bumps and testing pads TWI250598B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW094103006A TWI250598B (en) 2005-02-01 2005-02-01 Chip structure with bumps and testing pads

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW094103006A TWI250598B (en) 2005-02-01 2005-02-01 Chip structure with bumps and testing pads

Publications (2)

Publication Number Publication Date
TWI250598B TWI250598B (en) 2006-03-01
TW200629438A true TW200629438A (en) 2006-08-16

Family

ID=37433079

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094103006A TWI250598B (en) 2005-02-01 2005-02-01 Chip structure with bumps and testing pads

Country Status (1)

Country Link
TW (1) TWI250598B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103700598A (en) * 2013-12-10 2014-04-02 北京中电华大电子设计有限责任公司 Method for supporting multiple chip packaging modes
TWI474453B (en) * 2011-12-07 2015-02-21 Taiwan Semiconductor Mfg Co Ltd Packaged integrated circuit chip and forming method therof
CN108461411A (en) * 2017-02-21 2018-08-28 华邦电子股份有限公司 Encapsulating structure
TWI642159B (en) * 2017-02-21 2018-11-21 華邦電子股份有限公司 Package structure

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8420520B2 (en) 2006-05-18 2013-04-16 Megica Corporation Non-cyanide gold electroplating for fine-line gold traces and gold pads
US8421227B2 (en) 2006-06-28 2013-04-16 Megica Corporation Semiconductor chip structure
US8193636B2 (en) 2007-03-13 2012-06-05 Megica Corporation Chip assembly with interconnection by metal bump

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI474453B (en) * 2011-12-07 2015-02-21 Taiwan Semiconductor Mfg Co Ltd Packaged integrated circuit chip and forming method therof
US9570366B2 (en) 2011-12-07 2017-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Passivation layer for packaged chip
CN103700598A (en) * 2013-12-10 2014-04-02 北京中电华大电子设计有限责任公司 Method for supporting multiple chip packaging modes
CN108461411A (en) * 2017-02-21 2018-08-28 华邦电子股份有限公司 Encapsulating structure
TWI642159B (en) * 2017-02-21 2018-11-21 華邦電子股份有限公司 Package structure
US10366941B2 (en) 2017-02-21 2019-07-30 Winbond Electronics Corp. Package structure
CN108461411B (en) * 2017-02-21 2020-10-27 华邦电子股份有限公司 Packaging structure

Also Published As

Publication number Publication date
TWI250598B (en) 2006-03-01

Similar Documents

Publication Publication Date Title
US10573616B2 (en) Semiconductor package and method for fabricating base for semiconductor package
TW200620577A (en) Package substrate for a semiconductor device, a fabrication method for same, and a semiconductor device
US8183678B2 (en) Semiconductor device having an interposer
US7968991B2 (en) Stacked package module and board having exposed ends
US9029928B2 (en) Semiconductor device comprising a passive component of capacitors and process for fabrication
TW200715437A (en) Semiconductor device and method of manufacturing the same
MY151533A (en) Substrate and process for semiconductor flip chip package
SG152979A1 (en) Semiconductor device and method for forming passive circuit elements with through silicon vias to backside interconnect structures
SG151162A1 (en) Solder bump with inner core pillar in semiconductor package
TW200725824A (en) A package structure with a plurality of chips stacked each other
TW200629438A (en) Chip structure with bumps and testing pads
KR20070054553A (en) Semiconductor package and method of fabricating the same
TW200713609A (en) Chip structure, chip package structure and manufacturing thereof
TW200733268A (en) Redistribution connecting structure of solder balls
TW200743199A (en) Bonding pad structure and semiconductor chip
TW200612526A (en) Chip package structure, package substrate and manufacturing method thereof
WO2009004870A1 (en) Semiconductor package
US7030487B1 (en) Chip scale packaging with improved heat dissipation capability
US20080230886A1 (en) Stacked package module
KR101037827B1 (en) Semiconductor package
TWI311354B (en) Multi-chip package structure
US7847414B2 (en) Chip package structure
TW200629439A (en) Chip structure and wafer structure
TWI675387B (en) Film capacitor structure and semiconductor device having the same
TW200603300A (en) Chip structure

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees