TWI250598B - Chip structure with bumps and testing pads - Google Patents

Abstract

A chip structure comprising a semiconductor substrate, a plurality of dielectric layers, a plurality of circuit layers, a passivation layer, a metal layer and at least a bump. The semiconductor substrate has a plurality of electronic devices positioned on a surface layer of the semiconductor substrate. The dielectric layers are sequentially stacked on the semiconductor substrate and have a plurality of via holes. The circuit layers are disposed on one of the dielectric layers, wherein the circuit layers are electrically connected with each other through the via holes and are electrically connected to the electronic devices. The passivation layer is disposed over the circuit layers and the dielectric layers, wherein the passivation layer comprises an opening that exposes one of the metal layers. The metal layer is disposed over the passivation layer, wherein the metal layer comprises at least a bump pad and at least a testing pad, the bump pad electrically connecting with the testing pad. The bump is disposed on the bump pad.

Description

J25〇598 11759twf.doc/006 IX. Description of the Invention: [Technical Field] The present invention relates to a wafer structure having bumps and test pads, and more particularly to a wafer structure in which bumps are tested It will not be damaged by the test probe (teStlng Pr〇be) because the test probe does not touch the bump. Instead, the Lai probe is used to test the wafer structure. [Prior Art] In today's competitive society, information products play a very important role. The introduction of new products and the introduction of various circuit design integrations, the latest early film offers more functions than ever before. In the case of accumulating, most of the signals are transmitted in the same single chip. Therefore, the transmission path of the number is shortened and the performance of the wafer is also improved. The ll is on the entire silk area of the wafer and the bump can be formed on the green pull, U 7 VeSUrface), compared to the applicable; H · only use the wire bonding process to circuit. Transmitted in a shorter and wider path. Therefore: the second day of the system has a potential, because the electrical performance of the signal is determined to be a better quality 曰 bonding technology during the package test step, the test probe is generally repeated; = _, and in the test The bump may be damaged by the test probe. Therefore, it is reliable to accept the test chip and the substrate: if you want to be able to get drunk in this problem, then you usually need 5 1250598 11759twf.doc/006 to add extra work (rewQrti }. [Summary of the article] It is provided that there is a bump with a test day, and a mouth structure, in which the bump is not damaged by the test probe during the test, because the test probe is reconciled, and (4) Needle breaking or knowing its #μ, +. θ connection toughness type 5 pad, and the test pad has test use. Base; upper purpose or other purposes, the present invention proposes, for example, a semiconductor substrate, a plurality of dielectric layers , a metal layer and at least one bulge. The tomb is decorated with oysters - tower protection.

A ghostly V-limb substrate has a plurality of electronic components, which are on one of the surface layers of the semi-conductive substrate. A plurality of dielectric layers are successively on the +v coarse substrate, and the dielectric layers have a plurality of via holes. Each layer of the road is disposed on the towel of the aged electrical layer, and the recording layer of the towel is electrically connected to each other by the hole. The gift layer is electrically connected to the electronic component. The protective layer is disposed on the circuit layer and the dielectric layer, and the hearing layer includes, for example, at least one opening: 曰, a top metal layer of the 5 integrated circuit. The metal layer is disposed on the protective layer, and the i-layer includes, for example, at least a bump pad and at least a test pad, and the bump is electrically connected to the test pad. The bump is disposed on the bump pad. According to a preferred embodiment of the present invention, the metal layer is, for example, a composite structure including, for example, an adhesion/barrier layer (adhesion/barrier la=r) and a thick gold layer Qhickg〇ld laye〇. The thick gold layer is formed on the standing/resistive F layer, and the material of the adhesion/barrier layer includes, for example, chromium, titanium, and! Tantalum, titanium-tungsten au〇y, tantalum_nit; ride or titanium-nitride. In other preferred embodiments of the present invention, the metal layer is, for example, a composite, ', and a mouth structure' which includes, for example, an adhesion/barrier layer and a copper layer, and the copper layer is formed on the adhesion/resist layer. The material of the upper adhesion/barrier layer includes, for example, chromium, titanium, tantalum, 6!25〇598 1 1759twf.doc/006. Titanium, gold, nitride or titanium nitride. The metal layer further includes, for example, a recording layer and a gold layer, wherein the recording layer is formed on the copper layer, and the gold layer is formed on the recording layer. The thickness of the metal layer is, for example, greater than 0.4 micrometers and the visibility such as 疋 is greater than 〇. 1 micrometer. The size of the metal layer above the protective layer is greater than the size of the circuit layer below the protective layer. The sheet structure optionally includes a polymer layer disposed between the metal layer and the thin layer. The polymer layer includes, for example, polypyrene, benzocyci butene (BCB), porous dielectric material (p〇r〇us φ material), and polyparaphenylene benzene. Molecular (pairlene), epoxide, s〇ldermaskmaterial or elastic material (elast (10) er). Furthermore, a wafer structure having a plurality of metal layers can be allowed over the protective layer. In a preferred embodiment, the metal layer on the protective layer includes, for example, at least one metal line electrically connected to the bump pad and the test pad. In other embodiments, one of the circuit layers under the protective layer may also include a metal wire for electrically connecting the bump pad to the test pad. The width of the opening of the protective layer of φ is better than 0·1 μm, and the thickness of the protective layer is, for example, greater than 0·35 μm. The protective layer is, for example, a silicon-dioxide layer, a silic〇n_nitride layer, a phosphosilicate glass (PSG) layer, a bismuth oxide (siliC0n-0xynitride) layer or A composite structure comprising one of the above materials. The bump includes, for example, a solder metal and an under-bump-metallurgy (UBM), wherein the under bump metal is disposed on the bump pad, and the solder metal is disposed on the bump bottom layer. On the metal. The bottom layer to the top surface of the bump is, for example, a titanium layer (a layer, a copper layer and a nickel layer). The material of the solder metal includes, for example, tin-lead alloy (tin-lead 7 1250598 1 1759twf.doc/006 all〇y). ) or lead-free alloy. The following is another application of the test pad. When it is no longer necessary to perform the test, the test pad can be wire-bonded Μπ. or the metal layer is more Including - wire bonding pads, which are electrically connected to the test pad and the two pads, the wire bonding pads being adapted to be connected to a wire via a wire bonding process, a to make the above and other objects, features and advantages of the present invention more Obviously easy to 'heavy' the following special - the preferred embodiment, she is based on the detailed description

under. [Embodiment] [First Embodiment] Referring to Figs. 1A to 1F, there are shown schematic cross-sectional views of a wafer structure having bumps and test pads according to a first preferred embodiment of the present invention. In the semiconductor factory, the plurality of electronic components 112 include, for example, a transistor or a metal oxide semiconductor (Metals), which is formed on a surface of a semiconductor substrate, such as germanium. A fine interconnect structure is formed on the semiconductor substrate 11A. The semiconductor substrate 110 includes, for example, a plurality of dielectric layers 22, 124, and 126, and a plurality of wiring layers 132, 34" 136. The electrical layers 122, 124, and 126 are stacked on the semiconductor substrate 110 and have a plurality of channels. A hole 128 (only one of which is shown). The circuit layers 132, 134 and 136 are respectively disposed on the dielectric layers ι 22, 124 and 126, and the circuit layer 136 has contacts 138, and the circuit layers 132, 134 and 136 can The circuit layers 132, 134 and 136 can be electrically connected to the electronic component 112 by using the communication holes 128. The circuit layers 132, 134 and 136 can be, for example, a physical Vapor Deposition (PVD). The method is deposited by using Shao or Ming alloy, or it can be deposited by electroplating or inlay 8 1250598 11759twf.doc/006 (damascence). - The protective layer 140 is formed on the thin interconnect structure. The thin interconnect structure includes, for example, a plurality of dielectric layers 122, 124, and 126, and a plurality of wiring layers 132, 134, and 136. The thickness t of the protective layer 140 is, for example, greater than 〇·35 μm. The protective layer U0 needs to have sufficient thickness to avoid being Gas, miscellaneous; (Talk Hties), mobile ions (moblle coffee) or transitional metal element (transitional metal element) penetration. Protective layer 14 such as one gas cut layer, - glass layer, - nitrogen oxide hard layer Or a composite structure comprising the above material layer. The protective layer has just the opening 142, the contact 138' and the width w of the opening 142 is, for example, greater than 〇·丄 micron. ° The following description relates to the formation after the protection 3514〇^ The thickness of the metal layer 150 is greater than 〇. 6 microns, for example, the thickness of the metal layer 150 is greater than 〇. 6 microns, for example, the ruthenium layer is formed on the protective layer 144. And 〇乂 (4). In an example, the 'metal layer 15° meter is directly shaped by the guard, and the layer 140 is again (as shown in FIGS. 1A and 1B); in another example, the 'metal layer 150 is not directly formed. On the protective layer 14 。. When it is missing, the rear dielectric layer includes a polylayer layer, which is formed on the metal layer 150; and two, between (as shown in Figures 1C, 1D and 1E). Layer 192a = includes at least a via hole 193, and the metal layer (10) can be connected by a via hole i93 with a point p. The layers l92a and 192b are, for example, a polyimide, a benzoic dielectric material, a polyparaxylene polymer, an epoxy resin, a ruthenium material, etc. Further, the back cover structure may also include a polymerization of I 92b ' It is formed on the metal layer 150 to protect the metal layer 150 from damage to external forces or environmental damage (eg, reduction, particles, static electricity, etc.), causing failure (as shown in FIG. 1B and limiE). The polymer layer has 9 1250598 11759 twf.doc/006 openings 195 and 196 exposing the bump pads 152 and test 154 of the metal layer 150. The other structure is as shown in Fig. u and Fig. 1 (the figure shows that the entire upper surface of the metal layer can also be exposed to the outside. The arrangement structure of the species to the genus layer is as shown in Fig. 4. The metal layer GO is composite The structure includes, for example, an adhesive/barrier layer 151 and a gold layer, a drilled/resistive early layer 151 is positioned on the bottom layer, and a gold layer 153 is formed on the adhesive barrier layer 151. The thickness g of 153 is, for example, greater than ^μm, and the material of the adhesion/barrier layer 151 is, for example, chromium, titanium, group, titanium alloy _ or titanium nitride, etc. The 11-person metal layer 150 may be another configuration. The metal layer 15 is a composite structure, which includes, for example, a tensile/barrier layer and a copper layer, wherein the adhesion/barrier layer is on the bottom layer, and the layer is formed on the riding/barrier layer. The transfer layer = material is, for example, chromium, titanium, neodymium, titanium-niobium alloy, nitrided or titanium nitride, etc. In this example, the metal layer 15 is, for example, an adhesive/layer and a copper layer from the bottom surface to the top surface, respectively. + In addition, the 'metal layer 15G, for example, is further included, which is formed on the copper layer. In this example, the metal layer 150 is respectively from the bottom surface to the top surface. For example, the adhesion/barrier layer, the copper layer and the metal layer 150. For example, the metal layer 150 further includes a gold layer formed on the nickel layer. In this example, the metal layer 15 is respectively, for example, from the bottom surface to the top surface. The adhesion/barrier layer, the copper layer, the nickel layer and the gold layer. The metal layer 150 includes, for example, at least one bump pad 152, at least one test pad 154 and at least one metal wire 156, wherein the metal wire 156 is connected to the bump pad 152 and tested , 154. The distance s between the bump pad 152 and the test pad 154 is, for example, less than 丄米米, and preferably less than 3 〇〇 microns. At least one bump 16 is formed on the bump pad 152. The bump ι 60 includes, for example, a solder metal 162 and a bump underlayer metal 164. During testing, a test probe (not shown) is 1250598 11759tvvf.doc/006 contacting the test pad 154 instead of the contact bump 160. Therefore, the wafer structure 1〇〇 can be tested. Therefore, the solder metal 162 of the bump 1 (9) can be prevented from being damaged by the test probe. Further, the test pad 154 can be disposed on the semiconductor substrate 11〇, and there is no electron under the test pad 154. Element 112, electronic component 112 The under bump metal 164 is directly formed on the bump pad 152, and the solder metal 162 is formed on the bump underlayer metal 164. The bump underlayer metal 164 is respectively from the bottom surface to the top surface. For example, a titanium layer, a copper layer and a nickel layer. The solder metal 162 spring material includes, for example, a tin-lead alloy or a lead-free alloy. A wire bonding process is formed to form at least one wire 170 connected to the test pad 154 as shown in FIG. 1E. Since the test pad 154 is disposed on the semiconductor substrate 110 and there is no electronic component 112 under the test pad 154, the electronic component 112 can be protected from damage during wire bonding. If the top layer of the metal layer I50 is a gold layer for connection with the gold wire 170, the connection between the wire no and the test pad 154 is satisfactory. In other examples, after the protective layer 140 is formed, the sheath structure includes, for example, a plurality of metal layers and a plurality of polymer layers. In Fig. 1F, for example, two metal layers 15 and 15 〇b are included on the protective layer 14A. The present invention is not limited to the above-disclosed portions, and a metal layer of three, four or more layers may be formed on the protective layer 140. The metal layer 150b is disposed between the metal layer 15A and the protective layer 140, and the metal layer 15A is electrically connected to the contact layer 138 via the metal layer 15b to the susceptor layer 150b. The polymer layer ig2c is disposed between the metal layer 150a and the metal layer 150b, and the polymer layer 192c includes, for example, at least one via hole 183 for electrically connecting the metal layer 15A and the metal layer 15B. A polymer layer 192d is formed on the metal layer 15 for use in 11 1250598 11759 twf.doc/006

The protective metal layer 150a is protected from moisture intrusion or from electrostatic charges in the environment. The polymer layer 192d has openings 185 and 186 which respectively define a bump pad 152 of the metal layer 150a and a test pad 154. The polymer layer 7192^192d includes, for example, polyimine, phenylcyclobutene, porous dielectric a material, polyparaxylene polymer, epoxy resin, solder mask material, or elastic material. The metal layers 150a and 150b may be of the same construction and composition material, the structure and material of which may be as described above for the metal layer 150. The metal layer 15 is: with a metal wire 156 to connect the test pad 154 with the bump pad 152. The distance S between the bump pad 152 and the two test pads 154 is, for example, less than! Millimeters, and preferably less than micrometers. A bump 160 is formed on the bump pad 152. In the electrical position, Lai Lin (tree) will contact the test pad 54 to test the wafer structure. After the test is completed, a line (not shown) can also be selectively connected to the test pad 154. In the drawings of the first embodiment, if the reference numerals are the same, the components pointed to by the reference numerals are identical or similar. The second embodiment of the present invention is not limited to the first embodiment described above, and the second preferred embodiment of the present invention is described in detail below. 2A to 2E illustrate the invention. For example, a test pad can be used as a manufacturing route, and in the second embodiment, a pad can be additionally used as a wire bonding use. In the second embodiment, if the labels of the reference numerals are identical, the components pointed to by the reference numerals are identical or similar. ^ The structure of the sheath after having a single metal layer of 15 ( (as shown in Figure 2 to Figure 2D) is detailed later. The metal layer is formed on the protective layer "ο 12 1250598 11759 twf.doc / 006 ϋ junction 138. The metal layer 15 〇 has at least - bump pad 152, two 3 f 154Oi _ 158, metal, lines 156 and 157, The 157 series respectively connects the bump 塾 152 and the test 塾 154 and: = 4 and the wire bonding pad 158. The distance S between the bump pad 152 and the test pad 154 is, for example, less than 1 (7) is formed on the bump pad, 152 Preferably, it is less than micrometer. When the bump mi is in the vicinity of the pulse, the test probe can contact the test pad 154 TM^2〇〇°^2, to avoid the fork to be tested. The condition of the probe puncture. In the process of making the wire 2: ' ¥ line 170 can be formed on the wire bonding 塾 158 i. Test 塾 154 = D, the pad 158 is placed on the semiconductor substrate n ,, and measured % and = private The underside of the pad (10) may be called electronic component ιΐ2, so that the electron 70 纟' can be prevented from being damaged during the bonding process. In the example, the 'metal layer 150' is formed directly on the protective layer (10) (such as f A and 2B are shown.) In other examples, the metal layer 15 can also be formed in the protective layer 14G. (As shown in Fig. 2C and Fig. 2D), the ::, . . . structure further includes a polymer running between the metal layer and the protective layer 14〇. The polymer layer has at least one Channel hole = 3, for electrically connecting the metal 50 and the contact 138. In addition, the last four layers ', for example, include a polymer layer 192b (as shown in the second β-picture and the (9) figure), Finely formed on the metal layer 150 to protect the metal layer 150 from external force damage and environmental effects (such as moisture, particles and electric charges, etc.) The polymer layer has openings 195, 196 and 197, respectively exposing the convex The block pad 152, the test pad 154 and the wire bonding 塾 158. In addition, as shown in the second and 帛% diagrams, the entire upper surface of the metal layer 150 may also be exposed. The polymer layer and the 192b include, for example, the brewing. Imine, phenylcyclobutene, porous dielectric material, poly 13 1250598 11759tvvf.doc/006 p-phthalonitrile polymer, epoxy resin, welding cap material or elastic material, etc. In another example, 'formation After the protective layer, the sheath structure comprises, for example, a layer metal layer and a multilayer polymer layer. In the figure, the protective layer 14 includes, for example, two metal layers 150 & and 150b. It should be noted that this is not limited to the number of metal layers depicted in the figure. On the protective layer 14 The metal layer includes three layers, four layers or even more layers. The metal layer 15〇b is disposed between the layer 150a and the protective layer 140, and the metal layer 15〇a is electrically connected to the contact 138 via the metal layer. The layer is formed between the metal layer and the protective layer 140, and has a via hole 2〇2 for electrically connecting the ^150b and the contact 138. The polymer layer 192f is formed between the metal layers and has a via hole 2〇4 which is connected to the metal layer 15 as well. The entire upper surface of the metal layer 150a is exposed to the outside, for example. The metal layer (10) has a bump pad 152, a test pad 154, a wire bond pad 158, and all of the wires 156 and 157, wherein the wires 156 and 157 are respectively connected ==, and the pad 154 is bonded to the wire bond 158. The distance S between the bumps 152 and is, for example, less than 1 mm, and preferably less than 300 mm. A bump 160 is formed on the bump pad 152. During the test of the track t-passivity test, the test probe (not shown) can be contacted to test the wafer structure. When the wire bonding process is performed, the wire wires 170 are connected, and the wire bonding is performed with the m 192e#U92f oxygen tree two-hole dielectric material, the parylene polymer, the ring nipple, the mask material or the elastic material. . [Third Embodiment] In the above embodiment, the metal wires of the connection test pad and the bump pad are disposed on the protective layer of 14 1250598 1 l759twf.doc/〇〇6. However, in this example of the present invention, the arrangement of the test pads is connected. Below the layer. 3A to 3EFig.=P is a crystal disposed on the protective bump and the test pad. 具有The embodiment has the same reference numeral as the first embodiment or the ___ No., the component is -" gamma ^ 136 V packets: -I::: map, located in the protective layer 14 (3 below the circuit layer (7) 2 and 139 and - metal, line (3), and all of them Jing

3 l4〇^^r^ - ^ 4·4 = Don't show the contacts 138 and 139. The back cover "all 14" 54 / / by, for example, including at least one bump 152 and at least one test 的 Ϊ塾 152 and test 154 may be by the bit in the protective layer 140 (four) ^ Ϊ line each other Electrical connection. Between the bump 塾 152 and the test pad 154: ^ is less than 1 亳, and preferably less than 30 嶋. A bump 160 is formed on the bump pad 152. When the test step is performed, a test probe (not shown) can be contacted with the test 154 154 ' to test the wafer structure 3 〇〇. Therefore, it is possible to prevent the solder j 162 of the bump (10) from being stabbed by the test probe. In addition, the test pad 154 is disposed on the half V to the substrate 110, and the test pad 154 may have no electronic component 112 underneath, so that the force of the test probe being poked into the test pad 154 may be avoided. Element 112. In one example, the metal layer 15Q may be formed directly on the protective layer 14A (as shown in Figures 3A and 3B). In another example, the metal layer 15〇 may not be directly formed on the protective layer 14〇, and the back cover layer structure further includes, for example, a layer 192a′ which is formed on the metal layer 150 and the protective layer 140 15 1250598 11759twf.doc/006 (as shown in Figures 3C, 3D and 3E). The polymer layer has via holes 193 and 194' and the metal layer 150 is connected to the dots 138 and 139 by via holes 193 and 194, respectively. In addition, the back cover structure includes, for example, a polymer layer 1 formed on the metal layer 150, and the polymer layer 1· can protect the metal reed 150 (as shown in FIGS. 3B, 3D and 3E) from external force damage. And the environment ^ (such as moisture, particles and charges, etc.). The polymer layer 192b has openings 196 that expose the bump pads 152 and test pads 154, respectively. Furthermore, as shown in Fig. 3C, the entire upper surface of the metal layer 15Q may also be a violent outer layer. The polymer layers 192a and 192b include, for example, a polyamicimide, a phenylcyclobutene, a porous dielectric material, a poly(p-dioxene), or an elastic material. A "knife, bad cream, weld cap material after the test step is completed" may also be performed, for example, by a one-wire bonding process to form at least a wire 170 attached to the test pad 154 (e.g., No). Since the test pad 154 is placed on the semiconductor substrate 11 and the test 塾i54 is down = the electronic component 112 may not be disposed, when the wire bonding process is performed, it is avoided that the electronic component 震12 is shaken_large (four) to the machine. If the top layer of the metal crucible 150 is a gold layer and is connected to the gold wire 17Q, there will be a good bonding state between the wire 70 and the test pad. In summary, the present invention has the following advantages: ^ During the test step, a test probe will contact the test cymbal to thereby measure = slice = structure without contacting the bump. Therefore, the solder metal of the bump is subjected to a test such as a mussel injury. The =" type can be placed on a semiconductor substrate that does not have electronic components below, so that electronic components can be prevented from being damaged during testing. The top layer of the metal layer may be a gold layer for connection with the gold wire, so that a good connection between the * wire and the Ride or between the wire and the (4) bond pad can be formed as a good 16 1250598 11759 twf.doc/006. While the invention has been described in terms of a preferred embodiment of the present invention, it is not intended to limit the scope of the invention. Xu Zhi is moved and retouched, so the scope defined in the patent application is subject to change. ^之保4围田视视 [Simple diagram of the diagram] Figure 1A to ip diagram shows the hair ^^ ^ ; . r R ^ ^ R Mingdi, a better example of a bump test A cross-sectional view of the structure of the day.

2A to 2D are cross-sectional views showing the structure of a wafer having bumps and test pads according to a second preferred embodiment of the present invention. 3A to 3E are schematic cross-sectional views showing a wafer structure having bumps and potentials according to a third preferred embodiment of the present invention. Figure 4 is a schematic cross-sectional view of the metal layer. [Main component symbol description] 100, 200, 300: wafer structure 110: semiconductor substrate 112. Electronic components 122, 124, 126: dielectric layers 128, 183, 193, 194, 202, 204: via holes 132, 134, 136 · Circuit layers 137, 156, 157: metal lines 138, 139 · Contact 140: protective layers 142, 144, 185, 186, 195, 196, 197 · openings 150, 150a, 150b, 150c, 150d: metal Layer 151: Adhesive/barrier layer 17 1250598 11759twf.doc/006 152: Bump pad 153: Gold layer 154: Test 158: Wire bond pad 160: Bump 162: Solder metal 164: Bump bottom metal 170: Wire - 192a, 192b, 192c, 192d, 192e, 192f: polymer layer

18

Claims (1)

1250598 11 759twf.doc/006 X. Patent application scope: 1. A wafer structure, comprising: a semiconductor substrate, having a plurality of Taiyi electronic semiconductor components in the semiconductor base, and the electronic components One of the bits; the soil - one of the fine interconnect structures in the surface layer of the semiconductor substrate and the surface of the semiconductor substrate, including: the layer has the material county red, and the dielectric peas in the evening, f f layer, And each of the four tiers of the circuit layer is located in the dielectrics, wherein the circuit layers are electrically connected to each other through the via holes; the electrical connections are electrically connected to the electronic components; The connection structure, wherein the protection layer includes a portion from the top layer of the circuit layer to the 丄1 storm; the pile layer ' layer structure is located on the protection layer, and is electrically connected to the circuit layers, The last t-layer structure includes at least one of the tests, and is electrically connected to the bump pad; and at least one bump is located on the bump pad. Structure == genus: The crystal structure described in the above item, wherein the back cover layer is in the Maqiu-genus layer, wherein the metal layer is a composite structure including a large degree/barrier layer and a top layer - a gold layer, and the gold layer has a thick barrier = 1 ^ the wafer structure described in the second item, wherein the adhesion/mussels include chromium, titanium, tantalum, titanium tungsten alloy, tantalum nitride or nitride titanium. (4) Spoon, towel, please patent the first item of the wafer structure, the towel layer of the back cover metal layer, the towel is made of "composite structure", including a ^ F early layer and a copper layer, and the copper layer Formed on the adhesion/barrier layer 19 1250598 11759twf.doc/〇〇5. The material of the barrier layer ranges from the wafer structure described in item 4, wherein the adhesion/ 6. such as Shenshe = tongue =, titanium, tantalum, titanium tungsten alloy, nitride button or titanium nitride. Further, the wafer structure of claim 4, wherein the metal layer is further disposed on the copper layer. More specifically, the wafer structure includes a wafer structure in which a wafer layer is formed between the back layer and the protective layer, and the polymer layer is located on the metal layer to include a wafer structure. Wherein the polymer polymer, epoxy tree armor 10 · such as the Shenqing patent section drawing, the layer comprises at least - metal layer wafer structure, wherein the rear guard JS head female 铋 铋 、, wind " One of the layers is a polymer layer, and the polymerization port is exposed to ί. * mouth 'and the test pad and the bump pad respectively by the opening 11 · as claimed in the patent scope of the 1st layer includes polyimine, stupid, factory slab structure 'where the benzene The ruthenium molecule, the epoxy butylene butylene, the smectic dielectric material, and the poly-p-pair structure include at least two-sided 1-pin wafer structures, and the post-protection 13 is as claimed in the patent range 笙τ ^, and the layer includes a top metal a layer, a towel structure, wherein the back wire protects the wire and the test pad.至至属14. The wafer structure of claim 1, wherein the layer of the circuit layer under the protective layer of the 20 1250598 11 759 twf.doc/006 layer comprises at least a bump The pad is electrically connected to the test pad by the metal wire. ', _, ' 杲 and wherein the protection is wherein the protection of the oxynitride layer or the latter is 15. The width of the opening of the wafer structure layer of claim 1 is greater than 0.1 micron. . 16. The thickness of the wafer structure layer as described in claim i is greater than 〇·35 μm. 17. The wafer structure layer according to Item 1 of the patent application is a oxidized stone layer, a nitride layer, a disc stone layer, and a composite structure comprising the above materials. The wafer structure described in the first paragraph of the patent scope has the structure of τ, which includes the structure described in the above paragraph, wherein the bump (four) convex bump bottom metal, and the bump bottom metal layer The cyan system is disposed on the underlying metal of the bump. The bottom metal is from the bottom surface to the 'two turns', wherein the bump is a titanium layer, a copper layer and a nickel layer. The wafer structure, wherein the solder material comprises a tin material or a solder-free solder. The pad is in the wafer structure described in item 1, wherein the test is connected. After the handle, the test pad is borrowed The wafer structure described in the one-wire bonding process and the one-layer layer package, wherein the rear protection process is connected to a wire. The wire bonding pad is patented by a wire bonding system. The wafer structure, wherein the wire 21 1250598 11759 twf.doc/〇〇6 interface is connected to the test pad and/or the bump 塾. 5. The wafer structure according to the first item of the fourth patent, The distance between the convex pad and the _ test is less than · micron. The wafer structure of claim 1, wherein the bump U test pad has a drain loss of less than 1 n '27. The wafer structure comprises: 2. A semi-substrate having a plurality of electronic components, and wherein The electronic component is on the surface layer of the semiconductor substrate and a thin interconnect structure in the surface layer of the semiconductor substrate, including: a @ ^ 数 们 丨黾 , layer, located on the semiconductor substrate, and The dielectric layer has a plurality of via holes; and the rabbit layer has a plurality of circuit layers thereon, and each of the circuit layers is located on the dielectric layers, wherein the circuit layers are mutually Electrically connected, the Qiu Lu Road layer is electrically connected to the electronic components; +_„ 4 layers are located on the thin interconnect structure, and the protective layer includes the first layer to expose the circuit layers a topmost portion; at least the structure 'is located on the tilt layer, the (4) layer structure comprises a layer, and the circuit layers are electrically connected, and the metal layer comprises - the metal layer is not again in the rice, and the metal The layer includes at least one bump pad fish having at least one wire bonding pad; The main/, main eve to the parent bump is disposed on the bump pad; and is connected to the wire bonding pad by a wire bonding process. The layer is further composed of the structure 4 described in item 27, wherein the metal layer/resistance layer is located below the gold layer. 29. The wafer structure of claim 28, wherein the adhesive 22 1250598 11759 twf.doc/0 〇 6 / barrier early layer material comprises chromium, titanium, tantalum, titanium tungsten alloy, tantalum nitride or nitrogen Titanium. 30. The wafer structure of claim 2, wherein the backing layer further comprises a polymer layer disposed between the metal layer and the protective layer. 31. The wafer structure of claim 30, wherein the polymerization comprises poly-imine, stupid cyclobutene, porous dielectric material, polyparaphenylene-based south molecule, epoxy One of resin, welding material and elastic material. The wafer structure of claim 27, wherein the backing & structure further comprises a polymer layer overlying the metal layer. Ia33. The wafer structure of claim 32, wherein the polymeric cage is a mixture of aramid, a cyclopentene, a porous dielectric material, a polyparaphore, a knife, and an epoxy resin. One of the welding cap material and the elastic material. The wafer structure of claim 27, wherein the rear guard, and the structure further comprises a plurality of metal layers. The wafer structure of claim 27, wherein the metal-titanium pad and the crucible are connected to at least one metal wire, and the metal wire is connected to the convex layer package (4) 27 (4) piece structure, wherein The metal 1 includes at least some of the wires (four) of the protective layer under the protective layer. The width of the opening of the wafer layer of the wafer layer as described in claim 27 is greater than 0.1 micrometer. ,. 4〃七海保5也 38· If the thickness of the 27th layer of the patent application scope is greater than the system 〇·35 micro-seeking. The sputum structure passed by the clerk, wherein the protection 39. If the 27th item of the patent application scope is a layer of oxidized stone, a layer of nitriding stone,: 'a glaze layer: ί: 23 1250598 11759twf.doc/ 006 is a composite structure including one of the above materials. 4微米。 The thickness of the metal layer is greater than 0.4 microns. The wafer structure of claim 27, wherein the bump comprises a solder metal and a bump underlayer metal, and the bump underlayer metal is disposed on the bump pad, and the solder metal system It is disposed on the underlying metal of the bump. 42. The wafer structure of claim 41, wherein the bump underlayer metal is a titanium layer, a copper layer and a nickel layer from bottom to top. The wafer structure of claim 41, wherein the solder metal material comprises tin-lead solder or lead-free solder. The wafer structure of claim 27, wherein the metal layer further comprises at least one test pad electrically connected to the bump pad, and the distance between the bump pad and the test pad is less than 300 Micron. The wafer structure of claim 27, wherein the metal layer further comprises at least one test pad electrically connected to the bump pad, and the distance between the bump pad and the test pad is less than 1 Millimeter. twenty four