TWI225288B - Chip structure - Google Patents

Abstract

A chip structure includes a substrate, an integrated-circuit layer, a passivation layer, a pad-capping metal and a wire-bondable metal. The substrate has multiple electric devices located on a surface layer of a surface of the substrate. The integrated-circuit layer had multiple circuit layers electrically connecting with each other and electrically connecting with the electric devices. One of the circuit layers has multiple pads. The passivation layer is located on the integrated-circuit layer and has multiple openings penetrating through the passivation layer. The openings expose the pads. The pad-capping metal is located on the pads and the wire-bondable metal is positioned on the pad-capping metal. Multiple conductive wires formed by a wire-bonding process can be bonded onto the wire-bondable metal.

Description

1225288 V. Description of the invention α) [Technical field of the present invention with protection] The invention relates to a wafer structure for protecting a metal wafer structure. And in particular, there is a kind of [fundamental integration, reduction, shortened production, metal micron forward generation, current degree. Down, direction connected state. Former technology and information technology products, because there are more and larger signals, as electrical products become smaller and smaller, the connection line, and then down. However, the density of the metal connection will cause the so-called electric metal to move. The cut-off part of the wire will transfer the new power to the sub-segment. The new rule set a new step. The shrinkage of the wire will cause serious migration. This will make the conductor the industrial and commercial society. The role has been new, especially the single chip of the current circuit generation is often better than before. After the integration, not only the transmission of electrical signals only in the path of a single crystal, but also the evolution of the more local electrical technology, the functionality is more, as far as the appearance of electronic products is concerned. Therefore, the size of the semiconductor process has also been continuously reduced, from 0.25 to 0.15 microns, or even to reduce the metal connection lines, while the resistance and current density will greatly affect the electromigration (E 1 ectr 〇mi shift is when the number of atoms in the thin film wire originally extending along the grain boundary of the material itself is small, and finally the material of the metal connecting wire of the metal connecting wire element becomes more and more important. The volume of a single chip circuit can be on-chip, due to its performance. Complex, but also lighter, its chip micron reduction nanometer level and many problems will increase gr ati on) The electrons are extremely high, and the electrons are decremented, leading to the most broken circuit. It is often used to reduce the thickness of the human-friendly, thin, internal to 0 · 18 generations. As a result, a particularly reliable electric field flow is caused by metal.

11786twf.ptd Page 8 1225288 V. Description of the invention (2) Aluminum because of its strong manufacturability (including sputtering, evaporation, chemical vapor deposition, dry etching, and wet etching can be applied on aluminum) And the adhesion of aluminum to silicon dioxide is very good, so aluminum is a very good material for metal connection lines, but the ability to resist electromigration is very poor, so it is necessary to replace the metal connection while the metal connection line is shrinking. The material of the wire and the resistance value of aluminum is relatively high, so the effect of resistance capacitance delay will also occur. Therefore, in order to improve the above problems, it is necessary to select a metal material with low resistance and high resistance to electromigration, and copper has the above conditions. Early semiconductor processes were reluctant to use copper as the metal connection line because the diffusion coefficient of copper was very high. After copper and silicon or silicon dioxide contacted, it would diffuse into the substrate quickly, resulting in deep energy level problems. In addition, copper itself is susceptible to oxidation, reacts easily with other materials at low temperatures, and copper lacks effective dry etching techniques, all of which have limited the development of copper metal. However, with the advancement of materials and process technology, various barrier layers have been continuously researched. The development of the Damasa process and the copper chemical mechanical polishing technology have been successfully developed to solve these problems. However, after copper comes into contact with air, it is easy to produce an oxidation reaction. Therefore, after the wafer is manufactured by the copper process, a pad protection metal must be used to cover the copper pad exposed outside the opening of the protective layer, so as to avoid the copper pad. An oxidation reaction occurs when it comes into contact with air. For a detailed structure, please refer to FIG. 1, which is a schematic cross-sectional view showing a structure in which a conventional wire is connected to a copper pad. As shown in FIG. 1, after the wafer is completed with a copper etching process by an overetching process, the wafer 100 will have at least one pad 110 and a protective layer.

11786twf.ptd Page 9 1225288 V. Description of the invention (3) 1 2 0, the protective layer 1 2 0 has at least one protective layer opening 1 2 2 and the pad 1 1 0 is exposed to the outside through the protective layer opening 1 2 2 The material of the pad 1 1 0 is copper. In order to avoid the oxidation reaction between the pad 110 and the air, a pad protection metal 130 is formed on the pad 1 110, and the material of the pad protection metal 130 is aluminum. In the next wire bonding process, the wire 14 can be directly bonded to the pad protection metal 130. However, the material used for the general wire 1 40 is gold, which is not the same as the material (aluminum) of the pad protection metal 1 3 0. Therefore, the wire 14 1 is bonded to the pad protection metal 1 3 0. After the above, four kinds of gold aluminum alloys (A12Au, AlAu, AlAu2, A 1 2 Au 6) will be formed on the interface between the wire 1 14 and the pad Baozun metal 1 3 0. A porous structure will reduce the effective bonding area between the wire 140 and the pad protection metal 130. Based on the above reasons, the bonding between the wire 140 and the pad protection metal 130 is poor. For the bonding relationship between gold and aluminum, refer to "The Materials Science of Thin Films", Milton Ohring, Academic Press, Inc. 1992, ISBN 0-12-524990-X, pp. 376-379. The pad is only covered with the pad protection metal 1 3 0. If the thickness of the pad protection metal 1 3 0 is insufficient, the probe is likely to pass through the pad protection metal 1 3 0 during the test, and The material that is damaged is, for example, the copper pad 110. At this time, the pad 110 will be exposed to the air and oxidized. [Summary of the Invention]

11786twf.ptd Page 10 1225288 V. Description of the invention (4) Therefore, one of the objects of the present invention is to provide a wafer structure in which a wire bonding wire metal is also formed on the pad protection metal to increase the bonding of the wire bonding wire to the pad. Engagement ability. Another object of the present invention is to provide a wafer structure, in which the pad can protect the metal through the pad to electrically connect the connection line or the passive component formed on the protective layer, so that a high-performance wafer structure can be manufactured. The third object of the present invention is to provide a wafer structure, in which the pad protection metal and the bonding wire bonding metal can be stacked on the pad, and the total thickness of the stack is very low. Therefore, when the test is performed, the probe is less likely to penetrate. Over-wired wire bonding metal and connection protection metal, which damage the material such as copper pads, so that the pads can be prevented from being exposed to the air and oxidation will occur. Before describing the present invention, define the use of space prepositions. The so-called spatial preposition '' on π means that the spatial relationship between the two things is accessible or inaccessible. For example, the A object is on the B object, which means that the A object can be directly disposed on the B object, and the A object is in contact with the B object; or the A system is disposed in the space on the B object, and A The object is not in contact with the B object. In order to achieve the above and other objectives of the present invention, a chip structure is proposed, which is suitable for connecting a plurality of wire bonding wires to the chip structure by a wire bonding process. The chip structure includes at least a substrate, a circuit layer, a protective layer, and a pad. Protective metal, a wire bonding metal, a connection line and a passive component. The substrate has a plurality of electronic components, and is a surface layer on one surface of the substrate. The circuit layer is located on the surface of the substrate. The circuit layer has a plurality of circuit layers. The circuit layers are electrically connected to each other, and the circuit layers are connected to electronic components.

11786twf.ptd Page 11 of 1225288 of which the protective layer is exposed. The bonding metal wire is bonded to the pad due to the bonding wire. It improves the electrical connection of the bonding wire through the pad. Because of the distance here, you can avoid it. Sub-element; to reduce the current flow (eddy sensing element. The above mentioned embodiments preferably have multiple pads. The connection is located in the metal. The protective gold wire is connected and hit, so the wire and the protective gold are connected if necessary. The substrate is free of capacitance and the inductance of the inductor is curren. The metal is the same as the metal. The crystal structure of the above-mentioned energy can interfere with the silicon substrate. V. Description of the invention (5) Electrical connection, circuit On the layer, and the layer, the protective layer opening, and the wiring wire is connected to the wiring on the protective layer, and in summary, the surface material can be configured by the same metal, which can be greatly changed, and the pad can connect the line Or passive element structure. For example, on the protective layer, and as far as the capacitive element is located, the distance of electricity on the substrate can be far away. In order to make the present invention easier to understand, the following description of the eddy current with high quality parameters is given below: There are multiple connection protection layers, open pads, and gold pads to protect the connection lines. The structure is related to the formation of the capacitor element, which can also hold the element and the stored element, and has a t) effect, other purposes, characteristic examples, and cooperation. The protective layer is located at the mouth, and the protective protective system is located on the pad metal. The wire conductor and the passive component are evenly placed. The electromagnetic field from the substrate is so possible, and the advantages can be more clearly illustrated, for details.

11786twf.ptd Page 12 1225288 V. Description of the invention (6) First embodiment Please refer to FIG. 2 for a schematic cross-sectional view of a chip structure that can be used to connect wire bonding wires according to the first preferred embodiment of the present invention. The wafer structure 200 includes a substrate 210, a circuit build-up layer 220, a protective layer 230, a pad protection metal 240 and a wire bonding metal 250. The substrate 210 has a plurality of electronic components 212, which are located on the surface of one surface 214 of the substrate 210. The circuit layer 220 is located on the surface 214 of the substrate 21, and the line = layer 2 2 0 has a plurality of circuit layers 2 2 2, and the circuit layers 2 2 2 are electrically

The V VA circuit layer 222 is electrically connected to the electronic component 212. The circuit layer Γ is made of two layers with a plurality of pads 224 ', where the circuit layer 222 is, for example, 3Zi ^ H aSCene), and the circuit is wide. The material of 22 is made of St copper alloy. The protective layer 230 is located on the circuit layer 22o, and Ϊ J22 (f) can prevent #quality and water and gas in the environment from entering the circuit layer 220, and the protective layer 23 has multiple protective layers ^ , Protective layer 230, >

Mil Μ surname mr / only layer 3 exposes the connector 224, of which the protective layer: if the material Λ is composed of at least one of the following materials, nitrogen silicon compounds, oxysilicon compounds and phosphite glass, a composite layer Structure ίΐ ί The thickness of the protective layer 2 3 0 is greater than 0.35 micrometers, for example, and the edge-protective layer opening 2 3 2 can be measured: i * maid's palace; «, between 20 micrometers. 1. " Maximum visibility is between 0.1 micron to ^, for example. = For example, the connection of copper or copper alloy and air generate oxygen to configure the pad protection metal 240 on the pad 2 24, where The compliance metal 240 is, for example, an inscription or an inscription alloy. In this way, the transfer of wafers (such as transferring from a fab to a packaging plant) can

1225288 V. Description of the invention (7) Oxidation, and it is possible to prevent the probe (not shown) from being inserted into the pad 224 and hurting the pad 224 during the test. In order to improve the bonding between the bonding wire 3 1 0 and the chip structure 2 0, a bonding wire bonding metal 2 50 can be formed on the connection protection metal 2 4 0, and then the bonding wire 3 1 0 is bonded to the bonding wire. Wire bonding on metal 2 50. In general, since the material of the wire 3 3 0 is gold, if gold is used as the surface material of the metal 2 5 0 and the wire 3 10 in contact with the wire, then this is the bonding between the same metals. It is possible to greatly improve the bondability between the wire 3 3 0 and the chip structure 2 0. The structure of the wire bonding metal 2 50 is selected from a composite layer composed of the following metals, titanium tungsten alloy, titanium nitrogen compound, and gold. For example, the wire bonding metal 2 50 is composed of The order from bottom to top is, for example, the Qinyan alloy layer and the gold layer. Among them, the titanium-tungsten alloy layer is directly in contact with the pad protection metal 2 40, and the wire 3 1 0 is bonded to the gold layer; The order of 2 50 from bottom to top is, for example, a titanium nitride compound layer and a gold layer. The titanium nitride compound layer is directly in contact with the pad protection metal 2 40, and the wire 3 1 0 is bonded to the gold layer. 3 to 7 of the second embodiment are schematic cross-sectional views showing the connection between a chip structure and a connection line according to a second preferred embodiment of the present invention. If the reference numerals in this embodiment are the same as those in the first embodiment, then It means that the components specified in this embodiment are the same as those specified in the first embodiment, and will not be repeated here. In this embodiment, in addition to the wafer structure 2 0 1

11786twf.ptd Page 14 1 ^^ 288 Five descriptions of the invention (8) bottom 2 1 0, green erosion path 2 60, layer 22 0 and protective layer 23 (), and a connection line 23 0, & And > Figures, cars, and cars, the connection line 2 60 is directly formed on the protective layer line. The sound path 26 ° is connected to the pad protection metal 24 °, and the road is part of the line. It can be connected to the connection line 2 2 0 through the protective layer 2 3 0 $ 1 ^ Line 26〇 and the protective layer 23 ° to connect to the line stack, the slave / separated line, where the connection line 26〇 is for example the power bus_ Connect to the bus or use it for transmitting signals. In terms of signal transmission, Γβ i? Is transmitted from one of the electronic components 212 to the wiring layer 2 2 0. The knife circuit 'is then transmitted through the protective layer 230 to the connection circuit 26, and then transmitted through the protective layer 230 to other parts of the circuit stack 220, and finally to other electronic components 212. The structure of the connection 260 is selected from a composite layer composed of the following metals, titanium tungsten alloy, titanium nitrogen compound, titanium, chromium, copper, chromium copper alloy, nickel and gold, for example and In other words, the metal structure of the connection line 260 is, for example, a titanium layer and a copper layer laminated from the bottom up; or a titanium layer, a copper layer and a nickel layer laminated from the bottom up; or The titanium layer, the copper layer, the recording layer, and the gold layer are stacked from bottom to top; or the titanium tungsten alloy layer ^ gold layer is stacked from bottom to top; or the titanium nitrogen compound layer and Gold ^ is superimposed from bottom to top. However, the structure of the connection line 260 in the present invention is not limited to this. The material of the connection line 260 may also be made of aluminum or aluminum alloy. Please refer to FIG. 4 ′ After forming the connection line 2 6 〇 on the protective layer 230 as described above, it may be formed by spin-coating

11786twf.ptd Page 15 1225288 V. Description of the invention (9) An insulating layer 320 is on the protective layer 230, and the insulating layer 320 will cover the connection line 2 60 to protect the connection line 2 60. The material of the insulating layer 3 2 0 is, for example, polyimide (PI), benzocyclobutene (BCB), porous dielectric material, parylene, or elastomer (elastomer). ) And other high molecular polymers. Referring to FIG. 5, the connection line 2 60 of the present invention can also be formed on the insulating layer 3 3 0 as described below. After the pad protection metal 2 40 is formed on the pad 2 24 exposed by the protective layer opening 2 3 2, an insulating layer 330 may be formed on the protective layer 230 by spin-coating, where The material of the insulating layer 3 3 0 is, for example, polyimide (p 0 1 y 丨 m 丨 de, p I), phenylcyclobutene (BCB), porous dielectric material, polyarylene ether ( parylene) or elastomer (elastomer). After that, a connection line 26 can be formed on the insulating layer 3 3 0. The insulating layer 3 3 0 has a plurality of openings 3 3 2, and the pad protection metal 2 40 is exposed, so that the connection line 2 60 can be electrically connected to the pad protection metal 2 40 through the opening 3 3 2. The structure and material of the connection line 260 are as described above, and will not be repeated here. And some of the lines of the line stack 2 2 0 can be connected to the external lines such as the wire 3 3 0 through the protection layer 2 3 0 and the connection line 2 60. Please refer to FIG. 6 'After forming the connection line 2 6 0 as described in FIG. 5 on the insulating layer 3 3 0, a spin coating can be used to form an insulating layer 3 4 0 and The insulating layer 3 3 0, and the insulating layer 3 4 0 will cover the connecting line 2 6 0 ′, thereby protecting the connecting line 2 6 0, wherein the insulating layer 3 3 〇,

11786t.wf.ptd Page 16 1225288 V. Description of the invention (ίο) 340 materials such as polyimide (PI), phenylcyclobutene (BCB), porous dielectric materials, polyimide Polymers such as aryl ether (parylene) or elastomer (eiastomer). The insulating layer 3 4 0 has a plurality of openings 3 4 2, exposing the connection line 2 60, so that, for example, the outer boundary line of the bump 3 1 3 can be connected to the connection line 2 60. In addition to the single-layer circuit layer structure described above, the connection line may also have a multilayer circuit layer structure, as shown in FIG. 7, where the connection line 2 6 0 is, for example, a two-layer layer 2 6 1, 2 6 2 and an insulating layer 3 50 is located between the circuit layers 2 6 1 and 2 6 2 and can be used for electrical isolation. The insulating layer 350 has a via hole 352, and the circuit layer 262 can be connected to the circuit layer 261 through the via hole 252. The circuit layer 2 6 1 is directly on the protective layer 2 30 and is connected to the pad protective metal 2 40. The insulating layer 360 is located on the insulating layer 350, and the insulating layer 360 covers the circuit layer 2 62, thereby protecting the circuit layer 2 62. The materials of the insulation layers 350 and 360 are, for example, polyimide (PI), benzocyclobutene (BCB), porous dielectric material, polyarylene ether (parylene), or elastomer (elastomer). ) And other high molecular polymers. Third Embodiment FIG. 8 to FIG. 11 are schematic cross-sectional views showing a connection between a chip structure and an inductive element according to a third preferred embodiment of the present invention, where the reference numerals in this embodiment are the same as those in the first embodiment or the second embodiment. The same as the preferred embodiment means that the components specified in this embodiment are the same as those in the first embodiment or the second embodiment.

Page 17 1225288 V. Description of the invention (11) The components specified in the preferred embodiment are not repeated here. In this embodiment, the wafer structure 202 includes an inductive element 270 in addition to the aforementioned substrate 210, the circuit build-up layer 220, and the protective layer 230. Please refer to FIG. 8 and FIG. 8A, where FIG. 8A shows a schematic top view of the inductor element in FIG. 8, and the inductor element in FIG. 8 is a section along section line I-I in FIG. 8A schematic diagram. The inductive element 2 7 0 is directly formed on the protective layer 2 3 0, and the inductive element 2 7 0 is electrically connected to the pad protection metal 2 4 0, and the inductive element 2 7 0 is, for example, a spiral-wound pattern, or Similar to the style of the coil, the detailed structure can refer to the Republic of China Patent Publication No. 5 06, 0 5, US Patent Publication No. 6, 303, 423, 6, 455, 885, 6, 489, 647 No. 6, 489, 656 and 6, 515, 369, U.S. Patent Application Nos. 10/445558, 10/445559, and 10/445560, etc., the concepts of the above patent cases can be applied to this case . In this embodiment, a spiral-shaped inductance element 270 is used as an example. The circuit layer 220 also has an electromagnetic field isolation layer 226, which is located under the inductive element 270, that is, the electromagnetic field isolation layer 226 is located between the inductive element 270 and the electronic element 212. The electromagnetic field isolation layer 226 can shield the inductive element 2 7 The electromagnetic field generated by 0 can reduce the degree to which the electromagnetic field generated by the inductive element 270 affects the electronic component 270. The structure of the inductance element 270 is selected from a composite layer composed of the following partial metals, titanium tungsten alloy, titanium nitrogen compound, titanium, chromium, copper, copper alloy, and copper, for example The metal structure of the inductance element 270 is, for example, a Chin layer and a copper layer formed from the bottom to the ground; or a Chin layer and a copper layer.

11786twf.ptd Page 18 1225288 V. Description of the invention (12) Layers and nickel layers are stacked from bottom to top; or titanium, copper, nickel and gold layers are stacked from bottom to top It is formed by stacking a titanium-tungsten alloy layer and a gold layer from bottom to top; or a stack of a titanium nitrogen compound layer and a gold layer from bottom to top. However, the structure of the inductive element 270 of the present invention is not limited to this, and the material of the inductive element 270 may also be made of aluminum or aluminum alloy. Referring to FIG. 9, after forming the inductive element 270 on the protective layer 230 as described above, an insulating layer 320 may be formed on the protective layer 230 by spin-coating, and the insulating layer 320 will cover the inductive element 270, thereby protecting the inductive element 270. Referring to FIG. 10, the inductive element 270 of the present invention may also be formed on the insulating layer 3 3 0 as described below. After forming the pad protection metal 2 40 on the pad 2 2 4 exposed by the protective layer opening 2 3 2, an insulating layer 330 may be formed on the protective layer 230 by spin-coating. After that, an inductive element 270 can be formed on the insulating layer 330. The insulating layer 3 3 0 has a plurality of openings 3 3 2, and the pad protection metal 2 4 0 is exposed, so that the inductive element 2 70 can be electrically connected to the pad protection metal 2 4 0 through the opening 3 3 2. The structure and material of the inductive element 270 are as described above, and will not be repeated here. A part of the wiring layer 2 2 0 can be connected to the outer boundary line of the conductor 3 1 0 through the protective layer 2 3 0 and the inductive element 2 7 0. Please refer to FIG. 11. After the inductive element 2 7 0 described in FIG. 10 is formed on the insulating layer 330, an insulating layer 3 4 0 may be formed on the insulating layer by spin-coating. 3 3 0, and the insulating layer 3 4 0 will cover the inductive element 2 7 0 to protect the inductive element 2 7 0. Insulation layer 3 4 0 has

11786twf.ptd Page 19 1225288 V. Description of the invention (13) Multiple openings 342, exposing the ends of the inductive element 270 The bump 3 1 3 outer line can be connected to the inductive element 2 7 f) Xi! ^ For example, on the υ < endpoint. Fourth Embodiment Figures 12 to 15 show cross-sectional schematic diagrams of the connection between the different chip structure and the capacitor element according to each # 1 embodiment of the fourth embodiment of the present invention. The embodiment is the same as the second preferred embodiment. The components specified in this embodiment of the embodiment are the same as those specified in the first meeting. # Y ^ ^ τ The preferred components are not described here. Superfluous. + 丄 = For example, the wafer structure 203 includes a capacitor element 280 in addition to the aforementioned substrate 2 1 0, the circuit 220, and the protective layer 230. Please refer to FIG. 12. The capacitor element 280 is directly formed on the protective layer 230. The capacitor element 280 includes two electrodes 282, 286 and a capacitor dielectric layer 284. The capacitor dielectric layer is located between the two electrodes. The two electrodes of the capacitor 280 are electrically connected to the pad protection metal 240. For related descriptions of capacitors, please refer to U.S. Patent Publication Nos. 6, 3, 03, 4, 2 3, 6, 455, 885, 6, 489, 647, 6, 489, 656, and No. No. 6, 515, 369, US Patent Application Nos. 10/445558, 10/445559, and 10/445560, etc., the concepts of the above patent cases can be applied to this case. The structure of the two electrodes 2 82 and 286 of the capacitor element 280 is selected from the composite consisting of the following metals, titanium tungsten alloys, titanium nitrogen compounds, titanium, chromium, copper, chromium copper alloys, nickel and gold. For example, the structure of the two electrodes 282 and 286 of the capacitor element 280 is, for example, a titanium layer and a copper layer from bottom to top.

11786t.wf.ptd Page 20 1225288 V. Description of the invention (14) Superimposed on the ground; Or superimposed on the titanium layer, copper layer and recording layer from the bottom up; Or superimposed on the titanium layer, The copper, nickel and gold layers are stacked from bottom to top; or the titanium alloy layer and gold layer are stacked from bottom to top; or the titanium nitrogen compound layer and gold layer are stacked from bottom to top Overlaid on the ground. However, the structure of the two-electrode 2 8 2, 2 8 2 of the capacitive element of the present invention is not limited to this, and the material of the two electrodes 282, 286 of the two capacitive element 280 may also be made of aluminum or alloy. The capacitor dielectric layer is made of, for example, one of the following materials: tetraethylorthosilicate (TEOS), oxygen stone compound, nitrogen silicon compound, nitrogen oxide compound, and pentoxide (T a 2 0 5 ), Titanate (S r T i 0 3), and barium titanate (BST). However, the application of the present invention is not limited to this, and the capacitor dielectric layer may also be a composite layer structure composed of the aforementioned partial materials. Please refer to FIG. 13. After forming the capacitor element 280 on the protective layer 230 as described above, an insulating layer 320 may be formed on the protective layer 230 by spin-coating and insulated. The layer 320 will cover the capacitive element 280, thereby protecting the capacitive element 280. Referring to FIG. 14, the capacitor element 280 of the present invention can also be formed on the insulating layer 3 3 0 as described below. After forming the pad protection metal 2 40 on the pad 2 2 4 exposed by the protective layer opening 2 3 2, an insulating layer 330 may be formed on the protective layer 230 by spin-coating. After that, a capacitor element 280 can be formed on the insulating layer 330. The insulating layer 3 3 0 has a plurality of openings 3 3 2, and the pad protection metal 2 4 0 is exposed, so that the capacitor element 2 80 can be electrically connected to the pad protection metal 2 4 0 through the opening 3 3 2. its

11786twf. Pt.d Page 21 1225288 5. In the description of the invention (15), the structure and material of the capacitor element 2 8 0 are as described above, and will not be repeated here. A part of the wiring of the circuit stack 220 may be connected to, for example, the outer wiring of the wire 3 10 through the protective layer 230 and the capacitor element 280. Referring to FIG. 15, after the capacitor element 2 8 0 described in FIG. 14 is formed on the insulating layer 330, an insulating layer 3 4 0 may be formed on the insulating layer by spin-coating. 3 3 0, and the insulating layer 3 4 0 will cover the capacitive element 2 8 0, thereby protecting the capacitive element 2 8 0. The insulating layer 3 4 0 has a plurality of openings 3 4 2, and the electrodes 2 8 6 of the capacitor element 2 8 0 are exposed, so that, for example, the outer boundary line of the bump 3 1 3 can be connected to the electrode 2 8 0 of the capacitor element. Fifth Embodiment Figures 16 to 19 show cross-sectional schematic diagrams of the connection between a chip structure and a resistive element according to a fifth preferred embodiment of the present invention, where the reference numerals in this embodiment correspond to the first embodiment or the second embodiment. If the preferred embodiment is the same, it means that the components specified in this embodiment are the same as those specified in the first embodiment or the second preferred embodiment, and will not be repeated here. In this embodiment, the wafer structure 204 includes a resistive element 290 in addition to the aforementioned substrate 210, the circuit stack 220, and the protective layer 230. Please refer to FIG. 16, the resistance element 290 is directly formed on the protective layer 230, and the resistance element 290 is electrically connected to the pad protection metal 440. For the related description of the resistance element, please refer to U.S. Patent Publication Nos. 6,303,423, 6,455,885, 6,489,647, 6,489,656, and 6,515,369. Patent Application No. 10/445558, No.

11786twf.ptd Page 22 1225288 V. Description of the Invention (16) Nos. 10/445559 and 10/445560, etc., the concepts of the above patent cases can be applied to this case. The material of the resistance element is, for example, aluminum, aluminum alloy, copper, copper alloy, nickel-chromium alloy, nickel-tin alloy, tantalum-nitrogen compound, tantalum, or town. Referring to FIG. 17, after forming the resistive element 290 on the protective layer 230 as described above, an insulating layer 320 may be formed on the protective layer 230 by spin-coating and insulated. The layer 320 will cover the resistive element 290, thereby protecting the resistive element 290. Referring to FIG. 18, the resistive element 290 of the present invention may also be formed on the insulating layer 3 30, as described below. After forming the pad protection metal 2 40 on the pad 2 2 4 exposed by the protective layer opening 2 3 2, an insulating layer 330 may be formed on the protective layer 230 by spin-coating. After that, a resistive element 290 can be formed on the insulating layer 330. The insulating layer 3 3 0 has a plurality of openings 3 3 2, and the pad protection metal 2 4 0 is exposed, so that the resistance element 2 90 can be electrically connected to the pad protection metal 2 40 through the opening 3 3 2. The structure and material of the resistance element 290 are as described above, and will not be repeated here. A part of the wiring of the layer 2 2 0 can be connected to the outer boundary line of the conductor 3 1 0 through the protective layer 2 3 0 and the resistance element 2 9 0. Referring to FIG. 19, after forming the resistive element 2 9 0 as described in FIG. 18 on the insulating layer 330, an insulating layer 3 4 0 can be formed on the insulating layer by spin-coating. 3 3 0, and the insulating layer 3 4 0 will cover the resistive element 2 9 0 to protect the resistive element 2 9 0. The insulating layer 3 4 0 has a plurality of openings 3 4 2 and exposes one end of the resistance element 290, so that, for example, the outer boundary line of the bump 3 1 3 can be connected to the end of the resistance element 290.

11786twf.ptd Page 23 1225288 V. Description of the invention (17) Sixth embodiment Figures 20 and 21 show the structure of the comparative film according to the present invention and the passive components that have been made in advance;

If the reference numerals in this embodiment are the same as those in the first embodiment or the second preferred embodiment, it means that the components specified in this embodiment are the same as those in the first embodiment or the second preferred embodiment. The specified components are repeated here. In this embodiment, the wafer structure 205 includes a passive component 300 that has been fabricated in addition to the aforementioned substrate 210, the circuit build-up layer 220, and the protective layer 230. Pavilion I Please refer to FIG. 20, “Passive element 300 that has been made in advance can be used to bond passive element 300 to the chip structure using surface adhesion technology.” On the passive element 30, such as inductive element, capacitor, etc. Components or resistances of 70 pieces, etc. The passive component 300 which has been pre-fabricated is provided by, for example, a passive component manufacturer. When the passive component factory is manufacturing a piece of 300, it is possible to first solder 3〇1. It is formed on the passive component 30 (), 302, 304, and the material of the solder 301 is, for example, a tin-lead alloy or a pot of tin-silver-copper alloy. Increase the bonding of solder 3 0 5 and pad protection metal 2 4 0 to form a fresh bonding metal 3 0 8 on pad protection metal 2 4 0, where the material of ^ 3 0 5 is, for example, tin-lead alloy Or other lead-free solders, such as tin-silver-steel alloys. Generally speaking, the solder joint metal 3 08 has a gold dissipation layer 3 07 to prevent the metal atoms of the solder 3 05 from diffusing into the circuit, In the circuit layer 2 2 2 of the layer 2 2 0, the metal diffusion barrier layer 3 〇7 ratio Is titanium,

11786twf.ptd Page 24 1225288

V. Description of the invention (18) The layer of gold is made up of copper and nickel layers. The layer is directly opened, and the copper layer is formed on the protective tank 2 40. The copper layer is formed on titanium. On the layer, the nickel layer is transferred to the copper layer and the titanium layer can also be replaced by a titanium alloy layer or a chromium layer. When the σ and titanium layers are used, a chromium-copper alloy layer can also be formed on the road layer and the spreading layer to increase the bonding between the chromium layer and the copper layer. θ 〃, 5 means that if the fresh material 3 0 5 is formed by printing, then a bonding layer 3 0 6 is formed on the metal diffusion barrier layer 30 7, that is, a H whisker 3 0 6 is formed to nickel On the layer, the bonding layer 3 0 6 must be composed of a material that is sufficient to bond the bonding layer 3 5 5, such as a gold layer, a steel layer 7 tin °, a fresh alloy layer, or a lead-free solder layer. It is printed on the stomach, and tin-lead is used to form solder 305 on the bonding layer 306. In addition, if the solder plating method is formed in the form of a solder 305, the preparation of the bonding layer 306 can be omitted. The solder 305 can be directly formed on the metal diffusion barrier layer 307 by electricity, g That is, the material 305 can be directly formed on the nickel layer. p is the solder element 300 formed on the solder joint metal 3 08, and when the movable element 300 is placed on the fresh material 305, the passive element 300 is placed on top of the material 3 0 1 Align the position of the solder 305, and then the solder 301 and 305 can be joined or fused with each other through the reflow step, and the passive component 3 0 0 can be combined with the wafer structure 2 〇〇 Engage firmly. For example, as described above, the structure of the solder-bonded metal and the method of bonding the passive components that have been fabricated in advance on the wafer structure can refer to the Republic of China _ Application No. 9 2 1 0 7 4 8 0, the concepts of this patent are all Please refer to Figure 21 for the benefit of this case.

11786twf.ptd Page 25 1225288 V. Description of the invention (19) 3 0 0 can also be formed on the insulating layer 3 3 0 as described below. After the pad shy metal 240 is formed on the junction 224 exposed by the protective layer opening 232, an insulating layer 33 can be formed on the retaining layer 2 3 0 by spin-coating. . After that, the passive component 3 00 that has been fabricated in advance can be connected to the insulating layer 3 3 0 by using surface adhesion technology. The insulating layer 3 3 0 has a plurality of openings 3 3 2, and the pad protection metal 2 4 0 is exposed, so that the passive component 3 0 0 can be electrically connected to the pad protection metal 2 4 0 through the opening 3 3 2. The structure and material of the passive component 300 and the passive component 300 are as described above, and will not be repeated here. Conclusion In the present invention, part of the lines of the line stack 2 2 0 can be connected to the passive elements 260, 270, 280, 290, 300 or the connection line 2 60 through the protective layer 230, and via the passive elements 260, 270, 280, 290, 300 or connection line 2 60, and then through the protective layer 2 3 0, can be connected to other parts of the circuit stack 220. Alternatively, part of the lines of the line stack 2 2 0 can also be connected to the passive elements 260, 270, 280, 290 or the connection line 2 0 through the protective layer 230, and via the passive elements 2 6 0, 2 7 0, 2 8 0, 2 9 0 or the connection line 2 60 is connected to, for example, a wire 3 10 or a bump 3 1 3 outside the line. In summary, since the material of the surface where the wire bonding metal 2 50 and the wire 3 3 0 contact is made of gold, and the material of the wire 3 3 0 is also gold, this is the bonding between the same metals. 'Therefore, the configuration of wire bonding wire 2 5 0 can greatly improve the bonding of wire bonding wire 3 1 0 and the chip.

H786twf .ptd

Page 26 1225288 V. Description of the invention (20) The jointability between the two structures. In addition, because the pad protection metal 2 40 and the bonding wire bonding metal 2 50 are stacked on the bonding pad, the total thickness of the stack is even lower. Therefore, when testing, the probe is less likely to pass through the bonding wire bonding metal. 2 5 0 and the pad protect the metal 2 4 0 and damage the material such as the copper pad 2 2 4, so the pad 2 2 4 can be prevented from being exposed to the air and oxidized. The re-formed pads are transferred to the oxide layer to form the protective layer 23. As for the layer, the capacitor element disturbs the pitch generated by the base 2 curren 2 700. Since the wafer is fabricated in the semiconductor factory, the metal can be protected. 2 4 0 is on a copper pad 2 2 4. Therefore, in the process of the wafer bump factory or the packaging factory, the image of the pad 224 can be avoided, and after the wafer is transferred to the bump factory or the packaging factory, You can also connect the line 260 or the passive components 270, 280, 290, and 300 to ensure that a high-performance chip structure 2000 can be produced. Example Since the capacitive element can be used? ^ Here, the distance from the substrate 2 and the inductive element 2 70 to the protective member 2 8 0 can be-to avoid maintaining a great distance, so the electronic-electric components 280 on the substrate 210 are stored. The electric charge dry bottom 2 1 0 keeps far away pieces 2 1 2; while the inductive element 2 70 ’s phase electromagnetic field on the silicon substrate 2′0 ′ can reduce the effect caused by the inductive element 2 7 0 t), so that it can be made. The eddy current (eddy makes an inductive element with high quality parameters) Although the present invention has been limited to the present invention with a better spirit, anyone familiar with this & ^ example is disclosed above, but it is not intended to be used within the scope. All kinds of changers shall be treated as attached patents and retouches without departing from the spirit and scope of the present invention. Therefore, what is defined in the isolation of the present invention shall prevail.

1225288 Brief Description of Drawings Figure 1 shows a schematic cross-sectional view of a structure in which a conventional wire is connected to a copper pad. Fig. 2 illustrates a cross-section of a wafer structure that can be used to connect wire bonding wires according to the first preferred embodiment of the present invention. 3 to 7 are schematic cross-sectional views showing the connection between a chip structure and a connection line according to a second preferred embodiment of the present invention. 8 to 11 are schematic cross-sectional views showing a connection between a wafer structure and an inductive element according to a third preferred embodiment of the present invention. FIG. 8A is a schematic top view of the inductor element in FIG. 8. Figures 12 to 15 are schematic cross-sectional views showing the connection between a chip structure and a capacitor element according to a fourth preferred embodiment of the present invention. 16 to 19 are schematic cross-sectional views showing a connection between a chip structure and a resistive element according to a fifth preferred embodiment of the present invention. Figures 20 and 21 are schematic cross-sectional views showing the connection between a wafer structure and a passive component that has been made in advance according to a sixth preferred embodiment of the present invention. [Illustration of diagrams] 100 chip 110 pad 120 protective layer 122 • protective layer opening 130 pad protective metal 140 wire 200 wafer structure 20 1 • wafer structure 202 wafer structure 203 • wafer structure 204 wafer structure 205 wafer structure 210 substrate 212 • Electronic components

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Schematic description of 214 Surface 220: Circuit layer 222 Circuit layer 224 • Pad 226 Electromagnetic field isolation layer 2 3 0: Protective layer 232 Protective layer open V 2 4 0: > Pad protective metal 250 Wire bonding wire bonding metal 260 Connection line 26 1 Circuit layer 262 Circuit layer 270 Inductive element 280 Capacitive element 282 Electrode 284 Capacitive dielectric layer 286 Electrode 290 Resistive element 300 Pre-made passive element 30 1 Solder 302: Contact 304 Contact 305 Material 306 bonding layer 307 metal diffusion barrier layer 308 solder bonding metal 310 wire conductor 313 bump 320 insulating layer 330 insulating layer 332 open V 340 insulating layer 342 open a 350 insulating layer 352 through hole 360 insulating layer 11786twf.ptd page 29

Claims (1)

1225288 VI. Scope of patent application 1 · A wafer structure suitable for connecting a plurality of wire bonding wires to the wafer structure using a wire-making process. The wafer structure includes at least: a substrate having a plurality of electronic components on one surface of the substrate A surface layer; located on the surface of the substrate, the circuit layer has a plurality of circuit layers, the circuit layers are electrically connected to each other, and the circuit layers are electrically connected to the electronic components, One of the circuit layers has a plurality of pads; a protective layer is located on the circuit build-up, and the protective layer has a plurality of protective layer openings penetrating the protective layer, and the protective layer openings expose the contacts.塾 A pad protection metal is located on the pads; and a bonding wire bonding metal is located on the pad protection metal, and the bonding wires are connected to the bonding wire bonding metal. '2. The wafer structure according to item 1 of the scope of the patent application, wherein the main materials of the circuit layers are copper and copper alloys, either one of which is selected. 3. The wafer structure according to item 1 of the scope of the patent application, wherein the main material of the pad protection metal is aluminum and aluminum alloy, one of which is selected. 4. The wafer structure according to item 1 of the scope of patent application, wherein the surface material of the bonding wire bonding metal and the bonding wire is gold. 5. The wafer structure according to item 1 of the scope of the patent application, wherein the structure of the wire bonding metal is selected from a composite layer composed of the following metals, titanium tungsten alloys, titanium nitrogen compounds, and gold. . 6 · The wafer structure described in item 1 of the scope of patent application, wherein the protection 11786twf .pt.d Page 30 1225288 VI. The scope of the patent application The structure of the protective layer is composed of at least one of the following materials: nitrogen silicon compound, oxygen silicon compound, nitrogen oxide silicon compound, and phosphosilicate glass. Layer structure. 7. The wafer structure according to item 1 of the scope of patent application, wherein the thickness of the protective layer is greater than 0.35 microns. 8. A wafer structure including at least: a substrate having a plurality of electronic components, a surface layer located on one surface of the substrate; a wiring layer, located on the surface of the substrate, the circuit layer having a plurality of circuit layers, the The circuit layers are electrically connected to each other, and the circuit layers are electrically connected to the electronic components. One of the circuit layers has a plurality of pads; a protective layer is located on the circuit layer, and The protective layer has a plurality of protective layer openings penetrating the protective layer, and the protective layer openings expose the pads; a pad protecting metal is located on the pads; and a connection line is located on the protective layer. The connection line is connected to the pad protection metal. 9. The wafer structure according to item 8 of the scope of the patent application, wherein the main materials of the circuit layers are copper and copper alloy, which is either one of them. 10. The wafer structure according to item 8 of the scope of the patent application, wherein the main material of the protection metal is an inscription and an inscription alloy, whichever is selected. 1 1. The wafer structure according to item 8 of the scope of patent application, wherein the structure of the connection line is selected from the group consisting of the following metals, titanium tungsten alloy, titanium nitrogen 11786twf.ptd Page 31 1225288 6. Scope of patent application Compound layer composed of compound, titanium, chromium, copper, chromium-copper alloy, nickel and gold. 1 2 · The wafer structure as described in item 8 of the scope of the patent application, wherein the material of the connection line is aluminum or aluminum alloy, either one of which is selected. 1 3 · The wafer structure according to item 8 of the scope of patent application, wherein a part of the circuit stack is connected to the connection line through the protection layer, and then connected to the connection line through the protection layer and the protection layer. The other parts of the circuit stack. 1 4. The chip structure according to item 8 of the scope of the patent application, wherein the connection line is a power bus and a ground bus, either of which is selected. 1 5. The wafer structure according to item 8 of the scope of patent application, further comprising an insulating layer between the connection line and the protective layer. 16. The wafer structure according to item 15 of the scope of the patent application, wherein the material of the insulating layer is selected from the group consisting of polyimide, phenylcyclobutene, polyarylene ether, and porous dielectric materials. A material in the group of elastomers. 1 7 · The wafer structure described in item 8 of the scope of patent application, further comprising an insulating layer on the connection line. 1 8. The wafer structure according to item 17 of the scope of the patent application, wherein the material of the insulating layer is selected from the group consisting of polyimide, phenylcyclobutene, polyarylene ether, and porous dielectric materials. A material in the group of elastomers. 19. The wafer structure according to item 8 of the scope of patent application, wherein the maximum measurable width of the protective layer openings is between 0.1 μm and 20 μm. 11786twf.ptd Page 32 1225288 6. The scope of patent application. 20. The chip structure according to item 8 of the scope of patent application, wherein a wire bonding process is adapted to connect at least one wire bonding wire to the connection line. 2 1. The wafer structure according to item 8 of the scope of the patent application, wherein the structure of the protective layer is a composite composed of at least one of the following materials, nitrogen silicon compound, oxygen silicon compound, nitrogen oxide silicon compound, and phosphosilicate glass. Layer structure or single layer structure. 2 2. · The wafer structure according to item 8 of the scope of patent application, wherein the thickness of the protective layer is greater than 0.35 microns. 2 3. The wafer structure according to item 8 of the scope of patent application, wherein the connection line is a single-layer circuit layer structure. 2 4. The wafer structure according to item 8 of the scope of patent application, further comprising at least one insulating layer on the protective layer, and the connecting line is a structure of a plurality of circuit layers, and the insulating layer is located on the circuits Between these layers, the circuit layers are electrically isolated. 2 5. A wafer structure including at least: a substrate having a plurality of electronic components, a surface layer on one surface of the substrate; a circuit layer on the surface of the substrate, the circuit layer having a plurality of circuit layers, The circuit layers are electrically connected to each other, and the circuit layers are electrically connected to the electronic components. One of the circuit layers has a plurality of pads; a protective layer is located on the circuit layer, In addition, the protective layer has a plurality of protective layer openings. Through the protective layer, the protective layer openings expose the protective layer. 11786twf.ptd Page 33 1225288 VI. Patent application scopes Some pads; a pad protects the genus on the pads; and a passive element on the protective layer, the passive element and the pad Protect metal electrical connections. 26. The wafer structure described in item 25 of the scope of patent application, wherein the main material of these circuit layers is copper and copper alloy, either one of which is selected. 27. The wafer structure according to item 25 of the scope of patent application, wherein the main material of the pad protection metal is aluminum and aluminum alloy, which is either one of them. 28. The chip structure according to item 25 of the patent application scope, wherein the passive element is a capacitor element. 29. The wafer structure according to item 28 of the scope of patent application, wherein the capacitor element has two electrodes and a capacitor dielectric layer, and the capacitor dielectric layer is located between the two electrodes. 30. The wafer structure according to item 29 of the scope of the patent application, wherein the structure of at least one of the two electrodes is selected from the group consisting of the following metals, titanium hafnium alloy, titanium nitrogen compound, titanium, chromium, copper , Chrome-copper alloy, aluminum alloy, and gold. 3 1. The wafer structure described in item 29 of the scope of patent application, wherein the material of at least one of the two electrodes is aluminum and aluminum alloy, both of which are-0 3 2. As the scope of patent application scope 2 9 The chip structure described in the above item, wherein the material of the capacitor dielectric layer is tetraethane-based oxysiloxane (TEOS), oxysilicone compound, nitrogen broken compound, nitrogen broken compound, pentoxide, titanate And barium titanate, one of the seven. 11786twf.ptd Page 34 1225288 6. Scope of patent application 3 3 · The wafer structure described in item 29 of the patent application scope, wherein the capacitor dielectric layer is a composite layer composed of the following materials, these materials Including TEOS, TEOS, NOS, NOS, pentoxide, osmium titanate and barium osmium titanate. 3 4. The wafer structure according to item 25 of the patent application scope, wherein the passive element is a resistance element. 35. The wafer structure as described in item 34 of the scope of patent application, wherein the material of the resistance element is aluminum, aluminum alloy, copper, copper alloy, nickel-chromium alloy, tin alloy, nitrogen compound, sister and crane Choose one of the nine. 36. The chip structure according to item 25 of the patent application scope, wherein the passive element is an inductive element. 37. The wafer structure according to item 36 of the scope of the patent application, wherein the structure of the inductance element is selected from the group consisting of the following metals, titanium hafnium alloy, titanium nitrogen compound, titanium, chromium, copper, and chromium-copper alloy. , Recording and gold, a composite layer. 38. The wafer structure according to item 36 of the scope of patent application, wherein the material of the inductance element is aluminum or aluminum alloy, which is either one of them. 39. The wafer structure according to item 25 of the scope of patent application, further comprising a solder bonding metal on the pad protection metal, and the passive component is bonded to the solder bonding metal through a rod. 40. The wafer structure according to item 39 of the scope of the patent application, wherein the material of the surface layer of the solder bonding metal in contact with the solder is a metal capable of bonding with the solder. 41. The wafer structure described in item 40 of the scope of patent application, wherein 11786twf.ptd Page 35 1225288 Sixth, the scope of the patent application The material of the surface layer of the solder joint metal in contact with the solder is one selected from the group consisting of gold, copper, nickel, tin, tin-lead alloy and lead-free solder . 4 2 · The wafer structure according to item 39 of the scope of the patent application, wherein the solder bonding metal system includes a metal diffusion barrier layer and a bonding layer, and the metal diffusion barrier layer is located on the connection protection metal. The bonding layer is located on the metal diffusion barrier layer, and the passive component is bonded to the bonding layer of the solder bonding metal by a solder. 4 3. The wafer structure according to item 42 of the scope of the patent application, wherein the structure of the metal diffusion barrier layer is selected from the group consisting of the following metals, titanium-tungsten alloy, titanium, copper, copper, copper-copper alloy and , The combined composite layer. 44. The wafer structure according to item 42 of the scope of the patent application, wherein the material of the bonding layer is a material selected from the group consisting of gold, copper, nickel, tin, tin alloy, and lead-free solder. . 4 5. The wafer structure according to item 25 of the patent application scope further comprises an insulating layer between the passive element and the protective layer. 46. The wafer structure according to item 45 of the scope of patent application, wherein the material of the insulating layer is selected from the group consisting of polyimide, phenylcyclobutene, polyarylene ether, and porous dielectric materials. A material in the group of elastomers. 47. The wafer structure according to item 25 of the patent application scope, further comprising an insulating layer on the passive element. 48. The wafer structure according to item 47 of the scope of patent application, wherein the material of the insulating layer is selected from the group consisting of polyimide, phenylcyclobutene, and polyarylene. 11786twf.ptd Page 36 1225288 6. Scope of patent application One of the materials in the group consisting of aryl ether, porous dielectric material and elastomer. 49. The wafer structure according to item 25 of the patent application scope, wherein the maximum measurable width of the protective layer openings is between 0.1 micrometers and 20 micrometers. 50. The chip structure according to item 25 of the scope of patent application, wherein a wire bonding process is adapted to electrically connect at least one wire bonding wire to the passive element. 51. The wafer structure as described in item 25 of the scope of the patent application, wherein the structure of the protective layer is composed of at least one of the following materials, nitrogen silicon compound, oxygen silicon compound, nitrogen oxide silicon compound, and phosphosilicate glass. Composite layer structure or single layer structure. 52. The wafer structure according to item 25 of the scope of patent application, wherein the thickness of the protective layer is greater than 0.35 micrometers. 53. The chip structure described in item 25 of the scope of patent application, wherein a part of the circuit stack is connected to the passive element through the protective layer, and then connected to the passive element through the protective layer through the protective layer. The other layers of the circuit are stacked. 54. The chip structure according to item 25 of the scope of the patent application, wherein a part of the circuit stack is connected to an external circuit through the protective layer and the passive component. 11786t.wf.ptd Page 37