KR101067106B1 - Wafer level package and method for manufacturing thereof - Google Patents

Abstract

The present invention relates to a wafer level package (WLP) capable of improving the bonding reliability between a metal pad formed by rearranging chip pads and a ball bump, and a method of manufacturing the same.

A wafer level package of the present invention includes a semiconductor substrate having a plurality of integrated circuits and a plurality of chip pads on an upper surface thereof, a first passivation layer exposing the chip pads, and a plurality of chip pads passing through the first passivation layer. A via connected to the via, a metal wiring layer formed on the first passivation layer including the via to be connected to the via, an under bump metal electrically connected to the metal wiring layer on one side of the first passivation layer, and the metal wiring layer A second passivation layer provided to expose the under bump metal on the substrate, a protruding buffer pattern formed on the under bump metal, and the under bump metal on which the buffer pattern protrudes from the under bump metal It may include a ball bump provided to be connected.

Wafer Level Package, Under Bump Metal, Buffer Pattern, Ball Bump

Description

Wafer level package and its manufacturing method {WAFER LEVEL PACKAGE AND METHOD FOR MANUFACTURING THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer level package and a method of manufacturing the same, and more particularly, a wafer level package (WLP) capable of improving the bonding reliability between metal pads formed by rearranging chip pads and ball bumps. And a method for producing the same.

As electronic products are gradually reduced in size, weight, speed, and high capacity, there is a demand for development of semiconductor packages having a new structure that can cope with the development direction of electronic products in semiconductor packages. Among the semiconductor packages introduced to date, a semiconductor package that is most suitable for light weight reduction and high speed is known as a wafer level package (WLP).

A wafer level package refers to a package that proceeds without separating a semiconductor chip from a wafer.

1 is a cross-sectional view illustrating a typical wafer level chip scale package.

Referring to FIG. 1, a wafer level chip scale package includes a silicon substrate 100 including a chip pad 110 and a passivation layer 120 for protecting the chip pads 110. Is provided.

In addition, an insulating layer 130 (hereinafter referred to as a first insulating layer) is formed on the upper surface of the silicon substrate 100 to have a predetermined thickness so that the chip pad 110 is exposed. The metal wiring layer 140 and the ball pad unit 150 are formed to be connected to the chip pad 110 and rearrange the chip pad 110.

In addition, the second insulating layer 160 covering the first insulating layer 130 and the metal wiring layer 140 on the metal wiring layer 140 and the ball pad part 150 and exposing a part of the ball pad part 150 is exposed. ) Is formed.

In addition, a circular solder ball 170 is formed in the ball pad part 150 exposed by the second insulating layer 160.

 However, in general wafer-level packages manufactured at the wafer level, when solder balls are mounted, cracks occur at the interface between the ball pad portion and the solder balls to increase resistance, and when the resistance is severe, open phenomenon occurs to increase the reliability of the device. There was a problem falling.

A technique for improving the soldering defect of such solder balls has been disclosed under the title "two ball bumps" in Japanese Patent No. 3975569 filed and registered by SONY CORP.

The above-mentioned "two ball bumps" refer to a first solder ball bump made of high melting point solder formed on an electrode pad of a semiconductor device, and a second solder overlapping the first solder ball bump at least in a direction perpendicular to the electrode pad. It is comprised by the ball bump, and the thermal stress between a semiconductor device and a printed wiring board is alleviated, and the strength of a junction part is raised.

However, this technique has a disadvantage of causing an increase in chip size and an increase in processing steps as solder balls are formed in multiple layers.

In addition, as the area of the solder ball is increased, parasitic capacitances formed in the substrate, the insulating layer, and the ball pad are increased, thereby lowering the signal transmission speed.

The present invention is to solve the above problems, an object of the present invention is to form a stress relief buffer pattern on the under bump metal used as a ball pad to improve the bonding reliability between the ball bump and the under bump metal, under bump The present invention provides a wafer-level package and a method of manufacturing the same, which minimize the parasitic capacitance generated between the chip pad and the ball bump through the metal and metal wiring layers to improve the electrical characteristics.

A wafer level package of the present invention for achieving the above object is a semiconductor substrate having a plurality of integrated circuits and a plurality of chip pads on its upper surface, a first passivation layer exposing the chip pads, and the first passivation layer A via connected to the chip pad through the via, a metal wiring layer formed to be connected to the via on the first passivation layer including the via, and an under bump electrically connected to the metal wiring layer on one side of the first passivation layer. The second passivation layer provided to expose the under bump metal on the metal wiring layer, the protruding buffer pattern formed on the under bump metal, and the under bump metal on which the buffer pattern protrudes. It may include a ball bump provided in electrical connection with the under bump metal.

According to an aspect of the present invention, the buffer pattern may be formed in an annular shape formed around the upper portion of the under bump metal.

The buffer pattern may further include a circular shape formed at the center of the upper part of the under bump metal, a radial shape formed in the outer diameter direction from the center of the upper part of the under bump metal, or further include an auxiliary annular shape formed inside the annular shape. can do.

In addition, the wafer level package manufacturing method of the present invention for achieving the above object comprises the steps of preparing a semiconductor substrate having a plurality of semiconductor chips and chip pads, and a first passivation layer on a semiconductor substrate comprising the chip pad Forming a via, patterning the first passivation layer to form a via exposing the chip pad, forming a metal wiring layer and an under bump metal on the first passivation layer including the via; Forming a second passivation layer that opens an under bump metal region and a buffer pattern provided on the under bump metal; And forming a ball bump on the under bump metal including the buffer pattern.

In this case, the second passivation layer and the buffer pattern forming step may simultaneously form a buffer pattern when the under bump metal region is opened.

In addition, the ball bumps may be formed by any one of plating, stencil printing, ball placement, or metal jet.

According to the present invention, it is possible to improve the bonding reliability by reducing the contact resistance between the ball bump and the under bump metal used as the ball pad, and to improve the electrical reliability by preventing the increase of parasitic capacitance between the ball bump and the chip pad. Can be.

Details of the configuration of the wafer level package and the method of manufacturing the wafer level package according to the present invention will be clearly understood by the following detailed description with reference to the drawings in which preferred embodiments of the present invention are shown.

Example

2 to 7 are process diagrams sequentially showing a method of manufacturing a wafer level package according to an embodiment of the present invention.

First, as shown in FIG. 2, in the method of manufacturing a wafer level package according to the present invention, a semiconductor substrate 10 having a chip pad 12 is provided.

In this case, the semiconductor substrate 10 includes predetermined integrated circuits (not shown) formed through a general substrate manufacturing process.

In addition, the chip pad 12 may be electrically connected to an integrated circuit formed on the semiconductor substrate 10. For example, the chip pad 12 may be formed of an aluminum layer.

Referring to FIG. 3, the first passivation layer 14 is formed on the semiconductor substrate 10 having the chip pads 12.

The first passivation layer 14 is to protect the integrated circuits and the chip pad 12 in the semiconductor substrate 10 from the external environment. For example, the first passivation layer 14 may be a silicon oxide film (SiO ₂ ) or a silicon nitride film (SiN). have.

Referring to FIG. 4, a predetermined patterning process is performed on the first passivation layer 14 to form vias 16 exposing the chip pads 12. In this case, the patterning process may be performed through a photo process and an etching process.

Referring to FIG. 5, (a) is a cross-sectional view and (b) is a plan view of a main portion, forming a metal wiring layer 18 for rearranging the chip pads 12, but under bump metal in the exposed via 16 region. A metal wiring layer 18 is formed up to the (under bump metal) 20 region.

In this case, the metal wiring layer 18 may be formed simultaneously with the chip pad 12 region and the under bump metal 20 region, or may be formed separately through each photolithography process.

In addition, the metal wiring layer 18 may be deposited through a process such as sputtering, chemical vapor deposition (CD) or plating, and may be a single layer of copper (Cu) or aluminum (Al), or several metals. The multilayer structure may be stacked.

Although not shown in the drawing, before forming the metal wiring layer 18, a metal base layer (not shown) that functions as an adhesive layer, a diffusion barrier layer, and a plating base layer of the metal wiring layer 18 may be further formed.

At this time, the metal base layer (not shown) includes titanium / copper (Ti / Cu), titanium tungsten / copper (TiW / Cu), aluminum / nickel / copper (Al / Ni / Cu), aluminum / nickel vanadium / copper (Al / NiV / Cu) may be used.

Referring to FIG. 6, (a) is a cross-sectional view, (b) is a plan view of a main portion, and a second passivation layer 22 for protecting the metal wiring layer 18 and opening the under bump metal 20. ) And a buffer pattern 24 provided on the under bump metal 20.

In this case, the buffer pattern 24 may be formed separately from the under bump metal 20 opening process, or may be simultaneously formed during the under bump metal 20 opening process.

Referring to FIG. 7, (a) is a cross-sectional view, (b) is a plan view of a main portion, and the ball bumps 26 are formed on the under bump metal 20 on which the buffer pattern 24 is formed.

At this time, the ball bump 26 is a ball placement method for bonding the ball bump 26 on the under bump metal 20 by providing and reflowing the ball bump 26 on the under bump metal 20 It may be formed by, or by plating, stencil printing, or metaljet.

Accordingly, the ball bumps 26 are electrically connected to the chip pads 12 through the metal material of the under bump metal 20 and the metal wiring layer 18.

As described above, the present invention forms a stress relief buffer pattern 24 in this region prior to forming the ball bumps 26 on the under bump metal 20 according to a characteristic aspect. The resistance is reduced by reducing the interface crack between the bumps 26 and the under bump metal 20.

As a result, not only the joint reliability is improved by preventing the open phenomenon caused by the resistance of the ball bumps 26 and the under bump metal 20, but the size of the solder balls is increased in order to increase the contact area. Since there is no increase, it is possible to solve the problem of a decrease in signal transmission speed due to an increase in parasitic capacitance.

8 to 11 are plan views illustrating various shapes of the buffer patterns illustrated in FIGS. 6 and 7.

The buffer pattern 24 has a single annular shape formed around the under bump metal region A as shown in FIG. 8, or as shown in FIG. 9. ) May have an annular shape around the region A and may be formed in a circular shape at the center thereof.

Alternatively, the buffer pattern 24 may be formed in an annular shape around the under bump metal region A as shown in FIG. 10 and radially formed in the outer diameter direction from the center, or as shown in FIG. 11. As described above, the circumference and the inner side may be formed in a double annular structure having an annular shape, and the shape of the buffer pattern of the present invention is not limited thereto and may be modified through various embodiments.

Preferred embodiments of the present invention described above are disclosed for the purpose of illustration, and various substitutions, modifications, and changes within the scope without departing from the spirit of the present invention for those skilled in the art to which the present invention pertains. It will be possible, but such substitutions, changes and the like should be regarded as belonging to the following claims.

1 is a cross-sectional view of a typical wafer level chip scale package.

2 to 7 are process diagrams showing in sequence the wafer level package manufacturing method according to an embodiment of the present invention.

8 to 11 are plan views illustrating various shapes of the buffer pattern illustrated in FIGS. 6 and 7.

Description of the Related Art [0002]

10 semiconductor substrate 12 chip pad

14: first passivation layer 16: via

18: metal wiring layer 20: under bump metal

22: second passivation layer 24: buffer pattern

26: ball bump

Claims (8)

A semiconductor substrate having a plurality of integrated circuits and a plurality of chip pads on an inner surface thereof; A first passivation layer exposing the chip pads; A via penetrating the first passivation layer and connected to the chip pad; A metal wiring layer formed to be connected to the via on a first passivation layer including the via; An under bump metal electrically connected to the metal wiring layer on one side of the first passivation layer; A second passivation layer provided to expose the under bump metal on the metal wiring layer; A protruding buffer pattern formed on the under bump metal, wherein the buffer pattern is formed in an annular shape formed around an upper portion of the under bump metal and further includes an auxiliary annular shape formed inside the annular shape; And A ball bump provided on the buffer pattern to protrude from the under bump metal to be electrically connected to the under bump metal; Wafer level package comprising a. delete The method of claim 1, The buffer pattern further comprises a circular shape formed at a central portion of the under bump metal. The method of claim 1, The buffer pattern further comprises a radial shape formed in the outer diameter direction from the center of the upper portion of the under bump metal. delete Preparing a semiconductor substrate on which a plurality of semiconductor chips and chip pads are formed; Forming a first passivation layer on the semiconductor substrate including the chip pads; Patterning the first passivation layer to form a via exposing the chip pad; Forming a metal interconnection layer and an under bump metal on the first passivation layer including the vias; A second passivation layer that opens the under bump metal region and a buffer pattern provided on the under bump metal-The buffer pattern is formed in an annular shape formed around an upper portion of the under bump metal, and is formed in the annular shape. Further comprising an annular shape; And Forming a ball bump on an under bump metal including the buffer pattern; Wafer level package manufacturing method comprising a. The method of claim 6, Forming the second passivation layer and the buffer pattern; A wafer level package manufacturing method for simultaneously forming a buffer pattern when the under bump metal region is opened. The method of claim 6, The ball bump is a wafer-level package manufacturing method is formed by any one of plating, stencil printing, ball placement (ball placement) or metal jet (metal jet) method.

Images