CN102148203A - 半导体芯片以及形成导体柱的方法 - Google Patents

半导体芯片以及形成导体柱的方法 Download PDF

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CN102148203A
CN102148203A CN2011100352543A CN201110035254A CN102148203A CN 102148203 A CN102148203 A CN 102148203A CN 2011100352543 A CN2011100352543 A CN 2011100352543A CN 201110035254 A CN201110035254 A CN 201110035254A CN 102148203 A CN102148203 A CN 102148203A
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width
bond pad
passivation layer
conductor pin
resilient coating
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CN102148203B (zh
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陈志华
陈承先
郭正铮
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了一种半导体芯片以及一种形成导体柱的方法。该半导体芯片包含一钝化层，该钝化层具有位于基板上的一金属接触开口。一接合焊垫，具有位于金属接触开口内的一第一部分以及一位于钝化层上方的一第二部分。接合焊垫的第二部分具有一第一宽度。接合焊垫上有一缓冲层，其具有一第二宽度的一柱体接触开口以暴露接合焊垫的一部分。一导体柱，具有位于柱体接触开口内的一第一部分以及位于缓冲层上方的一第二部分。导体柱的第二部分具有一第三宽度。第二宽度与第一宽度的比在约0.35至0.65之间。第二宽度与第三宽度的比在约0.35至0.65之间。

Description

半导体芯片以及形成导体柱的方法
技术领域
本发明关于半导体凸块制程，特别关于一种形成导体柱凸块的结构和方法。
背景技术
覆晶技术在半导体装置的封装过程中扮演非常重要的角色。覆晶微电子组装包括使用焊锡凸块作为连接将倒装电子组件直接电性连接至基板上，例如电路板。由于覆晶在尺寸、性能以及适应性方面超越其它封装方法的优势，使得覆晶封装的使用大幅增长。
近年来，导体柱技术已取得长足进步。将焊锡凸块的使用取而代之的是借助铜柱把电子组件连接至基板。铜柱技术实现了具有更低凸块桥接可能性的更细间距，降低了电路的电容负载以及允许电子组件在更高的频率下运作。
然而，标准的柱体制造制程有一些不足之处。举例来说，标准导体柱制造程序会在微电子组装中产生导致破裂的压力。破裂会蔓延至芯片里下层的电子组件。破裂会损害或损毁电子组件，这样就提高了整个组装的不合格率。
有鉴于此，需要一个改进的结构和方法来制作用于半导体芯片的具有优良电子性能的导体柱。
发明内容
本发明的目的在于提供一种半导体芯片，以避免上述现有技术的一个或多个不足。
本发明的另一目的在于提供一种形成导体柱的方法，以调节标准柱体制作制程中的一个或多个不足之处。
本发明所揭露的一实施例包含具有导体柱的一半导体芯片。所述半导体芯片包括：一基板；一第一钝化层，具有在基板上方的一金属接触开口；一接合焊垫，具有位于金属接触开口内的一第一部分以及在钝化层上方的一第二部分，接合焊垫的第二部分具有一第一宽度；一缓冲层，沉积在接合焊垫上，缓冲层具有一第二宽度的一柱体接触开口，以此来暴露接合焊垫的一部分；以及一导体柱，具有位于柱体接触开口内的一第一部分以及在缓冲层上方的一第二部分，该导体柱的第二部分具有一第三宽度。第二宽度与第一宽度的比在约0.35至0.65之间。第二宽度与第三宽度的比在约0.35至0.65之间。
本发明所揭露的另一实施例包含具有一导体柱的一半导体芯片。一基板。一第一钝化层，具有位于基板上的一金属接触开口。一接合焊垫，具有一第一部分和一第二部分。第一部分位于金属接触开口内。第二部分位于第一钝化层上方，且具有一第一宽度。一第二钝化层位于第一钝化层上，部分覆盖接合焊垫，并留有一暴露的接合焊垫表面。一缓冲层位于第二钝化层以及一部分接合焊垫的第二部分上。缓冲层具有一第二宽度的柱体接触开口，位于一部分暴露的接合焊垫表面上。一导体柱，具有一第一部分和一第二部分。第一部分位于缓冲层的柱体接触开口内。第一部分上方的第二部分具有一第三宽度。第二宽度与第一宽度的比在约0.35至0.65之间。第二宽度与第三宽度的比在约0.35至0.65之间。
本发明所揭露的另一实施例包含一形成导体柱的方法。所述方法包括：提供一基板；在基板上形成一钝化层，钝化层具有一金属接触开口；在钝化层上形成一接合焊垫，接合焊垫具有位于金属接触开口内的一第一部分、以及在第一部分上方的具有一第一宽度的一第二部分；在接合焊垫上形成一缓冲层，缓冲层具有一第二宽度的柱体接触开口，用以部分暴露接合焊垫的第二部分；以及形成一导体柱，用以覆盖开口以及置于一部分缓冲层上，导体柱具有一第三宽度。第二宽度与第一宽度的比在约0.35至0.65之间。第二宽度与第三宽度的比在约0.35至0.65之间。
本发明的一些实施例用于调节标准柱体制作制程的不足之处。举例来说，一些实施例可降低组装制程中产生的压力并且减少导致产量降低的破裂蔓延。
附图说明
参见展示实施例的附图详细阐释本发明，应理解的是附图仅作示意之用，因此并未按比例绘制：
图1绘示了半导体基板的剖视图；
图2绘示了在图1中所示的基板的表面形成的具有一金属接触开口的一第一钝化层；
图3绘示了在第一钝化层上形成一接合焊垫；
图4绘示了在第一钝化层上形成一第二钝化层并覆盖一部分接合焊垫；
图5绘示了在第二钝化层上形成一缓冲层并覆盖一部分接合焊垫；
图6绘示了在缓冲层上形成的一导体柱；
图7绘示了半导体基板接合于一半导体组件；以及
图8绘示了制作导体柱的方法的流程图。
主要附图标记说明
101：基板
103：内连层
105：导电层
107：绝缘层
109：第一钝化层
111：金属接触开口
113：接合焊垫
113a：接合焊垫第一部分
113b：接合焊垫第二部分
115：宽度
117：第二钝化层
119：开口
121：宽度
123：缓冲层
125：柱体接触开口
127：宽度
129：导体柱
129a：导体柱第一部分
129b：导体柱第二部分
133：宽度
135：半导体组件
201至207：制程步骤
具体实施方式
以下将详细讨论例举实施例的制作与使用。然而应理解的是，本揭露内容提供的众多可行发明概念能够在许多特定情况下体现。讨论的实施例仅作为例举之用，并非用以限定本发明。
图1至图7是根据本发明一实施例在一基板上制作导体柱的各个阶段的剖视图。图8绘示了制作导体柱的方法200的流程图。其中“基板”通常指的是一半导体基板，各种沉积层和集成电路在其上形成。基板可包含硅或复合半导体，例如砷化镓(GaAs)、磷化铟(InP)、硅/锗(Si/Ge)、或碳化硅(SiC)。沉积层的例子包含介电层、掺杂层、金属层、多晶硅层，通过插塞可将一层与另一层或更多层相连接。集成电路的例子包含晶体管、电阻和/或电容。
请参照图1与图8，在制程步骤201中，提供一基板101。在基板101上形成一内连层103。内连层103包含排布于一或多个介电层107内的一或多个导电层105。在集成电路上形成导电层105是用以电性连接集成电路和上层。介电层107的形成可使用，举例来说，介电常数(k值)在约2.9和3.8之间的低k介电材料，k值在约2.5和2.9之间的超低k介电材料，低k介电材料的组合等等。随着k值的降低，介电层107变得更脆弱且易剥离和破裂。
请参照图2与图8，在制程步骤202中，在内连层103上形成一第一钝化层109以保护集成电路和内连层103免于损伤和污染。形成一金属接触开口111以暴露导电层105的一部分。在一实施例中，形成金属接触开口111的制程包括在内连层103上沉积第一钝化层109，用蚀刻定义金属接触开口111。第一钝化层109可以是一层或更多层，所包含的材料为，举例来说，氧化物、未掺杂的硅玻璃(undoped silicate glass，USG)、氮化硅(SiN)，二氧化硅(SiO2)或氮氧化硅(SiON)。钝化层109的厚度可在约0.6μm和约1.4μm之间。第一钝化层109可防止或降低水气、机械和辐射对集成电路造成的损伤。
请参照图3与图8，在制程步骤203中，在第一钝化层109上形成一接合焊垫113。接合焊垫113具有位于金属接触开口111内的一第一部分113a以及位于第一钝化层109上方的一第二部分113b。第二部分113b具有一宽度115。接合焊垫113接触导电层105并向下层集成电路提供电性连接。在一实施例中，接合焊垫113可包含一导电材料，比如铝、铝合金、铜、铜合金或其组合。接合焊垫113的沉积可使用物理气相沉积(physical vapor deposition，PVD)，比如使用铝、铜或其合金制作的溅镀靶材的溅镀沉积，接着用微影和蚀刻定义接合焊垫113的沉积层。
请参照图4与图8，在制程步骤204中，在第一钝化层109和接合焊垫113上形成一第二钝化层117。第二钝化层117的形成可使用与第一钝化层109类似的方式和材料。第一钝化层109和第二钝化层117可选择性的使用互不相同的材料来形成。第二钝化层117可使用传统的沉积技术沉积至第一钝化层109和接合焊垫113上，例如化学气相沉积(chemical vapor deposition，CVD)。沉积之后使用微影和蚀刻来选择性地在接合焊垫113上定义一开口119。第二钝化层117部分覆盖接合焊垫113，并在开口119内留有一暴露的接合焊垫113的表面。开口119具有一小于宽度115的宽度121。第二钝化层117可吸收或释放由封装基板引起的热量或机械压力。
请参照图5与图8，在制程步骤205中，在第二钝化层117和接合焊垫113上形成一缓冲层123。缓冲层123包含厚度在约2μm和约10μm之间的聚酰亚胺，一氧化铅(PBO)或环氧树脂。缓冲层123涂布在第二钝化层117上并填充开口119以覆盖接合焊垫113的第二部分113b的暴露表面。缓冲层123作为压力缓冲来降低在组装制程中传递至第一钝化层109和第二钝化层117的压力。接着进行微影和图案化用以在接合焊垫113上选择性的定义一柱体接触开口125。柱体接触开口125在接合焊垫113的暴露的表面上具有一宽度127。
请参照图6与图8，在制程步骤206中，在缓冲层123上形成一导体柱129。导体柱129具有位于柱体接触开口125内的一第一部分129a以及位于缓冲层123上的一第二部分129b。第二部分129b具有一宽度133。宽度133为约55μm至约130μm。导体柱129具有一高度，从第一部分129a的底部算起，高度为约35μm至约55μm。导体柱129藉由接合焊垫113电性连接内连层103，并向下层集成电路提供电性连接。在一实施例中，导体柱129包含一导电材料，比如铜或铜合金。导体柱129可使用电镀形成，以填充缓冲层123上的图案化的光阻层(未绘示)的开口。在电镀制程后将光阻层去除。在缓冲层123上形成多个导体柱(未绘示)。导体柱与相邻导体柱间形成一间距，该间距为约125μm至约250μm。
可接受的组装产量与两个比例有关。一第一比例是宽度127与宽度115的比。一第二比例是宽度127与宽度133的比。宽度127与宽度115的第一比例在约0.35至约0.65之间。宽度127与宽度133的第二比例在约0.35至约0.65之间。举例来说，如比例低于0.35，组装的不合格率将上升。当宽度127很小时，导体柱129与接合焊垫113的不良接触概率将更高。如比例高于0.65，第二钝化层117在组装制程中将破裂。举例来说，当宽度127很大时，缓冲层123将无法降低组装制程中传递至接合焊垫113的压力。届时，压力会从接合焊垫113扩散至第二钝化层117。脆弱的第二钝化层117会变得易剥离和破裂。
请参照图7与图8，在制程步骤207中，使用图6中所示的导体柱129将半导体基板101与一半导体组件135接合。在一实施例中，半导体组件135可为一半导体芯片，承载基板，电路板或任何熟习此技艺者熟知的合适组件。半导体基板101和半导体组件135可藉由导体柱129电性连接。接合方法包括铜-铜接合，焊接接合或任何熟习此技艺者熟知的合适方法。
虽然本发明及其优势已详细描述，然其应理解的是，在不脱离本发明的精神和范围内，依照本发明的权利要求当可作各种的更动与润饰。各实施例的制程、机器、制品和物的组合、方式、方法和步骤并非用以限定本发明的范围。本领域普通技术人员可轻易理解本发明揭露内容，利用现有或即将发展的制程、机器、制品和物的组合、方式、方法或步骤，产生对应于本发明实施例的相同的功能和结果。因此，所附权利要求包括在其范围内的制程、机器、制品和物的组合、方式、方法或步骤。

Claims (10)

1.一种半导体芯片，包含：
一基板；
一第一钝化层，具有位于该基板上的一金属接触开口；
一接合焊垫，具有位于该金属接触开口内的一第一部分以及位于该钝化层上方的一第二部分，该接合焊垫的第二部分具有一第一宽度；
一缓冲层，位于该接合焊垫上，该缓冲层具有一第二宽度的一柱体接触开口以暴露该接合焊垫的一部分；以及
一导体柱，具有位于该柱体接触开口内的一第一部分以及位于该缓冲层上方的一第二部分，该导体柱的第二部分具有一第三宽度，其中该第二宽度与该第一宽度的比在约0.35至约0.65之间，该第二宽度与该第三宽度的比在约0.35至约0.65之间。
2.根据权利要求1所述的半导体芯片，还包含：
一第二钝化层，位于该第一钝化层上方，部分覆盖该接合焊垫并留有一暴露的接合焊垫表面。
3.根据权利要求2所述的半导体芯片，其中该第一钝化层及该第二钝化层至少包含氧化物、未掺杂的硅玻璃、氮化硅和氮氧化硅其中之一者。
4.根据权利要求2所述的半导体芯片，其中该第二钝化层具有一第四宽度的一开口以暴露该接合焊垫，该第四宽度宽于该第三宽度，该第三宽度为约35μm至约55μm。
5.根据权利要求1所述的半导体芯片，还包含在该半导体基板上方和该第一钝化层下方形成的一内连层，其中该导体柱藉由该接合焊垫电性连接该内连层，该导体柱包含铜。
6.根据权利要求1所述的半导体芯片，其中该缓冲层包含聚酰亚胺。
7.根据权利要求1所述的半导体芯片，其中该导体柱与一相邻导体柱间的间距为约125μm至约250μm。
8.一种形成导体柱的方法，包含：
提供一基板；
形成一第一钝化层在该基板上，该第一钝化层具有一金属接触开口；
形成一接合焊垫在该钝化层上，该接合焊垫具有位于该金属接触开口内的一第一部分以及在第一部分上方的具有一第一宽度的一第二部分；
形成一缓冲层在该接合焊垫上，该缓冲层具有一第二宽度的一柱体接触开口，用以部分暴露该接合焊垫的第二部分；以及
形成一导体柱，用以覆盖该开口以及置于一部分该缓冲层上，该导体柱具有一第三宽度，
其中，该第二宽度与该第一宽度的比在约0.35至约0.65之间，该第二宽度与该第三宽度的比在约0.35至约0.65之间。
9.根据权利要求8所述的方法，还包含：
形成一第二钝化层在该第一钝化层上方，部分覆盖该接合焊垫并留有一暴露的接合焊垫表面，其中该第二钝化层具有一第四宽度的一开口以暴露该接合焊垫，该第四宽度窄于该第三宽度；以及
在该导体柱与一相邻导体柱间形成一间距，该间距为约125μm至约250μm。
10.根据权利要求9所述的方法，其中该第一钝化层及该第二钝化层至少包含氧化物、未掺杂的硅玻璃、氮化硅和氮氧化硅其中之一者，该缓冲层包含聚酰亚胺，该导体柱包含铜，该导体柱藉由该接合焊垫电性连接一内连层。
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CN103515254A (zh) * 2012-06-20 2014-01-15 英飞凌科技股份有限公司 芯片布置组件及用于形成芯片布置组件的方法
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CN108461411A (zh) * 2017-02-21 2018-08-28 华邦电子股份有限公司 封装结构
CN108461411B (zh) * 2017-02-21 2020-10-27 华邦电子股份有限公司 封装结构
CN110729179A (zh) * 2019-10-30 2020-01-24 华虹半导体(无锡)有限公司 智能卡芯片的加工方法及智能卡芯片
CN110767556A (zh) * 2019-10-30 2020-02-07 华虹半导体(无锡)有限公司 智能卡芯片的加工方法及智能卡芯片

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