TWI421994B - 用於半導體基板的導體柱結構以及製造方法 - Google Patents

用於半導體基板的導體柱結構以及製造方法 Download PDF

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TWI421994B
TWI421994B TW100103911A TW100103911A TWI421994B TW I421994 B TWI421994 B TW I421994B TW 100103911 A TW100103911 A TW 100103911A TW 100103911 A TW100103911 A TW 100103911A TW I421994 B TWI421994 B TW I421994B
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width
passivation layer
bonding pad
layer
conductor post
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TW201128754A (en
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Chihhua Chen
Chenshien Chen
Chencheng Kuo
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Taiwan Semiconductor Mfg
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Description

用於半導體基板的導體柱結構以及製造方法
本發明係關於半導體凸塊製程，特別係關於一種形成導體柱凸塊的結構和方法。
覆晶技術在半導體裝置的封裝過程中扮演非常重要的角色。覆晶微電子組裝包括使用焊錫凸塊作為連接將倒裝電子元件直接電性連接至基板上，例如電路板。由於覆晶在尺寸、性能以及適應性方面超越其他封裝方法的優勢，使得覆晶封裝的使用大幅增長。
近年來，導體柱技術已取得長足進步。將焊錫凸塊的使用取而代之的是借助銅柱把電子元件連接至基板。銅柱技術實現了具有更低凸塊橋接可能性的更細間距，降低了電路的電容負載以及允許電子元件在更高的頻率下運作。
然而，標準的柱體製造製程有一些不足之處。舉例來說，標準導體柱製造程式會在微電子組裝中產生導致破裂的壓力。破裂會蔓延至晶片裏下層的電子元件。破裂會損害或損毀電子元件，這樣就提高了整個組裝的不良率。
有鑒於此，需要一個改進的結構和方法來製作用於半導體晶片的具有優良電子性能的導體柱。
本發明所揭露的一實施例包含具有導體柱的一半導體晶片。一基板。一鈍化層，具有在基板上方的一金屬接觸開口。一接合焊墊，具有位於金屬接觸開口內的一第一部分以及在鈍化層上方的一第二部分。接合焊墊的第二部分具有一第一寬度。一緩衝層沉積在接合焊墊上。緩衝層具有一第二寬度的一柱體接觸開口，以此來暴露接合焊墊的一部分。一導體柱，具有位於柱體接觸開口內的一第一部分以及在緩衝層上方的一第二部分。該導體柱的第二部分具有一第三寬度。第二寬度與第一寬度之比在約0.35至0.65之間。第二寬度與第三寬度之比在約0.35至0.65之間。
本發明所揭露的另一實施例包含具有一導體柱的一半導體晶片。一基板。一第一鈍化層，具有位於基板上的一金屬接觸開口。一接合焊墊，具有一第一部分和一第二部分。第一部分位於金屬接觸開口內。第二部分位元於第一鈍化層上方，且具有一第一寬度。一第二鈍化層位於第一鈍化層上，部分覆蓋接合焊墊，並留有一暴露的接合焊墊表面。一緩衝層位於第二鈍化層以及一部分接合焊墊的第二部分上。緩衝層具有一第二寬度的柱體接觸開口，位於一部分暴露的接合焊墊表面上。一導體柱，具有一第一部分和一第二部分。第一部分位於緩衝層的柱體接觸開口內。第一部分上方的第二部分具有一第三寬度。第二寬度與第一寬度之比在約0.35至0.65之間。第二寬度與第三寬度之比在約0.35至0.65 之間。
本發明所揭露的另一實施例包含一形成導體柱的方法。提供一基板。在基板上形成一鈍化層。鈍化層具有一金屬接觸開口。在鈍化層上形成一接合焊墊。接合焊墊具有一第一部分，位於金屬接觸開口內，以及在第一部分上方的具有一第一寬度的一第二部分。在接合焊墊上形成一緩衝層，緩衝層具有一第二寬度的柱體接觸開口，用以部分暴露接合焊墊的第二部分。形成一導體柱，用以覆蓋開口以及置於一部分緩衝層上，導體柱具有一第三寬度。第二寬度與第一寬度之比在約0.35至0.65之間。第二寬度與第三寬度之比在約0.35至0.65之間。
本發明的一些實施例用於調節標準柱體製作製程的不足之處。舉例來說，一些實施例可降低組裝製程中產生的壓力並且減少導致產量降低的破裂蔓延。
以下將詳細討論例舉實施例的製作與使用。然而應理解的是，本揭露內容提供的衆多可行發明概念能夠在許多特定情況下體現。討論的實施例僅作為例舉之用，並非用以限定本發明。
第1圖至第7圖是根據本發明一實施例在一基板上製作導體柱的各個階段的剖視圖。第8圖繪示了製作導體柱的方法200的流程圖。其中“基板”通常指的是一半導體基板，各種沉積層和集積電路在其上形成。基 板可包含矽或複合半導體，例如砷化鎵(GaAs)、磷化銦(InP)、矽/鍺(Si/Ge)、或碳化矽(SiC)。沉積層的例子包含介電層、摻雜層、金屬層、多晶矽層，通過插塞可將一層與另一層或更多層相連接。集積電路的例子包含晶體管、電阻和/或電容。
請參照第1圖與第8圖，在製程步驟201中，提供一基板101。在基板101上形成一內連層103。內連層103包含排布於一或多個介電層107內的一或多個導電層105。在集積電路上形成導電層105是用以電性連接集積電路和上層。介電層107的形成可使用，舉例來說，介電常數(k值)在約2.9和3.8之間的低k介電材料，k值在約2.5和2.9之間的超低k介電材料，低k介電材料的組合等等。隨著k值的降低，介電層107變得更脆弱且易剝離和破裂。
請參照第2圖與第8圖，在製程步驟202中，在內連層103上形成一第一鈍化層109以保護集積電路和內連層103免於損傷和污染。形成一金屬接觸開口111以暴露導電層105的一部分。在一實施例中，形成金屬接觸開口111的製程包括在內連層103上沉積第一鈍化層109，用蝕刻定義金屬接觸開口111。第一鈍化層109可以是一層或更多層，所包含的材料為，舉例來說，氧化物、未摻雜的矽玻璃(undoped silicate glass,USG)、氮化矽(SiN)，二氧化矽(SiO2 )或氮氧化矽(SiON)。鈍化層109的厚度可在約0.6μm和約1.4μm之間。第一鈍化層109可防止或降低水氣、機械和輻射 對集積電路造成的損傷。
請參照第3圖與第8圖，在製程步驟203中，在第一鈍化層109上形成一接合焊墊113。接合焊墊113具有位於金屬接觸開口111內的一第一部分113a以及位於第一鈍化層109上方的一第二部分113b。第二部分113b具有一寬度115。接合焊墊113接觸導電層105並向下層集積電路提供電性連接。在一實施例中，接合焊墊113可包含一導電材料，比如鋁、鋁合金、銅、銅合金或其組合。接合焊墊113的沉積可使用物理氣相沉積(physical vapor deposition，PVD)，比如使用鋁、銅或其合金製作的濺鍍靶材的濺鍍沉積，接著用微影和蝕刻定義接合焊墊113的沉積層。
請參照第4圖與第8圖，在製程步驟204中，在第一鈍化層109和接合焊墊113上形成一第二鈍化層117。第二鈍化層117的形成可使用與第一鈍化層109類似的方式和材料。第一鈍化層109和第二鈍化層117可選擇性的使用互不相同的材料來形成。第二鈍化層117可使用傳統的沉積技術沉積至第一鈍化層109和接合焊墊113上，例如化學氣相沉積(chemical vapor deposition，CVD)。沉積之後使用微影和蝕刻來選擇性地在接合焊墊113上定義一開口119。第二鈍化層117部分覆蓋接合焊墊113，並在開口119內留有一暴露的接合焊墊113的表面。開口119具有一小於寬度115的寬度121。第二鈍化層117可吸收或釋放由封裝基板引起的熱量或機械壓力。
請參照第5圖與第8圖，在製程步驟205中，在第二鈍化層117和接合焊墊113上形成一緩衝層123。緩衝層123包含厚度在約2μm和約10μm之間的聚醯亞胺，一氧化鉛(PBO)或環氧樹脂。緩衝層123塗布在第二鈍化層117上並填充開口119以覆蓋接合焊墊113的第二部分113b的暴露表面。緩衝層123作為壓力緩衝來降低在組裝製程中傳遞至第一鈍化層109和第二鈍化層117的壓力。接著進行微影和圖案化用以在接合焊墊113上選擇性的定義一柱體接觸開口125。柱體接觸開口125在接合焊墊113的暴露的表面上具有一寬度127。
請參照第6圖與第8圖，在製程步驟206中，在緩衝層123上形成一導體柱129。導體柱129具有位於柱體接觸開口125內的一第一部分129a以及位於緩衝層123上的一第二部分129b。第二部分129b具有一寬度133。寬度133為約55μm至約130μm。導體柱129具有一高度，從第一部分129a的底部算起，高度為約35μm至約55μm。導體柱129藉由接合焊墊113電性連接內連層103，並向下層集積電路提供電性連接。在一實施例中，導體柱129包含一導電材料，比如銅或銅合金。導體柱129可使用電鍍形成，以填充緩衝層123上的圖案化的光阻層(未繪示)的開口。在電鍍製程後將光阻層去除。在緩衝層123上形成多個導體柱(未繪示)。導體柱與相鄰導體柱間形成一間距，該間距為約125μm至約250μm。
可接受的組裝產量與兩個比例有關。一第一比例是寬度127與寬度115之比。一第二比例是寬度127與寬度133之比。寬度127與寬度115的第一比例在約0.35至約0.65之間。寬度127與寬度133的第二比例在約0.35至約0.65之間。舉例來說，如比例低於0.35，組裝的不良率將上升。當寬度127很小時，導體柱129與接合焊墊113的不良接觸概率將更高。如比例高於0.65，第二鈍化層117在組裝製程中將破裂。舉例來說，當寬度127很大時，緩衝層123將無法降低組裝製程中傳遞至接合焊墊113的壓力。屆時，壓力會從接合焊墊113擴散至第二鈍化層117。脆弱的第二鈍化層117會變得易剝離和破裂。
請參照第7圖與第8圖，在製程步驟207中，使用第6圖中所示的導體柱129將半導體基板101與一半導體元件135接合。在一實施例中，半導體元件135可為一半導體晶片，承載基板，電路板或任何熟習此技藝者熟知的合適元件。半導體基板101和半導體元件135可藉由導體柱129電性連接。接合方法包括銅-銅接合，焊接接合或任何熟習此技藝者熟知的合適方法。
雖然本發明及其優勢已詳細描述，然其應理解的是，在不脫離本發明之精神和範圍內，依照本發明之權利要求當可作各種之更動與潤飾。各實施例的製程、機器、製品和物之組合、方式、方法和步驟並非用以限定本發明的範圍。熟習本領域之技藝者可輕易理解本發明揭露內容，利用現有或即將發展的製程、機器、製品和 物之組合、方式、方法或步驟，產生對應於本發明實施例的相同的功能和結果。因此，所附權利要求包括在其範圍內的製程、機器、製品和物之組合、方式、方法或步驟。
101‧‧‧基板
103‧‧‧內連層
105‧‧‧導電層
107‧‧‧絕緣層
109‧‧‧第一鈍化層
111‧‧‧金屬接觸開口
113‧‧‧接合焊墊
113a‧‧‧接合焊墊第一部分
113b‧‧‧接合焊墊第二部分
115‧‧‧寬度
117‧‧‧第二鈍化層
119‧‧‧開口
121‧‧‧寬度
123‧‧‧緩衝層
125‧‧‧柱體接觸開口
127‧‧‧寬度
129‧‧‧導體柱
129a‧‧‧導體柱第一部分
129b‧‧‧導體柱第二部分
133‧‧‧寬度
135‧‧‧半導體元件
201至207‧‧‧製程步驟
參見展示實施例的附圖詳細闡釋本發明，應理解的是附圖僅作示意之用，因此並未按比例繪製：第1圖繪示了半導體基板的剖視圖；第2圖繪示了在第1圖中所示的基板的表面形成的具有一金屬接觸開口的一第一鈍化層；第3圖繪示了在第一鈍化層上形成一接合焊墊；第4圖繪示了在第一鈍化層上形成一第二鈍化層並覆蓋一部分接合焊墊；第5圖繪示了在第二鈍化層上形成一緩衝層並覆蓋一部分接合焊墊；第6圖繪示了在緩衝層上形成的一導體柱；第7圖繪示了半導體基板接合於一半導體元件；以及第8圖繪示了製作導體柱的方法的流程圖。
101．．．基板
105．．．導電層
107．．．絕緣層
109．．．第一鈍化層
113a．．．接合焊墊第一部分
113b．．．接合焊墊第二部分
117．．．第二鈍化層
123．．．緩衝層
129．．．導體柱
129a．．．導體柱第一部分
129b．．．導體柱第二部分
135．．．半導體元件

Claims (10)

  1. 一種半導體晶片，包含：一基板；一第一鈍化層，具有位於該基板上的一金屬接觸開口；一接合焊墊，具有位於該金屬接觸開口內的一第一部分以及位於該鈍化層上方的一第二部分，該接合焊墊的第二部分具有一第一寬度；一緩衝層，位於該接合焊墊上，該緩衝層具有一第二寬度的一柱體接觸開口以暴露該接合焊墊的一部分；以及一導體柱，具有位於該柱體接觸開口內的一第一部分以及位於該緩衝層上方的一第二部分，該導體柱的第二部分具有一第三寬度，其中該第二寬度與該第一寬度之比在約0.35至約0.65之間，該第二寬度與該第三寬度之比在約0.35至約0.65之間。
  2. 如請求項1所述之半導體晶片，更包含：一第二鈍化層，位於該第一鈍化層上方，部分覆蓋該接合焊墊並留有一暴露的接合焊墊表面。
  3. 如請求項2所述之半導體晶片，該第一鈍化層及 該第二鈍化層至少包含氧化物、未摻雜的矽玻璃(undoped silicate glass，USG)、氮化矽和氮氧化矽其中之一者。
  4. 如請求項2所述之半導體晶片，其中該第二鈍化層具有一第四寬度的一開口以暴露該接合焊墊，該第四寬度寬於該第三寬度，該第三寬度為約35μm至約55μm。
  5. 如請求項1所述之半導體晶片，更包含在該半導體基板上方和該第一鈍化層下方形成的一內連層，其中該導體柱藉由該接合焊墊電性連接該內連層，該導體柱包含銅。
  6. 如請求項1所述之半導體晶片，其中該緩衝層包含聚醯亞胺。
  7. 如請求項1所述之半導體晶片，其中該導體柱與一相鄰導體柱間的間距為約125μm至約250μm。
  8. 一種形成導體柱的方法，包含：提供一基板； 形成一第一鈍化層在該基板上，該第一鈍化層具有一金屬接觸開口；形成一接合焊墊在該鈍化層上，該接合焊墊具有位於該金屬接觸開口內的一第一部分以及在第一部分上方的具有一第一寬度的一第二部分；形成一緩衝層在該接合焊墊上，該緩衝層具有一第二寬度的一柱體接觸開口，用以部分暴露該接合焊墊的第二部分；以及形成一導體柱，用以覆蓋該開口以及置於一部分該緩衝層上，該導體柱具有一第三寬度，其中，該第二寬度與該第一寬度之比在約0.35至約0.65之間，該第二寬度與該第三寬度之比在約0.35至約0.65之間。
  9. 如請求項8所述之方法，更包含：形成一第二鈍化層在該第一鈍化層上方，部分覆蓋該接合焊墊並留有一暴露的接合焊墊表面，其中該第二鈍化層具有一第四寬度的一開口以暴露該接合焊墊，該第四寬度窄於該第三寬度；以及在該導體柱與一相鄰導體柱間形成一間距，該間距為約125μm至約250μm。
  10. 如請求項9所述之方法，其中該第一鈍化層及該第二鈍化層至少包含氧化物、未摻雜的矽玻璃(undoped silicate glass，USG)、氮化矽和氮氧化矽其中之一者，該緩衝層包含聚醯亞胺，該導體柱包含銅，該導體柱藉由該接合焊墊電性連接一內連層。
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