TWI429040B - 半導體結構及半導體裝置的製造方法 - Google Patents

半導體結構及半導體裝置的製造方法 Download PDF

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TWI429040B
TWI429040B TW099111223A TW99111223A TWI429040B TW I429040 B TWI429040 B TW I429040B TW 099111223 A TW099111223 A TW 099111223A TW 99111223 A TW99111223 A TW 99111223A TW I429040 B TWI429040 B TW I429040B
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Taiwan
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pillar
layer
substrate
mask pattern
solder
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TW099111223A
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TW201126672A (en
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Yao Chun Chuang
Chen Cheng Kuo
Ching Wen Hsiao
Chen Shien Chen
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Taiwan Semiconductor Mfg
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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Description

半導體結構及半導體裝置的製造方法
本發明係有關於一種半導體裝置，特別是有關於一種用於半導體裝置的導電立柱(post)。
過去幾十年來電子及半導體封裝所呈現出的許多變化已影響了整個半導體工業。首先介紹的表面黏著技術(surface mount technology,SMT)及球柵陣列(ball grid array,BGA)對於廣泛的各種積體電路(integrated circuit,IC)裝置的高產率組件(high-throughput assembly)來說是重要的技術手段，且同時其能夠容許縮短印刷電路板上接墊的間距。傳統上，封裝積體電路的結構中係透過位於晶片上金屬接墊與延伸至模製樹脂封裝體外側的電極之間的微細金線作為基本的內連接。雙列式封裝(dual inline package,DIP)或四方扁平封裝(quad flat package,QFP)為現今IC封裝的基礎架構。然而，增加封裝體周圍引腳總數的設計及排列通常造成引腳導線的間距過短，而在封裝晶片的插件裝配中產生許多限制。
晶片級封裝(chip scale/size packing,CSP)或球柵陣列(BGA)封裝為一些解決之法，其能夠使電極排列緊密而無需大幅增加封裝體的尺寸。一些CSP技術具有額外的好處，其能夠進行晶片級的晶圓封裝。CSP的封裝尺寸通常在晶片尺寸的1.2倍以內，其大幅縮小由CSP材料所製成的裝置的尺寸。
一些CSP或BGA封裝藉由焊料凸塊(bump)作為晶片上的接觸點與基底(如，封裝基板或印刷電路板(printed circuit board,PCB))上的接觸點之間的電性連接。其他CSP或BGA封裝利用將一焊球或凸塊放置於凸塊電極或立柱(post)上，藉由焊點接合維持結構完整性。組成內連接的不同膜層通常具有不同的熱膨脹係數(coefficient of thermal expansion,CTE)。如此一來，時常在凸塊電極/立柱與焊球/凸塊之間的接墊區域內形成裂縫。
本發明揭示一種具有T型立柱的半導體裝置及其製造方法。T型立柱具有底層凸塊金屬化(UBM)部及延伸自UBM部的一柱體部。UBM部及柱體部可由相同或不同的材料所構成。在一實施例中，一具有T型立柱的第一基底與一第二基底的接觸窗接合。舉例而言，第一基底可為晶片、晶圓、印刷電路板、封裝基底等等，且第二基底可為晶片、晶圓、印刷電路板、封裝基底等等。T型立柱可具有一焊料預先形成於柱體部上，使柱體部露出來或使焊料覆蓋柱體部。在另一實施例中，T型立柱可形成於一基底上，而焊料則形成於另一基底上。
本發明亦揭示其他的實施例。
以下說明本發明實施例之製作與使用。然而，可輕 易了解本發明實施例提供許多合適的發明概念而可實施於廣泛的各種特定背景。所揭示的特定實施例僅僅用於說明以特定方法製作及使用本發明，並非用以侷限本發明的範圍。
以下所述的實施例係關於具有T型立柱的凸塊結構的使用。如以下所述，實施例中採用上述結構以將一基底貼附於另一基底，其中每一基底可為晶片、晶圓、印刷電路板、封裝基板等等，而能夠進行晶片對晶片、晶圓對晶片、晶圓對晶圓、或晶圓對印刷電路板或封裝基底等等的貼附。以下所述的各個不同實施例中，相同的標號係用於表示相同的部件。
請參照第1圖，其繪示出根據一實施例之一基底102的一部分具有複數T型立柱104形成於內。舉例而言，基底102可包括矽塊材基底、摻雜或未摻雜基底、或是絕緣層上覆矽(silicon on insulator,SOI)基底的一主動(active)層。一般來說，SOI基底包括一層半導體材料，例如矽，其形成於一絕緣層上。舉例而言，絕緣層可為埋入式氧化(buried oxide,BOX)層或氧化矽層。絕緣層係位於一基底上，其通常為矽基底或玻璃基底。同時也可使用其他的基底，例如多層式基底或漸變式基底。
形成於基底102上的電路106可為用於特定應用的任何型式電路。在一實施例中，電路106包括形成於基底102上的電子裝置，基底106具有一層或多層的介電層位於電子裝置上方。介電層之間可形成金屬層，以進行電子裝置之間電子信號的佈線。電子裝置也可形成於 一層或多層介電層內。
舉例而言，電路106可包括各種內連接的N型金屬氧化物半導體(NMOS)及/或P型金屬氧化物半導體(PMOS)裝置，例如電晶體、電容、電阻、二極體、光電二極體、熔絲等等，用以執行一或多重功能。這些功能包括記憶體結構、處理結構、感測器、放大器、電源分佈、輸入/輸出電路等等。所屬技術領域中具有通常知識者可以瞭解的是上述因闡述目的所提供範例僅用於進一步解釋某些實施例的應用，而非用於限定本發明。對於已知的應用來說，也可使用其他適用的電路。
在第1圖中也繪示出一內層介電(inter-layer dielectric,ILD)層108。舉例而言，內層介電(ILD)層108包括了低介電常數(low-k)材料，例如磷矽玻璃(phosphosilicate glass,PSG)、硼磷矽玻璃(borophosphosilicate glass,BPSG)、氟矽玻璃(fluorinated silicate glass,FSG)、SiOx Cy 、旋塗玻璃(spin-on-glass)、旋塗高分子材料(spin-on-polymers)、碳化矽材料、其化合物、其複合材、其組合物等等，其透過習知適當的方法製造而成，例如旋塗法、化學氣相沉積(chemical vapor deposition,CVD)法、及電漿輔助化學氣相沉積(plasma-enhanced CVD,PECVD)法。需注意的是內層介電(ILD)層108可包括複數介電層。
接觸窗(contact)，例如接觸窗110，係形成且穿過內層介電層108內，以作為電路106的電性接觸。舉例而言，接觸窗110的製作可先透過微影技術在內層介電 層108上沉積及圖案化一光阻材料以露出用於形成接觸窗110的內層介電層108部分。使用一蝕刻製程，例如非等向乾蝕刻製程，以在內層介電層108內形成開口。開口內可形成一擴散阻障襯層及/或一黏著層(未繪示)並填入一導電材料。在一實施例中，擴散阻障襯層包括一或多層的TaN、Ta、TiN、Ti、CoW等等，且導電材料包括銅、鎢、鋁、銀及其組合，藉以形成第1圖所示的接觸窗110。
一層或多層金屬層間介電(inter-metal dielectric,IMD)層112及相關的金屬化層(未繪示)係形成於內層介電層108上。一般來說，一層或多層金屬層間介電層112及相關的金屬化層係用於電路106彼此的內連接且提供外部電路的電性連接。金屬層間介電層112可由低介電常數材料所構成，例如由PECVD技術或高密度電漿化學氣相沉積(high-density plasma CVD,HDPCVD)等技術所形成的氟矽玻璃(FSG)且可包括中間蝕刻終止層。接觸窗114形成於頂層金屬層間介電層內，以提供外部電性連接。
需注意的是一或多層蝕刻終止層(未繪示)可位於相鄰的介電層(例如ILD層108及IMD層112)之間。一般來說，蝕刻終止層於形成介層窗(via)及/或接觸窗時，提供一停止蝕刻製程的機制。蝕刻終止層由介電材料所構成且與相鄰的膜層(例如下方的半導體基底102、上方的ILD層108、及上方的IMD層112)之間具有不同的蝕刻選擇比。在一實施例中，蝕刻終止層可由SiN、 SiCN、SiCO、CN、其組合等等所構成，且透過CVD或PECVD等技術而形成。
於頂層IMD層112的表面上形成且圖案化一保護層116，例如聚亞醯胺(polyimide)材料，以提供接觸窗114一接觸位置並保護下方的膜層而避免各種環境汙染源。之後，於保護層116上形成且圖案化一導電層118。導電層118提供上方用於外部連接的接觸凸塊的電性連接。導電層118已可作為引腳或球佈局所需的重佈局線層(redistribution layer,RDL)。導電層118可由任何適當的導電材料所構成，例如銅、鎢、鋁、銀及其組合等等。
於導電層118上形成且圖案化一鈍化(passivation)層120，例如聚亞醯胺材料，且於鈍化層120的開口上方形成T型立柱104，如第1圖所示。T型立柱104可由適當的導電材料所構成，例如Cu、Ni、Pt、Al、AlCu、W、CuSn、AuSn、InAu、PbSn等等，且與導電層118作電性接觸。以下有更詳細的說明。T型立柱104可透過沉積一種子層(未繪示於第1圖中)並使用電鍍技術來製作。
所屬技術領域中具有通常知識者將可以瞭解的是以上提供一般實施例的特徵部件說明，然而實施例中也可具有其他眾多的特徵部件。例如，其他電路、襯層(liner)、阻障層、底層凸塊金屬化層等等。以上所述僅提供於此處所述的實施例背景且並未限定本說明或是這些特定實施例任何所要保護的範圍。
請參照第2圖，其繪示出根據一實施例之T型立柱104連接於一第二基底202(例如封裝基底、印刷電路板 (PCB)、晶片、晶圓等等)之後，其中相同的部件係使用相同的標號。如第2圖所示，第二基底202包括一導電接觸窗204。在第二基底202上形成且圖案化一綠漆(solder mask)206，例如一聚亞醯胺層，使導電接觸窗204能形成電性連接。
為了便於探討，T型立柱104包括一底層凸塊金屬化(under-bump metallization,UBM)部208及一柱體部210。在一實施例中，柱體部210的寬度W1 與底層凸塊金屬化(UBM)部208的寬度W2 的比率(W1 /W2 )約在0.2至0.75的範圍。已發現的是具有上述比率的T型立柱在接合至第二基底202後提供了延展性焊料對於T型立柱的高模數材料(例如，Cu)的一適當比率。
在一實施例中，綠漆206內的開口具有一寬度W3 ，其容許T型立柱104的柱體部210的寬度W1 能夠置入綠漆206內的開口，使T型立柱104延伸過綠漆206的上表面(如第2圖的虛線212所示)。在本實施例中，綠漆206的寬度W3 大於T型立柱104的寬度W1 (W3 >W1 )。
第2圖也繪示出焊料216及介金屬化合物(inter-metallic compound,IMC)層218。在焊接期間，IMC自然地形成一膜層，例如IMC層218，其位於焊料216與相鄰表面(例如，T型立柱104及/或導電接觸窗204)之間的接點。IMC層218的存在表示焊料與相鄰材料之間具有良好的焊接。在一實施例中，T型立柱104的柱體部210係置入於綠漆206的開口內，使IMC層218完全地佔據柱體部210與第二基底202的導電接觸窗204 之間的空間。在此方式中，導電接觸窗204、IMC層218、柱體部210、及UBM部208形成一H型連接體而容許大部份的電流經由IMC層218及柱體部210而通過UBM部208與導電接觸窗204之間。在一實施例中，焊料216包括SnPb、高鉛材料、錫基焊料、無鉛焊料或其他適當的導電材料。
第3A至3C圖係繪示出不同的T型立柱104型式，其可使用於各種晶圓形式以及將第一基底102貼附於第二基底202的準備程序中，第二基底202基底可為晶片、晶圓、電路板、封裝基板等等。請先參照第3A圖，T型立柱104並無焊料直接與其貼附。確切來說，在本實施例中，第二基底202具有焊料216而位於欲貼附的T型立柱104上。
在第3B圖中，焊料直接放置於第一基底102上方的T型立柱104上。在本實施例中，由於焊料已形成於T型立柱104上，且其在本實施例中穿過焊料216而顯露出來，因此焊料216不需位於第二基底202上。
在第3C圖中，其繪示出相似於第3B圖的實施例。然而，在本實施例中，T型立柱104被焊料216所覆蓋。
第4至9圖係繪示出形成第3A圖所示的T型立柱的中間步驟。首先請參照第4圖，提供具有各種膜層、結構、張置等等的基底102，如第1圖所示，其中相同部件係使用相同的標號。可使用任何適當的製程來形成上述結構，此處將不再做詳細的說明。因此，所提供的基底102具有一鈍化層120，其圖案化後露出下方部分的導電 層118。
之後，如第4圖所示，一順應性晶種層410沉積於鈍化層120的表面上。晶種層410為導電材料所構成的一薄層，其有助於在後續製程步驟中形成較厚的膜層在一實施例中，晶種層410可透過CVD或物理氣相沉積(physical vapor deposition,PVD)技術來沉積一薄導電層而形成，例如由Cu、Ti、Ta、TiN、TaN、其組合等等所構成的薄層。舉例而言，透過PVD製程沉積一Ti層而形成一阻障層以及透過PVD製程沉積一Cu層而形成一晶種層。
之後，請參照第5圖，其繪示出根據一實施例之於晶種層410上方形成一第一罩幕圖案層510。第一罩幕圖案層510定義出T型立柱104(請參閱第2圖)的UBM部208的外型，如以下所述。第一罩幕圖案層510可為光阻罩幕圖案層、硬式罩幕(hard mask)、其組合等等。
第6圖係繪示出根據一實施例之形成T型立柱104的UBM部208。UBM部208可由任何適當的導電材料所構成，包括Cu、Ni、Pt、Al、其組合等等，且透過任何適當的技術而形成，例如PVD、CVD、電化學沉積(electrochemical deposition,ECD)、分子束磊晶(molecular beam epitaxy,MBE)、原子層沉積(atomic layer deposition,ALD)、電鍍(electroplating)等等。需注意的是在一些實施例中，例如在晶圓的整個表面上沉積(例如，PVD及CVD)一順應性層，且也可進行蝕刻或平坦化製程(例如，化學機械研磨(chemical mechanical polishing,CMP))，以去除第一罩幕圖案層510表面上多餘的導電材料。在一實施例中，UBM部208的厚度約在2微米(μm)至20微米的範圍。
第7圖係繪示出根據一實施例之於第一罩幕圖案層510上形成一第二罩幕圖案層710。第二罩幕圖案層710定義出T型立柱104(請參閱第2圖)的柱體部210的外型，如以下所述。第二罩幕圖案層710可為光阻罩幕圖案層、硬式罩幕、其組合等等。
之後，第8圖係繪示出根據一實施例之T型立柱104的柱體部210。柱體部210可由任何適當的導電材料所構成，包括Cu、Ni、Pt、Al、其組合等等，且透過任何適當的技術而形成，例如PVD、CVD、ECD、MBE、ALD、電鍍等等。在一些實施例中，柱體部210及UBM部208由相同的材料所構成，而在其他實施例中，柱體部210及UBM部208可由不同的材料所構成。需注意的是在一些實施例中，例如在晶圓的整個表面上沉積(例如，PVD及CVD)一順應性層，且也可進行蝕刻或平坦化製程，以去除第二罩幕圖案層710表面上多餘的導電材料。在一實施例中，柱體部210的厚度約在20微米至100微米的範圍。
在形成T型立柱104之後，去除第一罩幕圖案層510及二罩幕圖案層710，如第9圖所示。在第一罩幕圖案層510及二罩幕圖案層710由光阻材料所構成的實施例中，光阻可透過化學溶液加以剝除，例如乳酸乙酯(ethyllactate)、甲氧苯(anisole)、甲基丁酯(methyl butyl acetate)、醋酸戊酯(amyl acetate)、甲基酚醛樹脂(cresol novolak resin)、及重氮光活性化合物(diazo photoactive compound)的混合物(稱作SPR9)，或使用其他剝除製程。進行一清潔製程，例如濕式浸漬於磷酸(H3 PO4 )與雙氧水(H2 O2 )所構成的化學溶液(稱作DPP)，以及1%氫氟(HF)酸，或進行其他清潔製程，以去除露出的晶種層410部分以及鈍化層120表面的任何汙染物。
之後，可進行適合於特定應用的其他後段(back-end-of-line,BEOL)製程技術。舉例而言，可形成封膠(encapsulant)、進行切割(singulation)製程以分開個別的晶片、進行晶圓級或晶片級堆疊製程等等。然而，需注意的是上述實施例可使用於不同的狀態。舉例而言，上述實施例可使用於晶片對晶片接合、晶片對晶圓接合、晶圓對晶圓接合、晶片級封裝、晶圓級封裝等等。
第10至12圖係繪示出形成第3B圖所示的T型立柱的中間步驟。第10至12圖所示的實施例相似於第4至9圖所示的實施例。因此，第10圖係繪示出完成第9圖的製程之後的後續步驟。
請參照第10圖，其繪示出根據一實施例之形成一第三罩幕圖案層1010。第三罩幕圖案層1010定義出欲放置於T型立柱104的柱體部210周圍的焊料外型，如以下所述。第三罩幕圖案層1010可為光阻罩幕圖案層、硬式罩幕、其組合等等。
之後，請參照第11圖，形成焊料1110。在一實施例中，焊料1110由透過電鍍技術所形成的SnPb、高鉛材料、錫基焊料、無鉛焊料或其他適當的導電材料。可使用平坦化製程，例如CMP，以去除位於柱體部210的一端的焊料，以露出柱體部210的一端，如第11圖所示。
在形成焊料1110之後，去除第三罩幕圖案層1010，如第12圖所示。在第三罩幕圖案層1010由光阻材料所構成的實施例中，光阻可透過化學溶液加以剝除，例如SPR9，或使用其他剝除製程。進行一清潔製程，例如濕式浸漬於DPP化學溶液，以及1%氫氟(HF)酸，或進行其他清潔製程，以去除露出的晶種層410部分以及鈍化層120表面的任何汙染物。
之後，可進行適合於特定應用的其他後段(BEOL)製程技術。舉例而言，可形成封膠、進行切割製程以分開個別的晶片、進行晶圓級或晶片級堆疊製程等等。然而，需注意的是上述實施例可使用於不同的狀態。舉例而言，上述實施例可使用於晶片對晶片接合、晶片對晶圓接合、晶圓對晶圓接合、晶片級封裝、晶圓級封裝等等。
第13至15圖係繪示出形成第3C圖所示的T型立柱的中間步驟。第13至15圖所示的實施例相似於第4至9圖所示的實施例。因此，第13圖係繪示出完成第9圖的製程之後的後續步驟。
請參照第13圖，其繪示出根據一實施例之形成一第三罩幕圖案層1310。第三罩幕圖案層1310定義出欲放置於T型立柱104的柱體部210周圍的焊料外型，如以下所述。第三罩幕圖案層1310可為光阻罩幕圖案層、硬式罩幕、其組合等等。在一實施例中，光阻材料沉積厚度約在50微米至100微米之間的範圍，且透過微影技術進行圖案化。
之後，請參照第14圖，形成焊料1410。在一實施例中，焊料1410由透過電鍍技術所形成的SnPb、高鉛材料、錫基焊料、無鉛焊料或其他適當的導電材料。
在形成焊料1410之後，去除第三罩幕圖案層1010，如第15圖所示。在第三罩幕圖案層1310由光阻材料所構成的實施例中，光阻可透過化學溶液加以剝除，例如SPR9，或使用其他剝除製程。進行一清潔製程，例如濕式浸漬於DPP化學溶液，以及1%氫氟(HF)酸，以去除露出的晶種層410部分以及鈍化層120表面的任何汙染物。
之後，可進行適合於特定應用的其他後段(BEOL)製程技術。舉例而言，可形成封膠、進行切割製程以分開個別的晶片、進行晶圓級或晶片級堆疊製程等等。然而，需注意的是上述實施例可使用於不同的狀態。舉例而言，上述實施例可使用於晶片對晶片接合、晶片對晶圓接合、晶圓對晶圓接合、晶片級封裝、晶圓級封裝等等。
所屬技術領域中具有通常知識者可以瞭解的是相似的製程可用於形成第3A至3C圖所示的實施例。舉例而言，可注意到第10圖的第三罩幕圖案層1010的厚度近似於T型立柱104的柱體部210的高度，而第13圖的第三罩幕圖案層1310的厚度卻大於T型立柱104的柱體部210的高度。除此之外，第10至12圖所示的製程相似於第13至15圖所示的製程。厚度的差異說明了柱體部210上方焊料可具有不同厚度。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。再者，本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此，本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。另外，每一申請專利範圍構成個別的實施例，且本發明之保護範圍也包括各個申請專利範圍及實施例的組合。
102．．．基底/第一基底
104．．．T型立柱
106．．．電路
108．．．內層介電層
110、114．．．接觸窗
112．．．金屬層間介電層
116．．．保護層
118．．．導電層
120．．．鈍化層
202．．．第二基底
204．．．導電接觸窗
206．．．綠漆
208．．．底層凸塊金屬化部
210．．．柱體部
212．．．上表面
216、1110、1410．．．焊料
218．．．介金屬化合物層
410．．．晶種層
510．．．第一罩幕圖案層
710．．．第二罩幕圖案層
1010、1310‧‧‧第三罩幕圖案層
W1 、W2 、W3 ‧‧‧寬度
第1圖係繪示出根據一實施例之具有T型立柱的半導體裝置。
第2圖係繪示出根據一實施例之使用T型立柱將二基底接合在一起。
第3A至3C圖係繪示出提供T型立柱及焊料的不同實施例。
第4至9圖係繪示出根據一實施例之形成T型立柱的方法。
第10至12圖係繪示出根據另一實施例之形成T型立柱的方法。
第13至15圖係繪示出根據又另一實施例之形成T型立柱的方法。
102．．．基底/第一基底
104．．．T型立柱
202．．．第二基底
204．．．導電接觸窗
206．．．綠漆
208．．．底層凸塊金屬化部
210．．．柱體部
212．．．上表面
216．．．焊料
218．．．介金屬化合物層
W1 、W2 、W3 ．．．寬度

Claims (15)

  1. 一種半導體結構，包括：一第一基底，包括一第一導電層；一T型立柱，電性耦接至該第一導電層，該T型立柱具有一底層凸塊金屬化部與該第一導電層接觸，且具有一柱體部延伸自該底層凸塊金屬化部，該底層凸塊金屬化部具有一第一寬度且該柱體部具有一第二寬度，該第一寬度大於該第二寬度；一第二基底，具有一第二導電層；一焊料，圍繞該柱體部且與該第一導電層及該第二導電層作電性接觸；以及一介金屬化合物層，位於該柱體部與該第二導電層之間，該介金屬化合物層連續性地延伸至該第二導電層與該柱體部之間。
  2. 如申請專利範圍第1項所述之半導體結構，其中該柱體部與該底層凸塊金屬化部由不同的材料所構成，且該第二寬度為該第一寬度的0.2至0.75倍。
  3. 如申請專利範圍第1項所述之半導體結構，其中該第一基底與該第二基底的至少其中一個為一晶片或一晶圓。
  4. 如申請專利範圍第1項所述之半導體結構，其中該第二基底包括一綠漆，而該柱體部延伸越過該綠漆的一上表面。
  5. 一種半導體結構，包括：一第一基底，包括一第一導電層以及一鈍化層位於 該第一導電層的至少一部分；以及一T型立柱，位於該第一導電層上方，該T型立柱具有一底層凸塊金屬化部及一柱體部，該底層凸塊金屬化部位於該鈍化層與該柱體部之間，且該柱體部的一寬度小於該底層凸塊金屬化部的一寬度。
  6. 如申請專利範圍第5項所述之半導體結構，更包括一焊料，其與該T型立柱接觸，其中該焊料未覆蓋該T型立柱的該柱體部的一端。
  7. 如申請專利範圍第5項所述之半導體結構，更包括一焊料，其與該T型立柱接觸，其中該焊料覆蓋該T型立柱的該柱體部的一端。
  8. 如申請專利範圍第5項所述之半導體結構，其中該柱體部與該底層凸塊金屬化部由不同的材料所構成，且該柱體部的該寬度為該底層凸塊金屬化部的該寬度的0.2至0.75倍。
  9. 一種半導體裝置的製造方法，包括：提供一第一基底，其具有一接觸窗；在該第一基底上方形成一鈍化層，而露出至少一部分的該接觸窗；在該鈍化層上方形成一第一罩幕圖案層，該第一罩幕圖案層具有一第一開口而露出至少一部分的該接觸窗；在該第一開口內形成一底層凸塊金屬化部；在該第一罩幕圖案層上方形成一第二罩幕圖案層，該第二罩幕圖案層具有一第二開口而僅露出一部分的該 底層凸塊金屬化部；在該第二開口內形成一柱體部，該底層凸塊金屬化部及該柱體部形成一T型接觸窗，且該柱體部的一寬度小於該底層凸塊金屬化部的一寬度；以及去除該第一罩幕圖案層及該第二罩幕圖案層。
  10. 如申請專利範圍第9項所述之半導體裝置的製造方法，其中該柱體部的該寬度為該底層凸塊金屬化部的該寬度的0.2至0.75倍。
  11. 如申請專利範圍第9項所述之半導體裝置的製造方法，更包括：在該鈍化層上方形成一第三罩幕圖案層，該第三罩幕圖案層具有一上表面切齊於該柱體部的一頂部，該第三罩幕圖案層露出該柱體部；形成一焊料，其圍繞該柱體部，而使該柱體部的該頂部露出來；以及去除該第三罩幕圖案層。
  12. 如申請專利範圍第9項所述之半導體裝置的製造方法，更包括：在該鈍化層上方形成一第三罩幕圖案層，該第三罩幕圖案層具有一上表面高於該柱體部的一頂部，該第三罩幕圖案層露出該柱體部；形成一焊料，其圍繞該柱體部，而使該焊料覆蓋該柱體部的該頂部；以及去除該第三罩幕圖案層。
  13. 如申請專利範圍第9項所述之半導體裝置的製造 方法，更包括：提供一第二基底，其具有一導電接觸窗及一綠漆；以及將該第一基底接合至該第二基底，使該柱體部置入於該綠漆的一開口內。
  14. 如申請專利範圍第13項所述之半導體裝置的製造方法，其中一介金屬化合物層置於該柱體部與該導電接觸窗之間，該介金屬化合物層連續性地延伸自該導電接觸窗及該柱體部。
  15. 如申請專利範圍第9項所述之半導體裝置的製造方法，更包括：提供一第二基底，其具有一導電接觸窗、一綠漆、以及一焊料位於該綠漆的一開口內；以及將該第一基底接合至該第二基底，使該柱體部置入於該綠漆的該開口的該焊料中。
TW099111223A 2010-01-29 2010-04-12 半導體結構及半導體裝置的製造方法 TWI429040B (zh)

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