TWI467718B - 凸塊結構以及電子封裝接點結構及其製造方法 - Google Patents

凸塊結構以及電子封裝接點結構及其製造方法 Download PDF

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TWI467718B
TWI467718B TW100150088A TW100150088A TWI467718B TW I467718 B TWI467718 B TW I467718B TW 100150088 A TW100150088 A TW 100150088A TW 100150088 A TW100150088 A TW 100150088A TW I467718 B TWI467718 B TW I467718B
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Taiwan
Prior art keywords
electrode
conductive material
substrate
layer
electronic package
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TW100150088A
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English (en)
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TW201327749A (zh
Inventor
Yu Min Lin
Chau Jie Zhan
Tao Chih Chang
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Ind Tech Res Inst
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Priority to TW100150088A priority Critical patent/TWI467718B/zh
Priority to CN201210159760.8A priority patent/CN103187387B/zh
Priority to US13/484,289 priority patent/US9024441B2/en
Publication of TW201327749A publication Critical patent/TW201327749A/zh
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Publication of TWI467718B publication Critical patent/TWI467718B/zh

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Description

凸塊結構以及電子封裝接點結構及其製造方法
本發明是有關於一種凸塊結構以及電子封裝接點結構及其製造方法，且特別是有關於一種可用以形成介金屬化合物的凸塊結構以及一種具有介金屬化合物的電子封裝接點結構及其製造方法。
在電子封裝製程中，常見的接點為微凸塊接點(micro-bump joint)與介金屬化合物接點(intermetallic compound joint，IMC joint)。
微凸塊接點具有較佳的彈性與韌性，所以抗機械應力的能力較佳，但是微凸塊接點在抗電致遷移效應(anti-lectromigration，EM)的能力不佳。
微凸塊接點在溫度循環可靠度測試過程中，在微凸塊接點的介面上可能因為高溫而形成介金屬化合物接點，通常這種介金屬化合物接點的材料硬度比原來的微凸塊接點硬，剛性較高而缺乏彈性，較容易在溫度循環的可靠度測試中被破壞。但是，介金屬化合物具有可減緩電遷移效應的特性，所以提高介金屬化合物含量反而可以增加微凸塊接點抵抗電遷移效應的能力。
因此，目前業界企圖發展出將同時具有抗機械應力與抗電遷移效應之特性的電子封裝接點結構，以提升接點的可靠性及效能。
本發明的目的是提供一種凸塊結構，其可用以形成特定外型之介金屬化合物。
本發明的目的是提供一種電子封裝接點結構，其可同時具有抗機械應力與抗電遷移效應的特性。
本發明的另一目的是提供一種電子封裝接點結構的製造方法，其可製作出具有較佳可靠性及效能的電子封裝接點結構。
本發明提出一種凸塊結構，包括基板、銲墊、電極及凸出電極。銲墊設置於基板上。電極由第一金屬材料製成，且設置於銲墊上。凸出電極由第二金屬材料製成，且設置於電極上，其中凸出電極的截面積小於電極的截面積。
依照本發明的一實施例所述，在上述之凸塊結構中，更包括保護層，設置於基板上與銲墊上，且暴露出部分銲墊。
依照本發明的一實施例所述，在上述之凸塊結構中，更包括導電材料，覆蓋凸出電極與電極。
本發明提出一種電子封裝接點結構，包括第一基板、第二基板及接點。第一基板包括至少一第一電極，第一電極設置於第一基板上。第二基板包括至少一第二電極，第二電極設置於第二基板上。接點設置於第一電極與第二電極之間，且包括介金屬化合物層及導電材料層。介金屬化合物層為連續性結構，且直接連接第一電極與第二電極。導電材料層設置於介金屬化合物層周圍，且覆蓋介金屬化 合物層。
依照本發明的一實施例所述，在上述之電子封裝接點結構中，介金屬化合物層例如是柱狀結構。
依照本發明的一實施例所述，在上述之電子封裝接點結構中，介金屬化合物層包括第一部分、第二部分及第三部分。第一部分連接於第一電極與第二電極。第二部分設置於第一部分周圍，且連接於第一電極與第一部分。第三部分設置於第一部分周圍，且連接於第二電極與第一部分。
依照本發明的一實施例所述，在上述之電子封裝接點結構中，介金屬化合物層例如是I字型結構。
依照本發明的一實施例所述，在上述之電子封裝接點結構中，介金屬化合物層的材料例如是Cux Sny 、Nix Sny 、Inx Sny 、Znx Sny 或Aux Sny 等。
依照本發明的一實施例所述，在上述之電子封裝接點結構中，第一電極與第二電極的材料例如是銅(Cu)、銀(Ag)、鎳(Ni)、鋁(Al)、鈦(Ti)、鎢(W)、鉻(Cr)、金(Au)、鋅(Zn)、鉍(Bi)或銦(In)等或其組合合金。
依照本發明的一實施例所述，在上述之電子封裝接點結構中，導電材料層的材料例如是Sn、SnAg或SnAgCu等。
依照本發明的一實施例所述，在上述之電子封裝接點結構中，介金屬化合物層的電阻係數例如是小於導電材料層的電阻係數。
依照本發明的一實施例所述，在上述之電子封裝接點 結構中，導電材料層例如是連接於第一電極及第二電極或藉由介金屬化合物層而與第一電極及第二電極隔離。
本發明提出一種電子封裝接點結構的製造方法，包括下列步驟。首先，提供第一基板，第一基板上已形成有至少一第一電極、至少一第一凸出電極與至少一第一導電材料，其中第一凸出電極形成於第一電極上，且第一導電材料覆蓋第一電極與第一凸出電極。接著，提供第二基板，第二基板上已形成有至少一第二電極、至少一第二凸出電極與至少一第二導電材料，其中第二凸出電極形成於第二電極上，且第二導電材料覆蓋第二電極與第二凸出電極。然後，對第一基板與第二基板進行接合製程，以使得第一凸出電極與第二凸出電極連接而形成介金屬化合物層，介金屬化合物層為連續性結構，且直接連接於第一電極與第二電極。
依照本發明的一實施例所述，在上述之電子封裝接點結構的製造方法中，接合製程的加熱溫度例如是150℃至300℃，而接合製程的加熱時間例如是3秒至60分。
依照本發明的一實施例所述，在上述之電子封裝接點結構的製造方法中，第一凸出電極與第二凸出電極的材料例如是介金屬化合物。
依照本發明的一實施例所述，在上述之電子封裝接點結構的製造方法中，第一凸出電極與第二凸出電極的形成方法包括下列步驟。首先，形成由至少一第一金屬層與至少一第二金屬層交互堆疊而形成的金屬堆疊結構。接著， 對金屬堆疊結構進行熱製程，使第一金屬層與第二金屬層反應。
依照本發明的一實施例所述，在上述之電子封裝接點結構的製造方法中，熱製程例如是回銲製程(reflow process)或老化製程(aging process)。
依照本發明的一實施例所述，在上述之電子封裝接點結構的製造方法中，熱製程的加熱溫度例如是150℃至300℃，而熱製程的加熱時間例如是3秒至60分。
依照本發明的一實施例所述，在上述之電子封裝接點結構的製造方法中，介金屬化合物層例如是由第一凸出電極與第一導電材料反應以及第二凸出電極與第二導電材料反應而形成。
依照本發明的一實施例所述，在上述之電子封裝接點結構的製造方法中，介金屬化合物層例如是由第一凸出電極與第一導電材料反應、第二凸出電極與第二導電材料反應、第一電極與第一導電材料反應以及第二電極與第二導電材料反應而形成。
基於上述，在本發明所提出之凸塊結構中，由於凸塊結構具有凸出電極，因此有助於形成柱狀介金屬化合物。在本發明所提出之電子封裝接點結構中，由於接點包括介金屬化合物層及導電材料層，介金屬化合物層為連續性結構且直接連接第一電極與第二電極，且導電材料層設置於介金屬化合物層周圍，因此電子封裝接點結構可同時具有抗機械應力與抗電遷移效應的特性。此外，本發明所提出 之電子封裝接點結構的製造方法可輕易地與現行製程整合，且可製作出具有較佳可靠性及效能的電子封裝接點結構。
為讓本發明之上述和其他目的和特徵能更明顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下。
圖1A至圖1F所繪示為本發明之一實施例的電子封裝接點結構的製造流程剖面圖。
首先，請參照圖1A，提供基板100a。基板100a上可形成有銲墊102a與保護層104a。銲墊102a形成於基板100a上，用以與基板100a內部的金屬內連線(未繪示)電性連接。基板100a例如是有機載板或無機載板。有機載板例如是印刷電路板(PCB)。無機載板例如是矽晶片。銲墊102a的材料例如是鋁、鋁矽、鋁矽銅、銅、或鎳等。保護層104a形成於基板100a上與銲墊102a上，且暴露出部分銲墊102a。保護層104a的材料例如是聚亞醯胺(polyimide，PI)、聚苯噁唑(polybenzoxazole，PBO)、ABF(Ajinomoto build-up film)、氧化矽(Six Oy )、或氮化矽(Six Ny )等。銲墊102a與保護層104a例如是分別藉由進行沉積製程與圖案化製程而形成之。
接著，於基板100a上形成圖案化光阻層106a，且圖案化光阻層106a暴露出銲墊102a。在此實施例中，圖案化光阻層106a更可暴露出部分保護層104a。圖案化光阻 層106a的材料例如是正型光阻或負型光阻。圖案化光阻層106a的形成方法例如是進行微影製程而形成之。
然後，於圖案化光阻層106a所暴露的銲墊102a與保護層104a上形成至少一電極108a。電極108a的材料例如是銅(Cu)、銀(Ag)、鎳(Ni)、鋁(Al)、鈦(Ti)、鎢(W)、鉻(Cr)、金(Au)、鋅(Zn)、鉍(Bi)或銦(In)或其組合之合金等。電極108a的形成方法例如是電鍍法。雖然，電極108a是藉由上述方法所形成，但並不用以限制本發明。
接下來，請參照圖1B，移除圖案化光阻層106a。圖案化光阻層106a的移除方法例如是乾式去光阻法。
之後，於基板100a上形成圖案化光阻層110a，且圖案化光阻層110a暴露出部分電極108a。圖案化光阻層110a的材料例如是正型光阻或負型光阻。圖案化光阻層110a的形成方法例如是進行微影製程而形成之。
再者，於圖案化光阻層110a所暴露出的電極108a上形成由至少一金屬層112a與至少一金屬層114a交互堆疊而形成的金屬堆疊結構116a。金屬層112a的材料例如是銅(Cu)、銀(Ag)、鎳(Ni)、鋁(Al)、鈦(Ti)、鎢(W)、鉻(Cr)、金(Au)、鋅(Zn)、鉍(Bi)或銦(In)等或其組合合金。金屬層114a的材料例如是錫(Sn)。金屬層112a與金屬層114a的形成方法分別例如是電鍍法。
隨後，請參照圖1C，移除圖案化光阻層110a。圖案化光阻層110a的移除方法例如是乾式去光阻法。
繼之，對金屬堆疊結構116a進行熱製程，使金屬層 112a與金屬層114a反應，而於電極108a上形成至少一凸出電極118a。凸出電極118a的材料例如是介金屬化合物，如Cux Sny 、Nix Sny 、Inx Sny 、Znx Sny 或Aux Sny 等。熱製程例如是回銲製程(reflow process)或老化製程(aging process)。熱製程的加熱溫度例如是150℃至300℃，而熱製程的加熱時間例如是3秒至60分。雖然，凸出電極118a是藉由上述方法所形成，但並不用以限制本發明。
接著，於基板100a上形成圖案化光阻層120a，且圖案化光阻層120a暴露出電極108a與凸出電極118a。圖案化光阻層120a的材料例如是正型光阻或負型光阻。圖案化光阻層120a的形成方法例如是進行微影製程而形成之。
然後，形成至少一導電材料122a，導電材料122a覆蓋電極108a與凸出電極118a。導電材料122a的材料例如是Sn、SnAg或SnAgCu等。導電材料122a的形成方法例如是電鍍法。
接下來，請參照圖1D，移除圖案化光阻層120a。圖案化光阻層120a的移除方法例如是乾式去光阻法。
此時，所提供的基板100a上已形成有電極108a、凸出電極118a與導電材料122a，其中凸出電極118a形成於電極108a上，且導電材料122a覆蓋電極108a與凸出電極118a。此外，基板100a上更可形成有銲墊102a與保護層104a。銲墊102a形成於基板100a上。保護層104a形成於基板100a上與銲墊102a上，且暴露出部分銲墊102a。
此處，藉由圖1D說明本實施例中的凸塊結構123a。 凸塊結構123a包括基板100a、電極108a及凸出電極118a。電極108a設置於基板100a上。凸出電極118a設置於電極108a上，凸出電極118a的截面積小於電極108a的截面積。其中，凸出電極118a的寬度例如是小於電極108a的寬度。此外，凸塊結構123a更可包括銲墊102a、保護層104a及導電材料122a。銲墊102a設置於基板100a與電極108a之間。保護層104a設置於基板100a上與銲墊102a上，且暴露出部分銲墊102a。導電材料122a覆蓋凸出電極118a與電極108a。在此實施例中，由於凸塊結構123a具有凸出電極118a，因此有助於形成介金屬化合物。此外，凸塊結構123a中各構件的材料、特性、配置方式、形成方法及功效已於上述實施例中進行詳盡地說明，故於此不再贅述。
之後，請參照圖1E，提供基板100b，基板100b上已形成有電極108b、凸出電極118b與導電材料122b，其中凸出電極118b形成於電極108b上，且導電材料122b覆蓋電極108b與凸出電極118b。基板100b例如是有機載板或無機載板。有機載板例如是印刷電路板(PCB)。無機載板例如是矽晶片。此外，基板100b上更可形成有銲墊102b與保護層104b。銲墊102b形成於基板100b上。保護層104b形成於基板100b上與銲墊102b上，且暴露出部分銲墊102b。其中，電極108b與電極108a的材料可為相同或不同，於此技術領域具有通常知識者可依照產品設計而進行調整。然而，由於基板100b上的電極108b、凸出電極118b 與導電材料122b的材料、配置方式及形成方法與基板100a上的電極108a、凸出電極118a與導電材料122a的材料、配置方式及形成方法相似，請參照圖1A至圖1D的說明，於此不再贅述。
此處，藉由圖1E說明本實施例中的凸塊結構123b。凸塊結構123b包括基板100b、電極108b及凸出電極118b。電極108b設置於基板100b上。凸出電極118b設置於電極108b上，凸出電極118b的截面積小於電極108b的截面積。其中，凸出電極118b的寬度例如是小於電極108b的寬度。此外，凸塊結構123b更可包括銲墊102b、保護層104b及導電材料122b。銲墊102b設置於基板100b與電極108b之間。保護層104b設置於基板100b上與銲墊102b上，且暴露出部分銲墊102b。導電材料122b覆蓋凸出電極118b與電極108b。在此實施例中，由於凸塊結構123b具有凸出電極118b，因此有助於形成介金屬化合物。此外，凸塊結構123b中各構件的材料、特性、配置方式、形成方法及功效已於上述實施例中進行詳盡地說明，故於此不再贅述。
再者，請參照圖1F，對基板100a與基板100b進行接合製程，以使得凸出電極118a與凸出電極118b連接而形成介金屬化合物層124，介金屬化合物層124為連續性結構，且直接連接於電極108a與電極108b。此外，在此接合製程中，導電材料122a與導電材料122b連接而形成導電材料層126，而由介金屬化合物層124與導電材料層126形成接 點128。接合製程的加熱溫度例如是150℃至300℃，而接合製程的加熱時間例如是3秒至60分。此外，在接合製程中，當凸出電極118a與凸出電極118b再次與導電材料122a與導電材料122b反應時，介金屬化合物層124的寬度會大於凸出電極118a的寬度與凸出電極118b的寬度。
介金屬化合物層124例如是柱狀結構。介金屬化合物層124的材料例如是Cux Sny 、Nix Sny 、Inx Sny 、Znx Sny 或Aux Sny 等。
介金屬化合物層124例如是藉由化學鍵結方式與電極108a及電極108b形成電性通路。
導電材料層126設置於介金屬化合物層124周圍，且連接於介金屬化合物層124。此外，導電材料層126例如是連接於電極108a及電極108b。導電材料層126的材料例如是Sn、SnAg或SnAgCu等。介金屬化合物層124的電阻係數例如是小於導電材料層126的電阻係數，而可促使電子流經接點128時會儘可能往介金屬化合物層124流動，而可進一步地提升抗電遷移效應的能力。
在此實施例中，雖然介金屬化合物層124是以形成柱狀結構為例進行說明，但並不用以限制本發明。在其他實施例中，可透過對於電極108a及電極108b之材料的選擇而使得電極108a及電極108b分別可與導電材料122a與導電材料122b反應，藉此介金屬化合物層124亦可形成I字型結構(類似圖2F的介金屬化合物層218)。當介金屬化合物層124為I字型時，能強迫電子流經介金屬化合物層124，因此可 更進一步地提升抗電遷移效應的能力。
基於上述實施例可知，由於接點128中的介金屬化合物層124為連續性結構且直接連接電極108a與電極108b，且導電材料層126設置於介金屬化合物層124周圍，因此電子封裝接點結構可同時具有抗機械應力與抗電遷移效應的特性，而具有較佳的可靠性及效能。此外，上述實施例所提出之電子封裝接點結構的製造方法可輕易地與現行製程整合。
圖2A至圖2F所繪示為本發明之另一實施例的電子封裝接點結構的製造流程剖面圖。
首先，請參照圖2A，提供基板200a。基板200a上可形成有銲墊202a與保護層204a。銲墊202a形成於基板200a上，用以與基板200a內部的金屬內連線(未繪示)電性連接。基板200a例如是有機載板或無機載板。有機載板例如是印刷電路板(PCB)。無機載板例如是矽晶片。銲墊202a的材料例如是鋁、鋁矽、鋁矽銅、銅或鎳等。保護層204a形成於基板200a上與銲墊202a上，且暴露出部分銲墊202a。保護層204a的材料例如是聚亞醯胺(polyimide，PI)、聚苯噁唑(polybenzoxazole，PBO)、ABF(Ajinomoto build-up film)、Six Oy 、或Six Ny 等。銲墊202a與保護層204a例如是分別藉由進行沉積製程與圖案化製程而形成之。
接著，於基板200a上形成圖案化光阻層206a，且圖案化光阻層206a暴露出銲墊202a。在此實施例中，圖案化光阻層206a更可暴露出部分保護層204a。圖案化光阻 層206a的材料例如是正型光阻或負型光阻。圖案化光阻層206a的形成方法例如是進行微影製程而形成之。
然後，於圖案化光阻層206a所暴露的銲墊202a與保護層204a上形成至少一電極208a。電極208a的材料例如是銅(Cu)、銀(Ag)、鎳(Ni)、鋁(Al)、鈦(Ti)、鎢(W)、鉻(Cr)、金(Au)、鋅(Zn)、鉍(Bi)或銦(In)等或其組合合金。電極208a的形成方法例如是電鍍法。雖然，電極208a是藉由上述方法所形成，但並不用以限制本發明。
接下來，請參照圖2B，移除圖案化光阻層206a。圖案化光阻層206a的移除方法例如是乾式去光阻法。
之後，於基板200a上形成圖案化光阻層210a，且圖案化光阻層210a暴露出部分電極208a。圖案化光阻層210a的材料例如是正型光阻或負型光阻。圖案化光阻層210a的形成方法例如是進行微影製程而形成之。
再者，於圖案化光阻層210a所暴露出的電極208a上形成至少一凸出電極212a。凸出電極212a的材料例如是銅(Cu)、銀(Ag)、鎳(Ni)、鋁(Al)、鈦(Ti)、鎢(W)、鉻(Cr)、金(Au)、鋅(Zn)、鉍(Bi)、銦(In)或錫(Sn)等或其組合合金。凸出電極212a與電極208a的材料可為相同或不同。凸出電極212a的形成方法例如是電鍍法。雖然，凸出電極212a是藉由上述方法所形成，但並不用以限制本發明。
隨後，請參照圖2C，移除圖案化光阻層210a。圖案化光阻層210a的移除方法例如是乾式去光阻法。
繼之，於基板200a上形成圖案化光阻層214a，且圖 案化光阻層214a暴露出電極208a與凸出電極212a。圖案化光阻層214a的材料例如是正型光阻或負型光阻。圖案化光阻層214a的形成方法例如是進行微影製程而形成之。
接著，形成至少一導電材料216a，導電材料216a覆蓋電極208a與凸出電極212a。導電材料216a的材料例如是Sn、SnAg或SnAgCu等。導電材料216a的形成方法例如是電鍍法。
然後，請參照圖2D，移除圖案化光阻層214a。圖案化光阻層214a的移除方法例如是乾式去光阻法。
此時，所提供的基板200a上已形成有電極208a、凸出電極212a與導電材料216a，其中凸出電極212a形成於電極208a上，且導電材料216a覆蓋電極208a與凸出電極212a。此外，基板200a上更可形成有銲墊202a與保護層204a。銲墊202a形成於基板200a上。保護層204a形成於基板200a上與銲墊202a上，且暴露出部分銲墊202a。
此處，藉由圖2D說明本實施例中的凸塊結構217a。凸塊結構217a包括基板200a、電極208a及凸出電極212a。電極208a設置於基板200a上。凸出電極212a設置於電極208a上，凸出電極212a的截面積小於電極208a的截面積。其中，凸出電極212a的寬度例如是小於電極208a的寬度。此外，凸塊結構217a更可包括銲墊202a、保護層204a及導電材料216a。銲墊202a設置於基板200a與電極208a之間。保護層204a設置於基板200a上與銲墊202a上，且暴露出部分銲墊202a。導電材料216a覆蓋凸 出電極212a與電極208a。在此實施例中，由於凸塊結構217a具有凸出電極212a，因此有助於形成介金屬化合物。此外，凸塊結構217a中各構件的材料、特性、配置方式、形成方法及功效已於上述實施例中進行詳盡地說明，故於此不再贅述。
之後，請參照圖2E，提供基板200b，基板200b上已形成有電極208b、凸出電極212b與導電材料216b，其中凸出電極212b形成於電極208b上，且導電材料216b覆蓋電極208b與凸出電極212b。基板200b例如是有機載板或無機載板。有機載板例如是印刷電路板(PCB)。無機載板例如是矽晶片。此外，基板200b上更可形成有銲墊202b與保護層204b。銲墊202b形成於基板200b上。保護層204b形成於基板200b上與銲墊202b上，且暴露出部分銲墊202b。其中，電極208b與電極208a的材料可為相同或不同，於此技術領域具有通常知識者可依照產品設計而進行調整。然而，由於基板200b上的電極208b、凸出電極212b與導電材料216b的材料、配置方式及形成方法與基板200a上的電極208a、凸出電極212a與導電材料216a的材料、配置方式及形成方法相似，請參照圖2A至圖2D的說明，於此不再贅述。
此處，藉由圖2E說明本實施例中的凸塊結構217b。凸塊結構217b包括基板200b、電極208b及凸出電極212b。電極208b設置於基板200b上。凸出電極212b設置於電極208b上，凸出電極212b的截面積小於電極208b 的截面積。其中，凸出電極212b的寬度例如是小於電極208b的寬度。此外，凸塊結構217b更可包括銲墊202b、保護層204b及導電材料216b。銲墊202b設置於基板200b與電極208b之間。保護層204b設置於基板200b上與銲墊202b上，且暴露出部分銲墊202b。導電材料216b覆蓋凸出電極212b與電極208b。在此實施例中，由於凸塊結構217b具有凸出電極212b，因此有助於形成介金屬化合物。此外，凸塊結構217b中各構件的材料、特性、配置方式、形成方法及功效已於上述實施例中進行詳盡地說明，故於此不再贅述。
再者，請參照圖2F，對基板200a與基板200b進行接合製程，以使得凸出電極212a與凸出電極212b連接，且凸出電極212a與導電材料216a反應加上凸出電極212b與導電材料216b反應而形成介金屬化合物層218的第一部分218a，電極208a與導電材料216a反應而形成介金屬化合物層218的第二部分218b，電極208b與導電材料216b反應而形成介金屬化合物層218的第三部分218c。介金屬化合物層218為連續性結構，且直接連接於電極208a與電極208b。其中，介金屬化合物層218的第一部分218a的寬度例如是大於凸出電極212a的寬度與凸出電極212b的寬度。此外，在此接合製程中，導電材料216a與導電材料216b連接而形成導電材料層220，而由介金屬化合物層218與導電材料層220形成接點222。接合製程的加熱溫度例如是150℃至300℃接合製程的加熱時間例如是3秒至60 分。
在此實施例中，介金屬化合物層218例如是I字型結構。介金屬化合物層218的材料例如是Cux Sny 、Nix Sny 、Inx Sny 、Znx Sny 或Aux Sny 等。
介金屬化合物層218例如是藉由化學鍵結方式與電極208a及電極208b形成電性通路。此外，由於凸出電極212a與電極208a的材料可為相同或不同，且凸出電極212b與電極208b的材料可為相同或不同，所以所形成的第一部分218a、第二部分218b與第三部分218c的材料亦可互為相同或不同，於此技術領域具有通常知識者可依照產品設計自行調整。
導電材料層220設置於介金屬化合物層218周圍，且連接於介金屬化合物層218。此外，導電材料層220例如是藉由介金屬化合物層218而與電極208a及電極208b隔離。導電材料層220的材料例如是Sn、SnAg或SnAgCu等。介金屬化合物層218的電阻係數例如是小於導電材料層220的電阻係數，而可促使電子流經接點222時會儘可能往介金屬化合物層218流動，而可進一步地提升抗電遷移效應的能力。
在此實施例中，雖然介金屬化合物層218是以形成I字型結構為例進行說明，但並不用以限制本發明。在其他實施例中，可透過對於電極208a及電極208b之材料的選擇而使得電極208a及電極208b不會與導電材料216a與導電材料216b反應，所以介金屬化合物層218只具有由凸出電 極212a與導電材料216a反應以及凸出電極212b與導電材料216b反應而形成的第一部分218a，而成為柱狀結構(類似圖1F的介金屬化合物層124)。
同樣地，由於接點222中的介金屬化合物層218為連續性結構且直接連接電極208a與電極208b，且導電材料層220設置於介金屬化合物層218周圍，因此電子封裝接點結構可具有較佳的可靠性及效能。此外，當介金屬化合物層218為I字型時，能強迫電子流經介金屬化合物層218，因此可更進一步地提升抗電遷移效應的能力。另外，上述實施例所提出之電子封裝接點結構的製造方法可輕易地與現行製程整合。
以下，藉由圖1F與圖2F來說明上述實施例所提出之電子封裝接點結構。
請參照圖1F，電子封裝接點結構包括基板100a、基板100b及接點128。基板100a上具有至少一電極108a。基板100b上具有至少一電極108b。接點128設置於電極108a與電極108b之間，且包括介金屬化合物層124及導電材料層126。介金屬化合物層124為連續性結構，且直接連接電極108a與電極108b。導電材料層126設置於介金屬化合物層124周圍，且連接於介金屬化合物層124。介金屬化合物層124例如是柱狀結構。另外，電子封裝接點結構更可包括銲墊102a、保護層104a、銲墊102a與保護層104a。銲墊102a設置於基板100a上。保護層104a設置於基板100a上與銲墊102a上，且暴露出部分銲墊102a。銲 墊102b設置於基板100b上。保護層104b設置於基板100b上與銲墊102b上，且暴露出部分銲墊102b。此外，電子封裝接點結構中各構件的材料、特性、配置方式、形成方法及功效已於上述實施例中進行詳盡地說明，故於此不再贅述。
由上述實施例可知，在電子封裝接點結構中，由於接點128中的介金屬化合物層124為連續性結構且直接連接電極108a與電極108b，且導電材料層126設置於介金屬化合物層124周圍，因此可同時具有抗機械應力與抗電遷移效應的特性，而具有較佳的可靠性及效能。
接著，請同時參照圖1F及圖2F，圖2F的電子封裝接點結構與圖1F的電子封裝接點結構之差異在於：在圖2F的電子封裝接點結構中，介金屬化合物層218為I字型結構，而與圖1F中為柱狀結構的介金屬化合物層214不同。介金屬化合物層218包括第一部分218a、第二部分218b及第三部分218c。第一部分218a連接於電極208a與電極208b。第二部分218b設置於第一部分218a周圍，且連接於電極208a與第一部分218a。第三部分218c設置於第一部分218b周圍，且連接於電極208b與第一部分218a。此外，圖2F的電子封裝接點結構中的其他構件的設置方式與圖1的電子封裝接點結構相似，且圖2F的電子封裝接點結構中各構件材料、特性、配置方式、形成方法及功效已於上述實施例中進行詳盡地說明，故於此不再贅述。
同樣地，在電子封裝接點結構中，由於接點222中的 介金屬化合物層218為連續性結構且直接連接電極208a與電極208b，且導電材料層220設置於介金屬化合物層218周圍，因此可同時具有抗機械應力與抗電遷移效應的特性，而具有較佳的可靠性及效能。此外，當介金屬化合物層218為I字型時，能強迫電子流經介金屬化合物層218，因此可更進一步地提升抗電遷移效應的能力。
綜上所述，上述實施例至少具有下列特徵：
1.上述實施例所提出之凸塊結構，有助於形成介金屬化合物。
2.上述實施例所提出之電子封裝接點結構可同時具有抗機械應力與抗電遷移效應的特性。
3.上述實施例所提出之電子封裝接點結構的製造方法可與現行製程整合，且可製作出具有較佳的可靠性及效能的電子封裝接點結構。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100a、100b、200a、200b‧‧‧基板
102a、102b、202a、202b‧‧‧銲墊
104a、104b、204a、204b‧‧‧保護層
106a、110a、120a、206a、210a、214a‧‧‧圖案化光阻層
108a、108b、208a、208b‧‧‧電極
112a、114a‧‧‧金屬層
116a‧‧‧金屬堆疊結構
118a、118b、212a、212b‧‧‧凸出電極
122a、122b、216a、216b‧‧‧導電材料
123a、123b、217a、217b‧‧‧凸塊結構
124、218‧‧‧介金屬化合物層
126、220‧‧‧導電材料層
128、222‧‧‧接點
218a‧‧‧第一部分
218b‧‧‧第二部分
218c‧‧‧第三部分
圖1A至圖1F所繪示為本發明之一實施例的電子封裝接點結構的製造流程剖面圖。
圖2A至圖2F所繪示為本發明之另一實施例的電子封裝接點結構的製造流程剖面圖。
100a‧‧‧基板
102a‧‧‧銲墊
104a‧‧‧保護層
108a‧‧‧電極
118a‧‧‧凸出電極
122a‧‧‧導電材料
123a‧‧‧凸塊結構

Claims (13)

  1. 一種電子封裝接點結構，包括：一第一基板，包括：至少一第一電極，設置於該第一基板上；一第二基板，包括：至少一第二電極，設置於該第二基板上；以及一接點，設置於該第一電極與該第二電極之間，包括：一介金屬化合物層，其為連續性結構，且直接連接於該第一電極與該第二電極；以及一導電材料層，設置於該介金屬化合物層周圍，且覆蓋該介金屬化合物層，其中該導電材料層藉由該介金屬化合物層而與該第一電極及該第二電極隔離。
  2. 如申請專利範圍第1項所述之電子封裝接點結構，其中該介金屬化合物層包括：一第一部分，連接於該第一電極與該第二電極；一第二部分，設置於該第一部分周圍，且連接於該第一電極與該第一部分；以及一第三部分，設置於該第一部分周圍，且連接於該第二電極與該第一部分。
  3. 如申請專利範圍第1項所述之電子封裝接點結構，其中該介金屬化合物層的材料包括Cux Sny 、Nix Sny 、Inx Sny 、Znx Sny 或Aux Sny 。
  4. 如申請專利範圍第1項所述之電子封裝接點結構，其中該第一電極與該第二電極的材料包括銅(Cu)、銀 (Ag)、鎳(Ni)、鋁(Al)、鈦(Ti)、鎢(W)、鉻(Cr)、金(Au)、鋅(Zn)、鉍(Bi)、銦(In)或其組合之合金。
  5. 如申請專利範圍第1項所述之電子封裝接點結構，其中該導電材料層的材料包括Sn、SnAg或SnAgCu。
  6. 如申請專利範圍第1項所述之電子封裝接點結構，其中該介金屬化合物層的電阻係數小於該導電材料層的電阻係數。
  7. 一種電子封裝接點結構的製造方法，包括：提供一第一基板，該第一基板上已形成有至少一第一電極、至少一第一凸出電極與至少一第一導電材料，其中該第一凸出電極形成於該第一電極上，且該第一導電材料覆蓋該第一電極與該第一凸出電極；提供一第二基板，該第二基板上已形成有至少一第二電極、至少一第二凸出電極與至少一第二導電材料，其中該第二凸出電極形成於該第二電極上，且該第二導電材料覆蓋該第二電極與該第二凸出電極；以及對該第一基板與該第二基板進行一接合製程，以使得該第一凸出電極與該第二凸出電極連接而形成一介金屬化合物層，其中該接合製程的加熱溫度為150℃至300℃，而該接合製程的加熱時間為3秒至60分，該介金屬化合物層為連續性結構，且直接連接於該第一電極與該第二電極。
  8. 如申請專利範圍第7項所述之電子封裝接點結構的製造方法，其中該第一凸出電極與該第二凸出電極的材料包括介金屬化合物。
  9. 如申請專利範圍第8項所述之電子封裝接點結構的製造方法，其中該第一凸出電極與該第二凸出電極的形成方法包括：形成由至少一第一金屬層與至少一第二金屬層交互堆疊而形成的一金屬堆疊結構；以及對該金屬堆疊結構進行一熱製程，使該第一金屬層與該第二金屬層反應。
  10. 如申請專利範圍第9項所述之電子封裝接點結構的製造方法，其中該熱製程包括回銲製程或老化製程。
  11. 如申請專利範圍第9項所述之電子封裝接點結構的製造方法，其中該熱製程的加熱溫度為150℃至300℃，而該熱製程的加熱時間為3秒至60分。
  12. 如申請專利範圍第7項所述之電子封裝接點結構的製造方法，其中該介金屬化合物層是由該第一凸出電極與該第一導電材料反應以及該第二凸出電極與該第二導電材料反應而形成。
  13. 如申請專利範圍第7項所述之電子封裝接點結構的製造方法，其中該介金屬化合物層是由該第一凸出電極與該第一導電材料反應、該第二凸出電極與該第二導電材料反應、該第一電極與該第一導電材料反應以及該第二電極與該第二導電材料反應而形成。
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US9024441B2 (en) 2015-05-05

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