TWI662695B - 晶圓級晶片尺寸封裝結構 - Google Patents

晶圓級晶片尺寸封裝結構 Download PDF

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Publication number
TWI662695B
TWI662695B TW106146233A TW106146233A TWI662695B TW I662695 B TWI662695 B TW I662695B TW 106146233 A TW106146233 A TW 106146233A TW 106146233 A TW106146233 A TW 106146233A TW I662695 B TWI662695 B TW I662695B
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Taiwan
Prior art keywords
wafer
redistribution layer
conductive pad
layer
package structure
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TW106146233A
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English (en)
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TW201931580A (zh
Inventor
林育民
張道智
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財團法人工業技術研究院
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Priority to TW106146233A priority Critical patent/TWI662695B/zh
Priority to CN201810478854.9A priority patent/CN109979891B/zh
Priority to US16/194,802 priority patent/US10784297B2/en
Application granted granted Critical
Publication of TWI662695B publication Critical patent/TWI662695B/zh
Publication of TW201931580A publication Critical patent/TW201931580A/zh
Priority to US17/019,026 priority patent/US11538842B2/en

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Abstract

本發明提供一種晶圓級晶片尺寸封裝結構，包括：影像感測晶片以及晶片。影像感測晶片包括第一重分佈層，其中第一重分佈層包含導線與導電襯墊，導電襯墊形成於導線上，且導電襯墊露出於第一重分佈層的表面。晶片包括第二重分佈層，其中第二重分佈層包含導線與導電襯墊，導電襯墊形成於導線上，且導電襯墊露出於第二重分佈層的表面。晶片的面積小於影像感測晶片的面積，且晶片藉由第二重分佈層與影像感測晶片的第一重分佈層接合。

Description

晶圓級晶片尺寸封裝結構
本發明係有關於一種晶圓級晶片尺寸封裝(WLCSP)結構。
傳統影像感測模組的封裝製程是以打線封裝、或是晶片尺寸封裝(CSP)為大宗。對於整體影像感測模組系統來說，尚需借助記憶體晶片與控制晶片來進行資料的存取與控制，因此，影像感測器、記憶體晶片與控制晶片通常會組裝、整合至系統板上，而記憶體晶片、控制晶片與影像感測器間的溝通即透過此系統板來進行。
近來，由於影像感測器製程的革新與畫素的大幅提升，增加了巨量資料存取與控制的需求。對於傳統的系統整合方式，實已不足以應對市場趨勢。因此，有業者開發出將影像感測器/記憶體晶片/邏輯晶片等不同種類的晶圓以晶圓對晶圓(wafer to wafer)的方式加以整合的組裝技術，將三種元件統整於一，可大幅提升電傳輸與元件反應的速率。然而，此種技術仍有其瓶頸，要做到晶圓對晶圓接合的組裝技術，就目前而言，僅能適用於小型感測器。原因是雖記憶體晶片/邏輯晶片的晶片間距可以盡可能配合影像感測器的間距而做調整，然而，當感測器面積持續增大時，記憶體晶片/邏輯晶片的晶片 間距勢必隨之擴大，此時，單位晶圓面積中的記憶體晶片/邏輯晶片的數量就會減少，結果將使得整體晶圓的成本大幅上升。
因此，開發一種低成本、高電傳輸速率、且適用於中、大型感測器製作的晶片尺寸封裝(CSP)結構是眾所期待的。
根據本發明之一實施例，提供一種晶圓級晶片尺寸封裝結構，包括：一影像感測晶片，包括一第一重分佈層，其中該第一重分佈層包含一導線與一導電襯墊，該導電襯墊形成於該導線上，且該導電襯墊露出於該第一重分佈層的表面；以及一晶片，包括一第二重分佈層，其中該第二重分佈層包含一導線與一導電襯墊，該導電襯墊形成於該導線上，且該導電襯墊露出於該第二重分佈層的表面，其中該晶片的面積小於該影像感測晶片的面積，且該晶片藉由該第二重分佈層與該影像感測晶片的該第一重分佈層接合。
根據本發明之一實施例，提供一種晶圓級晶片尺寸封裝結構，包括：一第一晶片，包括一第一重分佈層，其中該第一重分佈層包含一導線與一導電襯墊，該導電襯墊形成於該導線上，且該導電襯墊露出於該第一重分佈層的表面；以及一第二晶片，包括一第二重分佈層，其中該第二重分佈層包含一導線與一導電襯墊，該導電襯墊形成於該導線上，且該導電襯墊露出於該第二重分佈層的表面，其中該第二晶片的面積小於該第一晶片的面積，且該第二晶片藉由該第二重分佈層與該 第一晶片的該第一重分佈層接合。
為讓本發明能更明顯易懂，下文特舉一較佳實施例，並配合所附的圖式，作詳細說明如下。
10‧‧‧晶圓級晶片尺寸封裝(WLCSP)結構
12‧‧‧影像感測晶片
14‧‧‧晶片
16‧‧‧第一重分佈層
18‧‧‧第二重分佈層
20‧‧‧第一重分佈層的導線
22‧‧‧第一重分佈層的表面
24‧‧‧第二重分佈層的導線
26‧‧‧第二重分佈層的表面
28‧‧‧第一重分佈層的導電襯墊
30‧‧‧第二重分佈層的導電襯墊
38‧‧‧第一金屬層
40‧‧‧微透鏡
42‧‧‧透光蓋層
44‧‧‧黏著層
46‧‧‧絕緣保護層
48‧‧‧內連線
50‧‧‧金屬襯墊
52‧‧‧導電球
54‧‧‧凸塊結構
56‧‧‧封閉空間
58‧‧‧模封材料層
60‧‧‧金屬導電柱
62‧‧‧保護層
64‧‧‧第一銅凸塊
66‧‧‧第二銅凸塊
68‧‧‧焊錫球
70‧‧‧底膠
100‧‧‧鏡頭模組
102‧‧‧基板
104‧‧‧主(被)動元件
106‧‧‧鏡片
108‧‧‧致動器
110‧‧‧鏡頭基座
A1‧‧‧影像感測晶片的面積
A2‧‧‧晶片的面積
H1‧‧‧金屬導電柱的高度
T1‧‧‧晶片的厚度
第1圖係根據本發明之一實施例，一種晶圓級晶片尺寸封裝結構的剖面示意圖；第2圖係根據本發明之一實施例，一種晶圓級晶片尺寸封裝結構中晶圓與晶片接合態樣的剖面放大示意圖；第3圖係根據本發明之一實施例，一種晶圓級晶片尺寸封裝結構中晶圓與晶片接合態樣的剖面放大示意圖；第4圖係根據本發明之一實施例，一種晶圓級晶片尺寸封裝結構的剖面示意圖；第5圖係根據本發明之一實施例，一種晶圓級晶片尺寸封裝結構的剖面示意圖；第6圖係根據本發明之一實施例，一種晶圓級晶片尺寸封裝結構的剖面示意圖；第7圖係根據本發明之一實施例，一種晶圓級晶片尺寸封裝結構的剖面示意圖；第8圖係根據本發明之一實施例，一種晶圓級晶片尺寸封裝結構結合鏡頭模組的剖面示意圖。
請參閱第1圖，根據本發明之一實施例，揭示一種晶圓級晶片尺寸封裝(wafer level chip scale package，WLCSP) 結構10。第1圖為晶圓級晶片尺寸封裝(WLCSP)結構10的剖面示意圖。
在本實施例中，晶圓級晶片尺寸封裝(WLCSP)結構10包括影像感測晶片12以及晶片14。影像感測晶片12包括第一重分佈層16。晶片14包括第二重分佈層18。晶片14的面積A2小於影像感測晶片12的面積A1。有關第一重分佈層16與第二重分佈層18的內部結構，以及影像感測晶片12與晶片14間的接合態樣(如圖中的虛線框處)將詳述於後。
在部分實施例中，影像感測晶片12亦可由其他感測晶片替代，例如聲波感測晶片、溫度感測晶片、濕度感測晶片、氣體感測晶片、壓力感測晶片、電感測晶片、磁感測晶片、圖像感測晶片、位移感測晶片、或光感測晶片。
在部分實施例中，晶片14可為記憶體晶片、邏輯晶片、或其他功能性晶片。
本揭露的封裝結構10可應用於車用電子領域、手持式電子裝置、機器人視覺辨識或高解析高速錄像機等巨量訊號或高速訊號傳輸的應用，但本發明不限於此。
請參閱第2圖(第2圖為第1圖中虛線框處的放大示意圖)，根據本發明之一實施例，揭示第一重分佈層16與第二重分佈層18的內部結構，以及影像感測晶片12與晶片14間的一種接合態樣。如第2圖所示，第一重分佈層16包含導線20、導電襯墊28以及覆蓋導線20的保護層，導電襯墊28形成於導線20上，且導電襯墊28露出於第一重分佈層16的表面22。第二重分佈層18包含導線24、導電襯墊30以及覆蓋導線24的保護層，導 電襯墊30形成於導線24上，且導電襯墊30露出於第二重分佈層18的表面26。在部分實施例中，導線(20、24)與導電襯墊(28、30)可包括銅。晶片14藉由其露出於第二重分佈層18的導電襯墊30與影像感測晶片12露出於第一重分佈層16的導電襯墊28接合，形成銅-銅接合(銅與銅直接接合)。
在部分實施例中，第一重分佈層16的表面22的粗糙度(Ra)大約小於1奈米。在部分實施例中，第二重分佈層18的表面26的粗糙度(Ra)大約小於1奈米。
請參閱第3圖(第3圖為第1圖中虛線框處的放大示意圖)，根據本發明之一實施例，揭示影像感測晶片12與晶片14間的一種接合態樣。如第3圖所示，於第二重分佈層18的導電襯墊30與第一重分佈層16的導電襯墊28之間，更包括形成有第一金屬層38。在部分實施例中，第一金屬層38可包括金、錫、鈷、錳、鈦、鈀、或銀與其合金。
仍請參閱第1圖，在本實施例中，於影像感測晶片12上，更包括形成有複數個微透鏡40，其相對於第一重分佈層16設置。在本實施例中，於微透鏡40上，更包括形成有透光蓋層42。在部分實施例中，透光蓋層42可包括玻璃或其他適當材料，以保護下層元件及有效促進訊號的穿透或增益。在本實施例中，於影像感測晶片12與透光蓋層42之間，更包括形成有黏著層44，覆蓋微透鏡40。在部分實施例中，黏著層44可包括任何適當的有機黏著材料。
在部分實施例中，於影像感測晶片12與透光蓋層42之間，更包括形成有封閉空間56，容納微透鏡40，如第4圖 所示。
仍請參閱第1圖，在本實施例中，於影像感測晶片12上，更包括形成有絕緣保護層46，覆蓋晶片14。在部分實施例中，絕緣保護層46可包括任何適當的模封絕緣材料。
在本實施例中，於影像感測晶片12中，更包括形成有內連線48，以電性連接影像感測晶片12中的各元件(未圖示)與第一重分佈層16。在本實施例中，於第一重分佈層16上，更包括形成有複數個金屬襯墊50，露出於絕緣保護層46。在部分實施例中，金屬襯墊50可包括鋁、銅、鎳、鋁銅合金、或鋁矽銅合金。在本實施例中，更包括形成有複數個導電球52，連接金屬襯墊50。在部分實施例中，本發明封裝結構10可進一步藉由導電球52與基板(未圖示)接合。在部分實施例中，上述與封裝結構10接合的基板可包括矽基板、陶瓷基板、玻璃纖維基板、印刷電路板、或其他符合製程需求的系統板。
在本實施例中，於影像感測晶片12上，更包括形成有複數個凸塊結構54，位於晶片14周圍，其中凸塊結構54可進一步抑制封裝結構10的翹曲現象。在一實施例，凸塊結構54可替換為功能性晶片，位於晶片14的周圍(例如：單側或雙側)，以可整合不同功能晶片於封裝結構10中並可進一步抑制封裝結構10的翹曲現象。在部分實施例中，功能性晶片可為記憶體晶片或邏輯晶片，但本發明不限於此。
本發明一實施例藉由晶片堆疊於晶圓上(chip on wafer)的組裝技術，利用銅-銅直接接合的方式(即，無焊錫球接合(bumpless interconnection))，將功能性晶片(例如記憶體晶 片或邏輯晶片)直接接合至感測晶片。此種晶片接合方式可使功能性晶片在搭配及選用上，更具靈活性，有效降低並控制整體的製作成本，相當適用於中、大型感測器的製作。此外，功能性晶片與感測晶片之間的電傳輸速度亦因銅-銅直接接合路徑而大幅提升。
請參閱第5圖，根據本發明之一實施例，揭示一種晶圓級晶片尺寸封裝(wafer level chip scale package，WLCSP)結構10。第5圖為晶圓級晶片尺寸封裝(WLCSP)結構10的剖面示意圖。
在本實施例中，晶圓級晶片尺寸封裝(WLCSP)結構10包括影像感測晶片12以及晶片14。影像感測晶片12包括第一重分佈層16。晶片14包括第二重分佈層18。晶片14的面積A2小於影像感測晶片12的面積A1。
在部分實施例中，影像感測晶片12亦可由其他感測晶片替代，例如聲波感測晶片、溫度感測晶片、濕度感測晶片、氣體感測晶片、壓力感測晶片、電感測晶片、磁感測晶片、圖像感測晶片、位移感測晶片、或光感測晶片。
在部分實施例中，晶片14可為記憶體晶片、邏輯晶片、或其他功能性晶片。
有關第一重分佈層16與第二重分佈層18的內部結構，以及影像感測晶片12與晶片14間的接合態樣，請參閱第2、3圖。
在本實施例中，於影像感測晶片12上，更包括形成有複數個微透鏡40，相對於第一重分佈層16設置。在本實施 例中，於微透鏡40上，更包括形成有透光蓋層42。在部分實施例中，透光蓋層42可包括玻璃或其他適當材料，以保護下層元件及有效促進訊號的穿透或增益。在本實施例中，於影像感測晶片12與透光蓋層42之間，更包括形成有黏著層44，覆蓋微透鏡40。在部分實施例中，黏著層44可包括任何適當的有機黏著材料。
在部分實施例中，於影像感測晶片12與透光蓋層42之間，更包括形成有封閉空間56，容納微透鏡40，如第6圖所示。
仍請參閱第5圖，在本實施例中，於影像感測晶片12上，更包括形成有模封材料層58，覆蓋晶片14。在部分實施例中，模封材料層58可包括任何適當的絕緣材料。
在本實施例中，於影像感測晶片12中，更包括形成有內連線48，以電性連接影像感測晶片12中的各元件(未圖示)與第一重分佈層16。在本實施例中，於第一重分佈層16上，更包括形成有複數個金屬導電柱60，貫穿並露出於模封材料層58。在部分實施例中，金屬導電柱60可包括銅或其他適當金屬。在部分實施例中，金屬導電柱60的高度H1大於晶片14的厚度T1。在部分實施例中，於模封材料層58上，更包括形成有保護層62，露出金屬導電柱60。在部分實施例中，保護層62可包括任何適當的絕緣材料。在本實施例中，更包括形成有複數個導電球52，連接金屬導電柱60。在部分實施例中，本發明封裝結構10可進一步藉由導電球52與基板(未圖示)接合。在部分實施例中，上述與封裝結構10接合的基板可包括矽基板、陶瓷基 板、玻璃纖維基板、印刷電路板、或其他符合製程需求的系統板。
請參閱第7圖，根據本發明之一實施例，揭示一種晶圓級晶片尺寸封裝(wafer level chip scale package，WLCSP)結構10。第7圖為晶圓級晶片尺寸封裝(WLCSP)結構10的剖面示意圖。
在本實施例中，晶圓級晶片尺寸封裝(WLCSP)結構10包括影像感測晶片12以及晶片14。影像感測晶片12包括第一重分佈層16。晶片14包括第二重分佈層18。晶片14的面積A2小於影像感測晶片12的面積A1。
在部分實施例中，影像感測晶片12亦可由其他感測晶片替代，例如聲波感測晶片、溫度感測晶片、濕度感測晶片、氣體感測晶片、壓力感測晶片、電感測晶片、磁感測晶片、圖像感測晶片、位移感測晶片、生物訊號感測晶片、或光感測晶片。
在部分實施例中，晶片14可為記憶體晶片、邏輯晶片、或其他功能性晶片。
以下詳述影像感測晶片12與晶片14間的接合態樣。
如第7圖所示，於影像感測晶片12的第一重分佈層16上，更包括形成有複數個第一銅凸塊64。於晶片14的第二重分佈層18上，更包括形成有複數個第二銅凸塊66，而於第一銅凸塊64與第二銅凸塊66之間，更包括形成有複數個焊錫球68。晶片14藉由第二銅凸塊66、焊錫球68、以及第一銅凸塊64與影 像感測晶片12接合，形成銅-焊錫球-銅的接合態樣。
在本實施例中，於影像感測晶片12上，更包括形成有複數個微透鏡40，相對於第一重分佈層16設置。在本實施例中，於微透鏡40上，更包括形成有透光蓋層42。在部分實施例中，透光蓋層42可包括玻璃或其他適當材料，以保護下層元件及有效促進訊號的穿透或增益。在本實施例中，於影像感測晶片12與透光蓋層42之間，更包括形成有黏著層44，覆蓋微透鏡40。在部分實施例中，黏著層44可包括任何適當的有機黏著材料。
在部分實施例中，於影像感測晶片12與透光蓋層42之間，更包括形成有封閉空間(未圖示)，容納微透鏡40。
在本實施例中，於影像感測晶片12上，更包括形成有絕緣保護層46。在部分實施例中，絕緣保護層46可包括任何適當的介電絕緣材料。在本實施例中，於絕緣保護層46與晶片14之間的部分區域，更包括填入底膠70。
在本實施例中，於影像感測晶片12中，更包括形成有內連線48，以電性連接影像感測晶片12中的各元件(未圖示)與第一重分佈層16。在本實施例中，於第一重分佈層16上，更包括形成有複數個金屬襯墊50，露出於絕緣保護層46。在部分實施例中，金屬襯墊50可包括鋁、鋁銅合金、或鋁矽銅合金。在本實施例中，更包括形成有複數個導電球52，連接金屬襯墊50。在部分實施例中，本發明封裝結構10可進一步藉由導電球52與基板(未圖示)接合。在部分實施例中，上述與封裝結構10接合的基板可包括矽基板、陶瓷基板、玻璃纖維基板、印刷電 路板、或其他符合製程需求的系統板。
請參閱第8圖，根據本發明之一實施例，揭示一種晶圓級晶片尺寸封裝(WLCSP)結構10結合鏡頭模組100的結構。第8圖為晶圓級晶片尺寸封裝(WLCSP)結構10結合鏡頭模組100的剖面示意圖。
如第8圖所示，將晶圓級晶片尺寸封裝(WLCSP)結構10接合於基板102上。而鏡頭模組100亦同時接合於基板102上。
在部分實施例中，與基板102接合的晶圓級晶片尺寸封裝(WLCSP)結構10可包括如第1、4、5、6、7圖所示的封裝結構。
在部分實施例中，基板102可包括矽基板、陶瓷基板、玻璃纖維基板、印刷電路板、或其他符合製程需求的系統板。在本實施例中，於基板102上，更包括形成有複數個主(被)動元件104。鏡頭模組100包括鏡片106、致動器108、以及鏡頭基座110。
本發明一實施例之晶圓級晶片尺寸封裝(WLCSP)結構與鏡頭模組同時嵌於基板上，使得晶圓級晶片尺寸封裝(WLCSP)結構中的影像感測晶片與鏡片形成良好的共平面性，有效解決了影像感測晶片與鏡片之間可能產生的歪斜現象。且晶圓級晶片尺寸封裝(WLCSP)結構中，影像感測晶片與其他功能性晶片(例如記憶體晶片或邏輯晶片)之間的訊號傳輸路徑，也因兩晶片藉由銅-銅對接的連接方式而縮短，大幅提升運算速度。
雖然本發明已以數個較佳實施例發明如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。

Claims (15)

  1. 一種晶圓級晶片尺寸封裝結構，包括：一影像感測晶片，包括一第一重分佈層，其中該第一重分佈層包含一導線與一導電襯墊，該導電襯墊形成於該導線上，且該導電襯墊露出於該第一重分佈層的表面；以及一晶片，包括一第二重分佈層，其中該第二重分佈層包含一導線與一導電襯墊，該導電襯墊形成於該導線上，且該導電襯墊露出於該第二重分佈層的表面，其中該晶片的面積小於該影像感測晶片的面積，且該晶片的該第二重分佈層的表面與該影像感測晶片的該第一重分佈層的表面直接接觸。
  2. 如申請專利範圍第1項所述的晶圓級晶片尺寸封裝結構，其中該導線與該導電襯墊包括銅。
  3. 如申請專利範圍第1項所述的晶圓級晶片尺寸封裝結構，其中該晶片藉由其露出於該第二重分佈層的該導電襯墊與該影像感測晶片露出於該第一重分佈層的該導電襯墊接合。
  4. 如申請專利範圍第3項所述的晶圓級晶片尺寸封裝結構，更包括一第一金屬層，形成於該第二重分佈層的該導電襯墊與該第一重分佈層的該導電襯墊之間。
  5. 如申請專利範圍第1項所述的晶圓級晶片尺寸封裝結構，更包括複數個微透鏡，形成於該影像感測晶片上，相對於該第一重分佈層設置。
  6. 如申請專利範圍第5項所述的晶圓級晶片尺寸封裝結構，更包括一透光蓋層，形成於該等微透鏡上。
  7. 如申請專利範圍第6項所述的晶圓級晶片尺寸封裝結構，更包括一黏著層，形成於該影像感測晶片與該透光蓋層之間，並覆蓋該等微透鏡。
  8. 如申請專利範圍第6項所述的晶圓級晶片尺寸封裝結構，更包括一封閉空間，形成於該影像感測晶片與該透光蓋層之間，並容納該等微透鏡。
  9. 如申請專利範圍第1項所述的晶圓級晶片尺寸封裝結構，更包括一絕緣保護層或一模封材料層，形成於該影像感測晶片上，並覆蓋該晶片。
  10. 如申請專利範圍第9項所述的晶圓級晶片尺寸封裝結構，更包括複數個金屬襯墊，形成於該第一重分佈層上，並露出於該絕緣保護層。
  11. 如申請專利範圍第10項所述的晶圓級晶片尺寸封裝結構，更包括複數個導電球，連接該等金屬襯墊。
  12. 如申請專利範圍第9項所述的晶圓級晶片尺寸封裝結構，更包括複數個金屬導電柱，形成於該第一重分佈層上，貫穿並露出於該模封材料層。
  13. 如申請專利範圍第12項所述的晶圓級晶片尺寸封裝結構，更包括複數個導電球，連接該等金屬導電柱。
  14. 如申請專利範圍第1項所述的晶圓級晶片尺寸封裝結構，更包括複數個凸塊結構，位於該影像感測晶片上，位於該晶片的單側或雙側。
  15. 一種晶圓級晶片尺寸封裝結構，包括：一第一晶片，包括一第一重分佈層，其中該第一重分佈層包含一導線與一導電襯墊，該導電襯墊形成於該導線上，且該導電襯墊露出於該第一重分佈層的表面；以及一第二晶片，包括一第二重分佈層，其中該第二重分佈層包含一導線與一導電襯墊，該導電襯墊形成於該導線上，且該導電襯墊露出於該第二重分佈層的表面，其中該第二晶片的面積小於該第一晶片的面積，且該第二晶片的該第二重分佈層的表面與該第一晶片的該第一重分佈層的表面直接接觸。
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