TW201740521A - 半導體封裝結構及其形成方法 - Google Patents

半導體封裝結構及其形成方法 Download PDF

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Publication number
TW201740521A
TW201740521A TW106104372A TW106104372A TW201740521A TW 201740521 A TW201740521 A TW 201740521A TW 106104372 A TW106104372 A TW 106104372A TW 106104372 A TW106104372 A TW 106104372A TW 201740521 A TW201740521 A TW 201740521A
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Taiwan
Prior art keywords
redistribution layer
layer structure
semiconductor package
molding compound
conductive
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TW106104372A
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English (en)
Inventor
林子閎
彭逸軒
蕭景文
劉乃瑋
黃偉哲
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聯發科技股份有限公司
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Publication of TW201740521A publication Critical patent/TW201740521A/zh

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Abstract

本發明提供了一種半導體封裝結構及其形成方法。其中該半導體封裝結構包括：一第一半導體封裝。該第一半導體封裝包括：一第一重分佈層(RDL)結構，具有相對設置的一第一表面及一第二表面。一第一半導體晶粒設置在該第一表面上並且電性耦接至該第一RDL結構。一第一模塑料設置在該第一表面上並且圍繞該第一半導體晶粒。複數個焊球或者導電柱結構設置在該第一模塑料中並且通過該第一RDL結構電性耦接至該第一半導體晶粒。

Description

半導體封裝結構及其形成方法
本發明涉及封裝領域，特別係涉及一種半導體封裝結構(例如扇出封裝結構)及其形成方法。
近年來，由於電子產品已變得越來越多功能並且尺寸已經縮小，因此業界期望半導體裝置的製造者能夠在單個半導體晶圓上形成更多的裝置，使得含有這些裝置的電子產品能夠更加緊湊。作為對此種需求的回應，開發了PoP(Package-on-package，封裝上封裝)技術。PoP技術使得兩個或者更多的封裝通過使用標准接口來安裝(即堆疊)於彼此之頂上，其中該標准接口用於在該兩個或更多的封裝之間路由訊號。PoP技術允許在電子產品中具有更高的元件密度，其中電子產品諸如為行動電話、PDA(Personal Digital Assistant，個人數位助理)和數位相機。
在此種PoP結構中，一般使用穿過模塑料的通孔(through vias)來電性連接堆疊的封裝，其中該通孔有時被稱為穿過封裝的通孔(Through Package Vias，TPV)或者穿過插入層的通孔(Through Interposer Vias，TIV)。TPV/TIV的形成製程至少包括：微影(lithography)製程，用來形成TPV/TIV 開口；以及電鍍製程，使用導電材料來填充這些開口。接著，執行模塑(molding)製程及研磨(grinding)製程以形成TPV/TIV。
但是，這些用來形成TPV/TIV的製程係複雜且昂貴的。如此，難以降低半導體封裝的製造成本，如此，期望創新的半導體封裝結構。
因此，本發明之主要目的即在於提供一種半導體封裝結構及其形成方法，可以降低製造成本。
根據本發明至少一個實施例之一種半導體封裝結構，包括：一第一半導體封裝，該第一半導體封裝包括：一第一重分佈層結構，具有相對設置的一第一表面與一第二表面；一第一半導體晶粒，設置在該第一表面上並且電性耦接至該第一重分佈層結構；一第一模塑料，設置在該第一表面上，並且圍繞該第一半導體晶粒；以及複數個導電結構，嵌入於該第一模塑料中，並且電性耦接該第一重分佈層結構；其中，每個導電結構包括：一焊球，嵌入於該第一模塑料中並且電性耦接至該第一重分佈層結構，並且該第一模塑料包括：複數個開口，分別露出該每個導電結構中的該焊球；或者，每個導電結構包括：一導電柱結構，設置於該第一模塑料中並且從該第一模塑料中露出，其中該導電柱結構包括：一焊料，接合在該第一重分佈層結構上並且電性耦接該第一重分佈層結構。
根據本發明至少一個實施例之一種半導體封裝結構的形成方法，包括：在一載體基底上形成一第一重分佈層結 構，其中該第一重分佈層結構具有相對設置的一第一表面與一第二表面，並且該第二表面附著至該載體基底；在該第一表面上形成複數個焊球；將一第一半導體晶粒安裝至該第一表面上，其中該第一半導體晶粒通過該第一重分佈層結構電性耦接至該等焊球；在該第一表面上形成一第一模塑料，以使該第一半導體晶粒和該等焊球嵌入於該第一模塑料中；在該第一模塑料中形成複數個開口，以露出該等焊球。
根據本發明至少一個實施例之一種半導體封裝結構的形成方法，包括：在一載體基底上形成一第一重分佈層結構，其中該第一重分佈層結構具有相對設置的一第一表面與一第二表面，並且該第二表面附著至該載體基底；在該第一表面上形成複數個導電柱結構，其中每個導電柱結構包括：一焊料，接合在該第一重分佈層結構上並且電性耦接至該第一重分佈層結構；將一第一半導體晶粒安裝至該第一表面上，其中該第一半導體晶粒通過該第一重分佈層結構電性耦接至該等導電柱結構；在該第一表面上形成一第一模塑料，以使該第一半導體晶粒和該等導電柱結構嵌入於該第一模塑料中，其中該等導電柱結構從該第一模塑料中露出。
本發明實施例，第一模塑料中的通孔結構(即導電結構)為採用焊球配合開口的結構或者為含有焊料的導電柱結構，從而使得該通孔結構的的形成過程中可以無需使用微影和電鍍製程，從而降低了半導體封裝結構的製造成本。
10、10'‧‧‧第一半導體封裝
140‧‧‧第一導電結構
300‧‧‧第一半導體晶粒
110‧‧‧第一重分佈層結構
301、605‧‧‧接墊
311‧‧‧導電結構
110a‧‧‧第一表面
110b‧‧‧第二表面
102‧‧‧金屬間介電層
103‧‧‧第一導電線路
101‧‧‧第二導電線路
400、500‧‧‧電子元件
130‧‧‧第一模塑料
120、120'‧‧‧通孔
112‧‧‧金屬柱
111‧‧‧焊料
200‧‧‧載體基底
20‧‧‧第二半導體封裝
610‧‧‧第二RDL結構
610a‧‧‧第三表面
610b‧‧‧第四表面
700‧‧‧第二半導體晶粒
800‧‧‧第三半導體晶粒
612、614‧‧‧接合線
630‧‧‧第二模塑料
640‧‧‧第二導電結構
130‧‧‧開口
通過閱讀接下來的詳細描述以及參考所附的圖式 所做的示例，可以更全面地理解本發明，其中：第1A~1E圖為剖面示意圖，用來說明根據本發明一些實施例的半導體封裝結構的形成方法；第2圖為根據本發明一些實施例的具有PoP結構的半導體封裝結構的剖面示意圖；第3A~3D圖為剖面示意圖，用來說明根據本發明一些實施例的半導體封裝結構的形成方法；第4圖為根據本發明一些實施例的具有PoP結構的半導體封裝結構的剖面示意圖。
以下描述係實現本發明的較佳預期方式。該描述僅係作為說明本發明一般原理的目的，並且不應被視為限制。本發明的範圍可參考所附的申請專利範圍來確定。
本發明將通過參考詳細的實施例及參考確定的圖式來描述，但是本發明不限制於此，並且本發明僅由申請專利範圍限定。此中描述的圖式僅為原理圖而非限制。在圖式中，出於說明目的以及非按比例繪制，可能誇大了某些元件的尺寸。圖式中的尺寸及相對尺寸不對應本發明實踐中的實際尺寸。
第1E圖為根據本發明一些實施例的半導體封裝結構的第一半導體封裝10的剖面示意圖。在一些實施例中，該半導體封裝結構為一覆晶半導體封裝結構。參考第1E圖，該半導體封裝結構包括：一第一半導體封裝10，可以安裝在一基底(未示出)上。在一些實施例中，該第一半導體封裝10可 以包括：一系統單晶片(System-On-Chip，SOC)封裝。另外，該基底可以包括：一印刷電路板(Printed Circuit Board，PCB)並且可以由聚丙烯(polypropylene，PP)形成。在一些實施例中，該基底可以包括：一封裝基板。該第一半導體封裝10通過一接合製程(bonding process)安裝於該基底上。例如，該第一半導體封裝10包括：一第一導電結構140，其通過該接合製程安裝於該基底上並且電性耦接至該基底。
該第一半導體封裝10包括：一第一半導體晶粒300(諸如SOC晶粒)以及一第一重分佈層(Redistribution Layer，RDL)結構110。該SOC晶粒例如可以包括：一邏輯晶粒，該邏輯晶粒包括：一中央處理單元(Central Processing Unit，CPU)、一圖像處理單元(Graphics Processing Unit，GPU)、一動態隨機訪問記憶體(Dynamic Random Access Memory，DRAM)控制器或者他們的任意組合。
如第1E圖所示，該第一半導體晶粒300之接墊301係電性耦接至該第一半導體晶粒300的電路(未示出)。在一些實施例中，該接墊301屬於該第一半導體晶粒300的互連結構(未示出)的最上層金屬層。該接墊301與對應的導電結構311接觸，例如導電凸塊、導電柱(post)或者焊膏(solder paste)。需要注意的是，該半導體封裝結構中整合的半導體晶粒的數目不限制於本實施例公開的數量。
該第一RDL結構110，也稱為扇出結構，具有相對設置的一第一表面110a以及一第二表面110b。該第一半導體晶粒300設置於該第一表面110a上。該第一半導體晶粒300 通過導電結構311電性耦接至該第一RDL結構110。
在本實施例中，該第一RDL結構110包括：一條或者複數條導電線路(conductive trace)，設置於一金屬間介電(Inter-Metal Dielectric，IMD)層102中。例如，複數條第一導電線路103設置在該IMD層102的第一層級處，並且該等第一導電線路103中的至少一條係電性連接至該第一半導體晶粒300。另外，第二導電線路101係設置在該IMD層102的第二層級處，該第二層級不同於該第一層級。在一些實施例中，該IMD層102可以為單層或者多層結構。另外，該IMD層102可以由有機材料或者無機材料形成，該有機材料包括：聚合物基材料，該無機材料包括：氮化矽(SiNx)、氧化矽(SiOx)、石墨烯，等等。
在一些實施例中，該IMD層102為高k值介電層，其中k為介電層的介電常數。在其他的一些實施例中，該IMD層102可以由光敏材料形成，例如乾膜光阻(dry film photoresist)、或者貼膜(taping film)。
第二導電線路101的接墊部分自IMD層102的開口露出，並且連接至設置在第二表面110b上的第一導電結構140。另外，需要注意的是，在第1E圖中示出的第一RDL結構110的導電線路的數目僅是示例，而不是對本發明的限制。
在本實施例中，該第一半導體封裝10進一步包括：至少一個電子元件400，諸如整合被動裝置(Integrated Passive Device，IPD)，設置在該第一表面110a上。該IPD係通過第一RDL結構110電性耦接至該第一半導體晶粒300。在 一些實施例中，該IPD可以包括：電容、電感、電阻或者他們的組合。另外，該IPD可以為電容，該電容含有至少一個耦接至該等第一導電線路103之一的電極。另外，該第一半導體封裝10可以包括：至少一個電子元件500，諸如IPD，設置在該第二表面110b上。該IPD也通過該第一RDL結構電性耦接至該第一半導體晶粒300。類似地，該電子元件500可以為電容，該電容含有至少一個耦接至該等第二導電線路101之一的電極。
在本實施例中，如第1E圖所示，該第一半導體封裝10進一步包括：一第一模塑料130，設置在該第一表面110a上，並且圍繞該第一半導體晶粒300。在一些實施例中，該第一模塑料130可以由環氧樹脂、樹脂、可塑聚合物或者類似物形成。
在本實施例中，第一半導體封裝10進一步包括：一通孔(through vias)120，嵌入於該第一模塑料130中，並且穿過該第一模塑料130。在一些實施例中，該通孔120包括：一導電柱結構，設置在該第一模塑料130中並且從該第一模塑料130露出。該通孔120充當TIV或者TPV。在此情形中，每個導電柱結構包括：一金屬柱112(如銅柱)以及一焊料111，該焊料111接合在該金屬柱112的一端與該第一導電線路103的接墊部分之間，使得該導電柱結構電性耦接至該第一RDL結構110。另外，通孔120可以圍繞該第一半導體晶粒300。
該第一導電結構140通過該第一RDL結構110與第一模塑料130分隔開。在一些實施例中，該第一導電結構140 可以包括：導電凸塊結構(諸如銅或者焊料凸塊結構)，導電柱結構，導線結構，或者導電膏結構。
第1A~1E圖為剖面示意圖，用來說明根據本發明一些實施例的半導體封裝結構的形成方法。如第1A圖所示，提供了一載體基底200。在一些實施例中，該載體基底200可以包括：矽或者玻璃晶圓。通過沉積及圖案化製程於該載體基底200上形成一第一RDL結構110。在本實施例中，該第一RDL結構具有相對設置的一第一表面110a和一第二表面110b。該第二表面110b附著至該載體基底200。在一些實施例中，該第一RDL結構110包括：複數條導電線路，設置在一IMD層102中。例如，第一導電線路103設置在該IMD層102的第一層級處。另外，第二導電線路101設置在該IMD層102的第二層級處，其中第一層級不同於第二層級。
如第1B圖所示，通孔120，諸如導電柱結構，係形成於該第一表面110a上。在一些實施例中，每個導電柱包括：一金屬柱112(如銅柱)以及一焊料111，該焊料111形成於該金屬柱112的一端上。在此情形中，通過網印(screen printing)製程來形成該導電柱結構，使得該導電柱結構通過該焊料111電性耦接至該第一導電線路103的接墊部分。
如第1C圖所示，一第一半導體晶粒300以及一可選的電子元件400安裝至該第一表面110a上，使得該第一半導體晶粒300以及該電子元件400係通過第一RDL結構110電性耦接至通孔120(即導電柱結構)。在一些實施例中，通孔120圍繞該第一半導體晶粒300及該電子元件400。
在一些實施例中，該第一半導體晶粒300為SOC晶粒。該SOC晶粒例如可以包括：邏輯晶粒，其中該邏輯晶粒包括：CPU、GPU、DRAM控制器或者他們的任意組合，並且該SOC晶粒通過覆晶技術安裝至該第一RDL結構110上。該第一半導體晶粒300包括：一接墊301，接觸對應的導電結構311(諸如導電凸塊、柱或者焊膏)，使得該第一半導體晶粒300通過該導電結構311安裝在該第一導電線路103上。
在一些實施例中，該電子元件400(諸如電容、電感、電阻或者他們的組合)通過表面安裝技術(Surface Mount Technology，SMT)安裝至第一RDL結構110上，使得該電子元件400電性耦接至第一導電線路103。
如第1D圖所示，一第一模塑料130形成於第一表面110a上，以完全覆蓋第一半導體晶粒300以及通孔120(即導電柱結構)。也就是說，第一半導體晶粒300及通孔120嵌入於該第一模塑料130中。
在一些實施例中，該第一模塑料130在大致為液體時使用，接著通過化學反應固化，例如在環氧樹脂或者樹脂中。在其他的一些實施例中，該第一模塑料130可以為紫外(ultraviolet，UV)或者熱固化聚合物，其中該UV或者熱固化聚合物充當能夠在第一半導體晶粒300與電子元件400周圍形成的凝膠或者可塑固體使用；接著，通過UV或者熱固化製程來固化該第一模塑料130。第一模塑料130可以按照模型(未示出)來固化。
在第一模塑料130形成之後，在第一模塑料130 的頂面上執行研磨製程，諸如化學機械研磨(Chemical Mechanical Polishing，CMP)，以使得通孔120(即導電柱結構)從第一模塑料130露出。在一些實施例中，在執行研磨製程之後，第一半導體晶粒300也從第一模塑料130露出。在一些實施例中，在執行完研磨製程之後，第一半導體晶粒300不從第一模塑料130露出。
如第1E圖所示，將載體基底200從第二表面110b移除。此後，一可選的電子元件500可以通過SMT安裝至第二表面500上，使得該電子元件500電性耦接至第二導電線路101的接墊部分，其中該電子元件500相同或者不同於該電子元件400。
另外，在第二表面110b上形成一第一導電結構140，使得該第一導電結構140電性耦接至第二導電線路101的接墊部分。如此，完成了第一半導體封裝10。在一些實施例中，第一導電結構140圍繞電子元件500。另外，第一導電結構140可以包括：導電凸塊結構(諸如銅凸塊或者焊料凸塊結構)，導電柱結構，導電線結構，或者導電膏結構。
第2圖為根據本發明實施例的具有PoP結構的半導體封裝結構的剖面示意圖。以下實施例中元件的描述，若有相同或者類似於先前參考第1E圖已描述了的，出於簡潔而省略。在本實施例中，該半導體封裝結構類似於第1E圖所示的半導體封裝結構，所不同之處在於：本實施例的半導體封裝結構進一步包括：一第二半導體封裝20，堆疊在第1E圖所示的第一半導體封裝10之上。該第二半導體封裝20可以包括：一 記憶體封裝，例如DRAM封裝。
如第2圖所示，提供了第1E圖所示的第一半導體封裝10。在該第一模塑料130的上方形成一第二RDL結構610，該第二RDL結構610也被稱為扇出結構。在本實施例中，該第二RDL結構610的結構和形成類似於第一RDL結構110。在本實施例中，該第二RDL結構610具有相對設置的一第三表面610a及一第四表面610b。該第四表面610b面向該第一模塑料130。在一些實施例中，該第二RDL結構610包括：一導電線路，設置在一IMD層602中，該IMD層602相同或者類似於IMD層102。例如，第三導電線路603係設置在IMD層602的第一層級處。另外，第四導電線路601係設置在IMD層602的第二層級處，其中第二層級不同於第一層級。
在一些實施例中，一個或更多的半導體晶粒依次地堆疊在第三表面610a上，其中該半導體晶粒包括：記憶體裝置。例如，第二半導體晶粒700(如DRAM晶粒)使用黏著劑(未示出)安裝至第三表面610a上。另外，第三半導體晶粒800(如DRAM晶粒)使用黏著劑(paste)堆疊在第二半導體晶粒700上。第二和第三半導體晶粒700和800的接墊(未示出)分別通過接合線(諸如接合線612和614)耦接至第二RDL結構610的接墊605，使得第二和第三半導體晶粒700和800係電性耦接至第二RDL結構610。需要注意的是，第二半導體封裝20中堆疊的半導體晶粒的數目不限制於公開的實施例。
在一些實施例中，在第三表面610a上形成一第二 模塑料630，以完全覆蓋第二和第三半導體晶粒700和800，使得該第二模塑料630圍繞第二和第三半導體晶粒700和800。也就是說，第二和第三半導體晶粒700和800嵌入於第二模塑料630中。第二模塑料630的材料和形成相同或者類似於第一模塑料130。
在一些實施例中，在形成第二模塑料630之後，在第四表面610b上形成一第二導電結構640。此後，將第二導電結構640接合至第一模塑料130中露出的通孔120(即導電柱結構)上，使得第一RDL結構110通過第二導電結構640和通孔120電性耦接至第二RDL結構610。如此，完成第二半導體封裝20，並且將其堆疊在第一半導體封裝10上，以便於形成具有PoP結構的半導體封裝結構。
根據前述的實施例，半導體封裝結構被設計為在第一半導體封裝中製造用來充當TPV/TIV的導電柱結構。該導電柱結構提供兼容於半導體封裝結構的製程。
另外，沒有使用微影及電鍍製程來形成導電柱結構。相應地，可以降低半導體封裝結構的製造成本。另外，由於在安裝半導體晶粒之前，形成RDL結構，因此可以將已知合格晶粒(KGD)安裝至RDL結構上，從而提高半導體封裝結構的良品率。
另外，被動裝置可以嵌入於模塑料中，以便於對半導體封裝結構的系統整合提供設計彈性。
第3D圖為根據本發明實施例的半導體封裝結構的第一半導體封裝10'的剖面示意圖。以下實施例的元件描述， 有相同或者類似於參考第1E圖已描述了的，出於簡潔而省略。在本實施例中，該第一半導體封裝10'類惟於第1E圖所示的第一半導體封裝10，所不同之處在於：該第一半導體封裝10'使用焊球來充當嵌入於第一模塑料130中並且從第一模塑料130中露出的通孔120'(如TPV/TIV)。
在一些實施例中，如第3D圖所示第一模塑料130包括：複數個開口130a，並且這些開口130a對應地露出通孔120'(即焊球)。在此情形中，每個焊球接合至第一導電線路103的接墊部分上，使得導電柱結構係電性耦接至第一RDL結構110。另外，通孔120'圍繞第一半導體晶粒300與電子元件400。
第3A~3D圖為剖面示意圖，用於示意根據本發明實施例的形成半導體封裝結構的方法。以下實施例的元件描述，以相同或者類似於參考第1A~1E圖已描述了的，出於簡潔而省略。如第3A圖所示，提供第1A圖所示的結構。
此後，在第一表面110a上形成通孔120'，諸如焊球，使得焊球係電性耦接至第一導電線路103的接墊部分。在一些實施例中，通過網印製程來形成焊球。
如第3B圖所示，通過第1C圖所示的方法來將第一半導體晶粒300及可選的電子元件400安裝至第一表面110a上，使得第一半導體晶粒300與電子元件400係通過第一RDL結構110電性耦接至通孔120'(即，焊球)。
如第3C圖所示，通過第1D圖所示的方法來在第一表面110a上形成第一模塑料130。如此，第一模塑料130 可以完全地覆蓋第一半導體晶粒300和通孔120'(即焊球)。
在一些實施例中，在形成第一模塑料130之後，在第一模塑料130的頂面上執行鐳射鑽孔製程，以在第一模塑料130中形成開口130a並且開口130a對應上面的通孔120'(即焊球)。如此，通孔120'係通過開口130a從第一模塑料130露出。
如第3D圖所示，將載體基底200從第二表面110b上移除。此後，將可選的電子元件500安裝至第二表面110b上。另外，在第二表面110b上形成第一導電結構140。通過第1E圖所示的方法來形成電子元件500與第一導電結構140。如此，完成了第一半導體封裝10'。
第4圖為根據本發明一些實施例的具有PoP結構的半導體封裝結構的剖面示意圖。以下實施例的元件描述，有相同或者類似於參考第2和3D圖已描述了的，出於簡潔而不再重複。在本實施例中，半導體封裝結構類似於第2圖所示的半導體封裝結構，所不同之處在於：本實施例的半導體封裝結構包括：第3D圖所示的第一半導體封裝10'，堆疊在第2圖所示的第二導體封裝20的下方。
如第4圖所示，提供了第3D圖所示的第一半導體封裝10'和第2圖所示的第二半導體封裝20。第二半導體封裝20通過第二導電結構640接合至第一半導體封裝10'。在一些實施例中，在第四表面610b上的第二導電結構640填充對應的開口130，以接觸露出的通孔120'(即焊球)。如此，完成具有PoP結構的半導體封裝結構。
根據前述的實施例，半導體封裝結構被設計為在第一半導體封裝中製造用於充當TPV/TIV的焊球。焊球提供兼容用於半導體封裝結構的製程。
另外，沒有使用微影和電鍍製程來形成焊球。相應地，半導體封裝結構的製造成本可以降低。
另外，由於在安裝半導體晶粒之前，形成RDL結構，因此可以將已知合格晶粒(KGD)安裝至RDL結構上，從而提高半導體封裝結構的良品率。
另外，被動裝置嵌入於模塑料中，以便於為半導體封裝結構的系統整合提供設計彈性。
以上所述僅為本發明的較佳實施例而已，並不用以限制本發明，凡在本發明的精神和原則之內所作的任何修改、等同替換和改進等，均應包含在本發明的保護範圍之內。
10‧‧‧第一半導體封裝
140‧‧‧第一導電結構
300‧‧‧第一半導體晶粒
110‧‧‧第一重分佈層結構
301‧‧‧接墊
311‧‧‧導電結構
110a‧‧‧第一表面
110b‧‧‧第二表面
102‧‧‧金屬間介電層
103‧‧‧第一導電線路
101‧‧‧第二導電線路
400、500‧‧‧電子元件
130‧‧‧第一模塑料
120‧‧‧通孔
112‧‧‧金屬柱
111‧‧‧焊料

Claims (23)

  1. 一種半導體封裝結構，包括：一第一半導體封裝，該第一半導體封裝包括：一第一重分佈層結構，具有相對設置的一第一表面與一第二表面；一第一半導體晶粒，設置在該第一表面上並且電性耦接至該第一重分佈層結構；一第一模塑料，設置在該第一表面上，並且圍繞該第一半導體晶粒；以及複數個導電結構，嵌入於該第一模塑料中，並且電性耦接該第一重分佈層結構；其中，每個導電結構包括：一焊球，嵌入於該第一模塑料中並且電性耦接至該第一重分佈層結構，並且該第一模塑料包括：複數個開口，分別露出該每個導電結構中的該焊球；或者，每個導電結構包括：一導電柱結構，設置於該第一模塑料中並且從該第二模塑料中露出，其中該導電柱結構包括：一焊料，接合在該第一重分佈層結構上並且電性耦接該第一重分佈層結構。
  2. 如申請專利範圍第1項所述的半導體封裝結構，其中，該第一半導體封裝進一步包括：一電子元件，設置在該第一或第二表面上，並且電性耦接至該第一重分佈層結構。
  3. 如申請專利範圍第2項所述的半導體封裝結構，其中，該電子元件包括：電阻、電容、電感或者他們的組合。
  4. 如申請專利範圍第1項所述的半導體封裝結構，其中，該第一半導體封裝進一步包括：複數個第一導電結構，設置在該第二表面上並且電性耦接至該第一重分佈層結構。
  5. 如申請專利範圍第1項所述的半導體封裝結構，其中，進一步包括：一第二半導體封裝，堆疊在該第一半導體封裝上；其中，該第二半導體封裝包括：一第二重分佈層結構，電性耦接至該第一重分佈層結構，並且具有相對設置的一第三表面和一第四表面；一第二半導體晶粒，設置在該第三表面上並且電性耦接至該第二重分佈層結構；以及一第二模塑料，設置在該第三表面上並且圍繞該第二半導體晶粒。
  6. 如申請專利範圍第5項所述的半導體封裝結構，其中，該第二半導體封裝進一步包括：一第三半導體晶粒，設置在該第二半導體晶粒上，並且由該第二模塑料圍繞，並且電性耦接至該第一重分佈層結構。
  7. 如申請專利範圍第6項所述的半導體封裝結構，其中，該第二和第三半導體晶粒分別包括一記憶體裝置。
  8. 如申請專利範圍第5項所述的半導體封裝結構，其中，當該每個導電結構包括該焊球時，該第二半導體封裝進一步包括：複數個第二導電結構，設置在該第四表面上，並且每個第二導電結構延伸進對應的該開口，以電性耦接在該焊球和 該第二重分佈層結構之間。
  9. 如申請專利範圍第5項所述的半導體封裝結構，其中，當該每個導電結構包括該導電柱結構時，該第二半導體封裝進一步包括：複數個第二導電結構，設置在該第四表面與該露出的導電柱結構之間，使得該等第二導電結構電性耦接在該第二重分佈層結構與該導電柱結構之間。
  10. 一種半導體封裝結構的形成方法，包括：在一載體基底上形成一第一重分佈層結構，其中該第一重分佈層結構具有相對設置的一第一表面與一第二表面，並且該第二表面附著至該載體基底；在該第一表面上形成複數個焊球；將一第一半導體晶粒安裝至該第一表面上，其中該第一半導體晶粒通過該第一重分佈層結構電性耦接至該等焊球；在該第一表面上形成一第一模塑料，以使該第一半導體晶粒和該等焊球嵌入於該第一模塑料中；以及在該第一模塑料中形成複數個開口，以露出該等焊球。
  11. 如申請專利範圍第10項所述的方法，其中，進一步包括：從該第一重分佈層結構移除該載體基底；以及在移除該載體基底之前，將一電子元件安裝至該第一表面上，或者，在移除該載體基底之後，將一電子元件安裝至該第二表面上。
  12. 如申請專利範圍第11項所述的方法，其中，該電子元件包括：電阻、電容、電感或者他們的組合。
  13. 如申請專利範圍第10項所述的方法，其中，進一步包括，從該第一重分佈層結構移除該載體基底；以及在該第二表面上形成複數個第一導電結構。
  14. 如申請專利範圍第10項所述的方法，其中，進一步包括：從該第一重分佈層結構移除該載體基底；在該第一模塑料的上方形成一第二重分佈層結構，其中該第二重分佈層結構具有相對設置的一第三表面與一第四表面，其中該第四表面面向該第一模塑料；以及在該第四表面上和該複數個開口中形成複數個第二導電結構，使得該等第二導電結構電性耦接在該等焊球與該第二重分佈層結構之間。
  15. 如申請專利範圍第14項所述的方法，其中，進一步包括：在該第三表面上形成一個或複數個堆疊的第二半導體晶粒；以及在該第三表面上形成一第二模塑料，使得該第二模塑料圍繞該一個或複數個堆疊的第二半導體晶粒。
  16. 如申請專利範圍第15項所述的方法，其中，該一個或複數個堆疊的第二半導體晶粒均為記憶體裝置。
  17. 一種半導體封裝結構的形成方法，包括：在一載體基底上形成一第一重分佈層結構，其中該第一重分佈層結構具有相對設置的一第一表面與一第二表面，並且該第二表面附著至該載體基底；在該第一表面上形成複數個導電柱結構，其中每個導電柱結構包括：一焊料，接合在該第一重分佈層結構上並且電 性耦接至該第一重分佈層結構；將一第一半導體晶粒安裝至該第一表面上，其中該第一半導體晶粒通過該第一重分佈層結構電性耦接至該等導電柱結構；以及在該第一表面上形成一第一模塑料，以使該第一半導體晶粒和該等導電柱結構嵌入於該第一模塑料中，其中該等導電柱結構從該第一模塑料中露出。
  18. 如申請專利範圍第17項所述的方法，其中，進一步包括：從該第一重分佈層結構移除該載體基底；以及在移除該載體基底之前，將一電子元件安裝至該第一表面上，或者，在移除該載體基底之後，將一電子元件安裝至該第二表面上。
  19. 如申請專利範圍第18項所述的方法，其中，該電子元件包括：電阻、電容、電感或者他們的組合。
  20. 如申請專利範圍第17項所述的方法，其中，進一步包括：從該第一重分佈層結構移除該載體基底；以及在該第二表面上形成複數個第一導電結構。
  21. 如申請專利範圍第17項所述的方法，其中，進一步包括：從該第一重分佈層結構移除該載體基底；在該第一模塑料的上方形成一第二重分佈層結構，其中該第二重分佈層結構具有相對設置的一第三表面與一第四表面，其中該第四表面面向該第一模塑料；以及在該第四表面上和露出的該等導電柱結構之間形成複數個第二導電結構，使得該等第二導電結構電性耦接在該等導 電柱結構與該第二重分佈層結構之間。
  22. 如申請專利範圍第21項所述的方法，其中，進一步包括：在該第三表面上形成一個或複數個堆疊的第二半導體晶粒；以及在該第三表面上形成一第二模塑料，使得該第二模塑料圍繞該一個或複數個堆疊的第二半導體晶粒。
  23. 如申請專利範圍第22項所述的方法，其中，該一個或複數個堆疊的第二半導體晶粒均為記憶體裝置。
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