TWI597815B - 半導體封裝結構 - Google Patents

半導體封裝結構 Download PDF

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Publication number
TWI597815B
TWI597815B TW104127286A TW104127286A TWI597815B TW I597815 B TWI597815 B TW I597815B TW 104127286 A TW104127286 A TW 104127286A TW 104127286 A TW104127286 A TW 104127286A TW I597815 B TWI597815 B TW I597815B
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Taiwan
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package
semiconductor package
dram
chip
germanium wafer
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TW104127286A
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TW201611233A (zh
Inventor
林子閎
楊明宗
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聯發科技股份有限公司
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Publication of TW201611233A publication Critical patent/TW201611233A/zh
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Description

半導體封裝結構
本發明涉及半導體技術領域，尤其涉及一種半導體封裝結構，例如混合的DRAM(Dynamic Random Access Memory，動態隨機存取記憶體)封裝結構。
POP(Package-on-Package，疊層封裝)結構是一種用於垂直組合分開的SOC(System-On-Chip，片上系統)和記憶體封裝的積體電路封裝方法。使用標準介面(standard interface)來安裝(如堆疊)兩個或更多的封裝於彼此之頂上，從而在該兩個或更多的封裝之間路由訊號。POP封裝結構允許設備具有更高的元件密度，該設備例如為行動電話、個人數位助理(Personal Digital Assistant，PDA)和數碼相機。
對於具有增強集成水準和改進了性能、頻寬、延遲、功率、重量和形狀因子(form factor)之記憶體應用，訊號墊與接地墊之比率在改善耦合效應中變得重要。
如此，期望創新的半導體封裝結構。
因此，本發明之主要目的即在於提供一種具有更好性能之半導體封裝結構。
根據本發明至少一個實施例提供了一種半導體封 裝結構，包括：一第一半導體封裝以及堆疊於該第一半導體封裝上之一第二半導體封裝；該第一半導體封裝，包括：一第一半導體祼晶片，該第一半導體祼晶片上具有一第一連接墊；一第一通孔，設置於該第一半導體祼晶片之上，並且耦接至該第一連接墊；以及一第一動態隨機存取記憶體祼晶片，安裝於該第一半導體祼晶片之上，並且耦接至該第一通孔；該第二半導體封裝，包括：一主體，具有一祼晶片接觸面以及位於該祼晶片接觸面對面之一凸塊接觸面；以及一第二動態隨機存取記憶體祼晶片，安裝於該祼晶片接觸面之上，並且由一接合線耦接至該主體；其中，該第一動態隨機存取記憶體祼晶片的輸入/輸出引腳的數量不同於該第二動態隨機存取記憶體祼晶片的輸入/輸出引腳的數量。
根據本發明至少一個實施例提供了一種半導體封裝結構，包括：一第一半導體封裝和堆疊於該第一半導體封裝上的一第二半導體封裝；該第一半導體封裝，包括：一半導體祼晶片，該半導體祼晶片之上具有一連接墊；以及一第一通孔，設置在該半導體祼晶片之上，並且耦接至該連接墊；該第二半導體封裝，包括：一主體，具有一祼晶片接觸面和位於該祼晶片接觸面對面的一凸塊接觸面；以及一第一動態隨機存取記憶體祼晶片，安裝於該凸塊接觸面之上，並且耦接至該主體；以及一第二動態隨機存取記憶體祼晶片，安裝於該祼晶片接觸面之上，並且由一接合線耦接至該主體；其中，該第一動態隨機存取記憶體祼晶片的輸入/輸出引腳的數量不同於該第二動態隨機存取記憶體祼晶片的輸入/輸出引腳的數量。
根據本發明至少一個實施例提供了一種半導體封裝結構，包括：一片上系統封裝和堆疊於該片上系統封裝上的一動態隨機存取記憶體封裝；該片上系統封裝包括：一邏輯祼晶片，該邏輯祼晶片上具有一第一連接墊；一第一重分佈層結構，耦接至該邏輯祼晶片；以及一模塑料，圍繞該邏輯祼晶片，並且與該第一重分佈層結構和該邏輯祼晶片接觸；該動態隨機存取記憶體封裝包括：一主體，具有一祼晶片接觸面和在該祼晶片接觸面對面的一凸塊接觸面；以及一動態隨機存取記憶體祼晶片，安裝於該祼晶片接觸面之上，並且由接合線耦接至該主體；其中，該片上系統封裝和該動態隨機存取記憶體封裝之一進一步包括：嵌於其中的一額外的動態隨機存取記憶體祼晶片；其中，該額外的動態隨機存取記憶體祼晶片具有一矽通孔內連結構，該矽通孔內連結構穿過該額外的動態隨機存取記憶體祼晶片。
本發明實施例，由於提供了使用POP半導體封裝結構集成的第一動態隨機存取記憶體祼晶片和第二動態隨機存取記憶體祼晶片，因此同時具有第一動態隨機存取記憶體封裝和第二動態隨機存取記憶體封裝的優點，例如低成本、高頻寬、低功耗和快速轉變等。
500a、500b‧‧‧半導體封裝結構
300a‧‧‧混合的SOC封裝
300b‧‧‧SOC封裝
400b‧‧‧混合的DRAM封裝
400a‧‧‧DRAM封裝
200‧‧‧基底
202、420‧‧‧祼晶片接觸面
322、432、452‧‧‧導電結構
302‧‧‧SOC祼晶片
600‧‧‧DRAM祼晶片
316、440‧‧‧RDL結構
308、310、314、444‧‧‧通孔
302a‧‧‧後表面
302b‧‧‧前表面
324‧‧‧頂部表面
304、306‧‧‧連接墊
602、602a、602b‧‧‧TSV內連結構
312、412、442‧‧‧模塑料
317、446‧‧‧IMD層
318、448‧‧‧導電跡線
320、450‧‧‧RDL接觸墊
321‧‧‧阻焊層
418‧‧‧主體
402、404、406‧‧‧LPDDR DRAM祼晶片
422‧‧‧凸塊接觸面
414、416‧‧‧接合線
424、426、430‧‧‧金屬墊
408、410‧‧‧連接墊
428‧‧‧電路
600a、600b‧‧‧寬I/O DRAM祼晶片
第1圖是根據本發明一實施例的半導體封裝結構的剖面示意圖，該半導體封裝結構包括：混合的SOC封裝和堆疊在該混合的SOC封裝之上的DRAM封裝。
第2圖是根據本發明另一實施例的半導體封裝結構的剖面示意圖，該半導體封裝結構包括：SOC封裝和堆疊在該SOC封裝之上的混合的DRAM封裝。
在說明書及後續的申請專利範圍當中使用了某些詞彙來指稱特定的元件。所屬領域中具有習知技術者應可理解，電子裝置製造商可能會用不同的名詞來稱呼同一個元件。本說明書及後續的申請專利範圍並不以名稱的差異來作為區分元件的方式，而是以元件在功能上的差異來作為區分的準則。在通篇說明書及後續的請求項當中所提及的「包含」係為一開放式的用語，故應解釋成「包含但不限定於」。以外，「耦接」一詞在此係包含任何直接及間接的電氣連接手段。因此，若文中描述一第一裝置耦接到一第二裝置，則代表該第一裝置可直接電氣連接於該第二裝置，或透過其他裝置或連接手段間接地電氣連接至該第二裝置。
本發明將參考特定的實施例以及相關圖式進行描述，但是本發明並不限制於該特定的實施例以及相關圖式，並且本發明僅由申請專利範圍進行限制。描述的圖式僅是原理圖並且不具有限制含義。在圖式中，出於說明目的而誇大了某些元件的尺寸，並且圖式並非是按比例繪製。圖式中的尺寸和相對尺寸並不對應本發明實踐中的真實尺寸。
第1圖是根據本發明一實施例的半導體封裝結構500a的剖面示意圖，該半導體封裝結構500a包括：一混合的SOC封裝300a和堆疊在該混合的SOC封裝300a上的一DRAM 封裝400a。在一些實施例中，半導體封裝結構500a可以是POP半導體封裝結構。半導體封裝結構500a包括：安裝於一基底200上的至少兩個垂直堆疊的晶圓級(wafer-level)半導體封裝。在本實施例中，該垂直堆疊的晶圓級半導體封裝包括：混合的SOC封裝300a和垂直堆疊於該混合的SOC封裝300a之上的DRAM封裝400a。
如第1圖所示，基底200(例如印刷電路版(Printed Circuit Board，PCB))可以由PP(polypropylene，聚丙烯)形成。需要注意的是：基底200可以為單層或多層結構。複數個連接墊(pad)和/或導電跡線(conductive trace)(均未圖示)設置於基底200之祼晶片接觸面202之上。在一個實施例中，導電跡線可以包括：訊號跡線部分或接地跡線部分，用於SOC封裝300a和DRAM封裝400a的輸入/輸出(I/O)連接。另外，SOC封裝300a直接安裝於導電跡線之上。在一些其它實施例中，連接墊設置於祼晶片接觸面202之上，並且連接至導電跡線的不同端。SOC封裝300a直接安裝於連接墊上。
如第1圖所示，混合的SOC封裝300a通過接合工藝(bonding process)安裝於基底200的祼晶片接觸面202之上。混合的SOC封裝300a通過導電結構322安裝於基底200之上。混合的SOC封裝300a可以是包含SOC祼晶片302、DRAM祼晶片600和RDL(redistribution layer，重分佈層)結構316的三維(3D)半導體封裝。例如，SOC祼晶片302可以包括：邏輯祼晶片，該邏輯祼晶片包括如下至少一項：CPU(central processing unit，中央處理單元)、GPU(graphic processing unit，影像處理單元)和DRAM控制器。DRAM祼晶片600可以為寬I/O(Wide I/O)DRAM祼晶片，垂直地堆疊於SOC祼晶片302之上。在本實施例中，通過TSV(Through Silicon via，矽通孔)技術裝配混合的SOC封裝300a中的DRAM祼晶片600。混合的SOC封裝300a中的SOC祼晶片302和DRAM祼晶片600由通孔(諸如通孔308，310)互相連接和/或連接至RDL結構316。需要注意的是：SOC祼晶片302的數量和DRAM祼晶片600的數量並不限制於公開的實施例。
如第1圖所示，SOC祼晶片302具有後表面302a和前表面302b。通過倒裝晶片技術裝配SOC祼晶片302。SOC祼晶片302的後表面302a接近或者對齊於混合的SOC封裝300a的頂部表面324。SOC祼晶片302的連接墊304設置於前表面302b之上，以電性連接至SOC祼晶片302的電路(未示出)。在一些實施例中，連接墊304屬於SOC祼晶片302的互連結構(未示出)的最頂層金屬層。SOC祼晶片302的連接墊304與對應的通孔308接觸。
如第1圖所示，DRAM祼晶片600堆疊於SOC祼晶片302的前表面302b之上。DRAM祼晶片600通過設置於SOC祼晶片302之上的通孔308耦接至SOC祼晶片302的連接墊304。DRAM祼晶片600可以包括：穿過DRAM祼晶片600而形成的TSV內連結構602。排列為陣列的TSV內連結構602可用於從DRAM祼晶片600向SOC祼晶片302和/或基底200傳送I/O訊號、接地訊號或功率訊號。TSV內連結構602可以設計為符合引腳佈置規則，例如JEDEC(Joint Electron Device Engineering Council，固態技術協會)的寬I/O記憶體規範。需要注意的是，陣列中的TSV內連結構的數量由DRAM祼晶片600和安裝於其上的SOC祼晶片302的設計而確定，並且不限制於公開的範圍。通孔308耦接至TSV內連結構602。
如第1圖所示，混合的SOC封裝300a進一步包括：模塑料(molding compound)312，圍繞在SOC祼晶片302和DRAM祼晶片600的周圍並且填充SOC祼晶片302和DRAM祼晶片600周圍的任何間隙。模塑料312與SOC祼晶片302和DRAM祼晶片600接觸。模塑料312也覆蓋SOC祼晶片302的前表面302b。在一些實施例中，模塑料312可以由非導電材料形成，例如環氧樹脂、樹指、可塑聚合物(moldable polymer)，等等。在模塑料312基本上為液體時使用，然後通過化學反應固化，例如在環氧樹脂或者樹脂中。在一些其它實施例中，模塑料312可以是紫外的(ultraviolet，UV)或者熱固化的聚合物，該聚合物作為能夠設置在SOC祼晶片302和DRAM祼晶片600附近的凝膠或者可塑固體，然後通過UV工藝或者熱固化工藝使該聚合物固化。模塑料312以模型固化。
如第1圖所示，混合的SOC封裝300a進一步包括：RDL結構316，設置於DRAM祼晶片600和SOC祼晶片302之上，以便於DRAM祼晶片600位於SOC祼晶片302和RDL結構316之間。RDL結構316可以與模塑料312和DRAM祼晶片600的TSV內連結構602接觸。在一些實施例中，RDL結構316可以具有一個或複數個設置於一個或複數個IMD(intermetal dielectric，內部金屬介電)層317中的導電跡線 318。導電跡線318是電性連接至對應的RDL接觸墊320。RDL接觸墊320暴露於阻焊層321的開口處。但是，需要注意的是：第1圖所示的導電跡線318的數量、IMD層317的數量和RDL接觸墊320的數量僅是舉例，並不用於限制本發明。
如第1圖所示，混合的SOC封裝300a進一步包括：導電結構322，設置於RDL結構316的遠離DRAM祼晶片600和SOC祼晶片302的表面。導電結構322通過RDL接觸墊320耦接於導電跡線318。在一些實施例中，導電結構可以包括：導電凸塊結構(例如銅凸塊或焊料凸塊結構)、導電柱結構、導電線結構或者導電膠結構。
如第1圖所示，DRAM祼晶片600使用TSV內連結構602和通孔308來連接SOC祼晶片302的連接墊304和RDL結構316的導電跡線318。另外，通孔310穿過SOC祼晶片302和RDL結構316之間的模塑料312，SOC祼晶片302的連接墊306通過該通孔310耦接至RDL結構316的導電跡線318。通孔310圍繞DRAM祼晶片600。
如第1圖所示，設計導電跡線318自SOC祼晶片302的連接墊304和306以及DRAM祼晶片600的TSV內連結構602中的一個或複數個扇出(fan out)，以提供SOC祼晶片302、DRAM祼晶片600和RDL接觸墊320之間的電性連接。因此，RDL接觸墊320可以具有比SOC祼晶片302的連接墊304和306以及DRAM祼晶片600的TSV內連結構602更大的接合間距(bond pitch)，該具有更大接合間距的RDL接觸墊320適用於球柵陣列或者另外的封裝安裝系統。
如第1圖所示，DRAM封裝400a通過接合工藝堆疊在混合的SOC封裝300a之上。在一個實施例中，DRAM封裝400a是具有符合管腳佈置規則(如JEDEC LPDDR I/O記憶體規範)的LPDDR DRAM(low-power double data rate DRAM，低功耗雙倍速率DRAM)封裝。DRAM封裝400a包括：主體418和至少一個LPDDR DRAM祼晶片，例如堆疊於主體418之上的三個LPDDR DRAM祼晶片402、404和406。主體418具有祼晶片接觸面420和相對於祼晶片接觸面420的凸塊接觸面422。在一些實施例中，寬I/O DRAM祼晶片的I/O引腳數量設計為不同於每個LPDDR DRAM祼晶片402、404和406的I/O引腳數量。在一個實施例中，寬I/O DRAM祼晶片的I/O引腳數量大於每個LPDDR DRAM祼晶片402、404和406的I/O引腳數量的8倍。在本實施例中，如第1圖所示，有三個LPDDR DRAM祼晶片402、404和406安裝於主體418的祼晶片接觸面420之上。LPDDR DRAM祼晶片404通過粘貼(未示出)堆疊於LPDDR DRAM祼晶片402之上，以及LPDDR DRAM祼晶片406通過粘貼(paste)堆疊於LPDDR DRAM祼晶片404之上。LPDDR DRAM祼晶片402、404和406可以由接合線耦接至主體418，例如接合線414和416，接合線414的兩端分別連接金屬墊424和LPDDR DRAM祼晶片402的連接墊408，接合線416的兩端分別連接金屬墊426和LPDDR DRAM祼晶片406的連接墊410。但是，堆疊的DRAM設備的數量不限制於公開的實施例。可選地，第1圖所示的三個LPDDR DRAM祼晶片402、404和406可以一個挨一個地(side by side)的佈置。如此，LPDDR DRAM祼晶片402、404和406可以通過粘貼而安裝於主體418的祼晶片接觸面420上。主體418可以包括：電路428和金屬墊424、426和430。金屬墊424和426設置於電路428接近於祼晶片接觸面420的頂部之上。金屬墊430設置在電路428接近於凸塊接觸面422的底部之上。複數個導電結構432設置於主體418的凸塊接觸面422之上，DRAM封裝400a的電路428與RDL結構316的導電跡線318通過該複數個導電結構432內部連接。在一些實施例中，導電結構432可以包括：導電凸塊結構(如銅凸塊或者焊料凸塊結構)、導電柱結構、導電線結構或者導電膠結構。在一些實施例中，通孔314穿過混合的SOC封裝300a中的DRAM封裝400a和RDL結構316之間的模塑料312，DRAM封裝400a通過該通孔314耦接至RDL結構316的導電跡線318。通孔314圍繞SOC祼晶片302和DRAM祼晶片600。
在一個實施例中，如第1圖所示，DRAM封裝400a進一步包括：模塑料412，覆蓋主體418的祼晶片接觸面420，並且包封(encapsulating)LPDDR DRAM祼晶片402、404和406和接合線414和416。
第2圖是根據本發明另一實施例的半導體封裝結構500b的剖面示意圖，該半導體封裝結構500b包括：SOC封裝300b以及堆疊在該SOC封裝300b之上的混合的DRAM封裝400b。出於簡潔，不再重複下文實施例中相同或者類似於參考第1圖所描述的先前實施例中的元件。半導體封裝結構500a和半導體封裝結構500b之間的不同在於：半導體封裝結構 500b包括：純的SOC封裝300b和垂直地堆疊于該SOC封裝300b上的混合的DRAM封裝400b。
如第2圖所示，SOC封裝300b為包含SOC祼晶片302和RDL結構316的半導體封裝。該SOC封裝300b不包括任何集成於其中的DRAM祼晶片。SOC封裝300b中的SOC祼晶片302由通孔(如通孔310)連接至RDL結構316。SOC祼晶片302的連接墊304與對應的通孔310接觸。需要注意的是，SOC祼晶片302的數量不限制於公開的實施例。
如第2圖所示，混合的DRAM封裝400b通過接合工藝堆疊在SOC封裝300b之上。混合的DRAM封裝400b為三維半導體封裝，該三維半導體封裝包括：堆疊在TSV DRAM封裝之上的線接合DRAM封裝。在本實施例中，混合的DRAM封裝400b為LPDDR DRAM/寬I/O DRAM混合封裝，該LPDDR DRAM/寬I/O DRAM混合封裝包括：LPDDR DRAM祼晶片，符合特定引腳佈置規則(如JEDEC LPDDR I/O記憶體規範)；以及寬I/O DRAM祼晶片，符合其它特定的引腳佈置規則(如JEDEC寬I/O記憶體規範)。混合的DRAM封裝400b包括：主體418、堆疊於主體418之上的至少一個LPDDR DRAM祼晶片和堆疊於主體418之上的至少一個寬I/O DRAM祼晶片。在如第2圖所示的一些實施例中，存在三個LPDDR DRAM祼晶片402、404和406安裝於主體418的祼晶片接觸面420之上。LPDDR DRAM祼晶片404通過粘貼堆疊於LPDDR DRAM祼晶片402之上，以及LPDDR DRAM祼晶片406通過粘貼(未示出)堆疊在LPDDR DRAM祼晶片404之上。LPDDR DRAM 祼晶片402、404和406由接合線耦接至主體418，例如接合線414和416。但是，堆疊的LPDDR DRAM祼晶片的數量不限制於公開的實施例。可選地，第2圖所示的三個LPDDR DRAM祼晶片402、404和406可以一個挨一個地設置。如此，LPDDR DRAM祼晶片402、404和406可以通過粘貼安裝於主體418的祼晶片接觸面420上。
在一個實施例中，如第2圖所示，主體418可以包括：電路(未示出)和金屬墊424、426和430。金屬墊424和426設置於電路428的頂部，該頂部靠近祼晶片接觸面420。金屬墊430設置在電路中的底部，該底部靠近凸塊接觸面430。接合線414的兩端分別連接金屬墊424和LPDDR DRAM祼晶片402的連接墊408，接合線416的兩端分別連接金屬墊426和LPDDR DRAM祼晶片406的連接墊410。
在一個實施例中，如第2圖所示，混合的DRAM封裝400b進一步包括：模塑料412，該模塑料412覆蓋主體418的祼晶片接觸面420，並且包封LPDDR DRAM祼晶片402、404和406和接合線414和416。
如第2圖所示，混合的DRAM封裝400b進一步包括：至少一個寬I/O DRAM祼晶片，例如兩個嵌入於其中的寬I/O DRAM祼晶片600a和600b。在這個實施例中，兩個寬I/O DRAM祼晶片600a和600b安裝在凸塊接觸面422之上並且耦接至主體418的金屬墊430。寬I/O DRAM祼晶片600a和600b一個挨一個地佈置。但是，寬I/O DRAM祼晶片的數量和佈置方式不限制於公開的實施例。寬I/O DRAM祼晶片600a和600b 可以包括：對應的分別穿過寬I/O DRAM祼晶片600a和600b而形成的TSV內連結構602a和602b。佈置為陣列的TSV內連結構602a和602b可用於從寬I/O DRAM祼晶片600a和600b向LPDDR DRAM祼晶片402、404和406和/或基底200傳送I/O訊號、接地訊號或者功率訊號。TSV內連結構602a和602b可以設計為符合引腳佈置規則(如JEDEC寬I/O記憶體規範)。需要注意的是：陣列中的TSV內連結構的數量由用於寬I/O DRAM祼晶片600a和600b以及安裝於其上的LPDDR DRAM祼晶片402、404和406的設計而定，並且不限制公開的範圍。TSV內連結構602a和602b耦接至主體418的金屬墊430。在一些實施例中，寬I/O DRAM祼晶片600a和600b的I/O引腳數量設計為不同于任一LPDDR DRAM祼晶片402、404和406的I/O引腳數量。在一個實施例中，寬I/O DRAM祼晶片600a和600b的I/O引腳數量大於任一LPDDR DRAM祼晶片402、404和406的I/O引腳數量的8倍。
如第2圖所示，混合的DRAM封裝400b進一步包括：模塑料442，設置於主體418的凸塊接觸面422之上。該模塑料442圍繞寬I/O DRAM祼晶片600a和600b，並且填充寬I/O DRAM祼晶片600a和600b周圍的任何空隙。模塑料442與寬I/O DRAM祼晶片600a和600b接觸。
如第2圖所示，混合的DRAM封裝400b進一步包括：RDL結構440，位於主體418的凸塊接觸面422之上。RDL結構440也設置在LPDDR DRAM祼晶片402、404和406和寬I/O DRAM祼晶片600a和600b之上。寬I/O DRAM祼晶片600a 和600b位於主體418和RDL結構440之間。RDL結構440可以與模塑料442和寬I/O DRAM祼晶片600a和600b的TSV內連結構602a和602b接觸。RDL結構440可以具有一個或複數個導電跡線448，該一個或複數個導電跡線448設置於一個或複數個IMD層446中。導電跡線448電性連接至對應的RDL接觸墊450。但是，需要注意的是：第2圖所示的導電跡線448的數量，IMD層446的數量和RDL接觸墊450的數量僅是示例而不是本發明的限制。
如第2圖所示，通孔444穿過主體418的凸塊接觸面422和RDL結構440之間的模塑料442，LPDDR DRAM祼晶片402、404和406可以通過該通孔444耦接至RDL結構440的RDL接觸墊450。通孔444圍繞該寬I/O DRAM祼晶片600a和600b。
如第2圖所示，複數個導電結構452設置於RDL結構440的RDL接觸墊450之上，DRAM封裝400b的導電跡線448通過該複數個導電結構452與SOC封裝300b的RDL結構316的導電跡線318內連。在一些實施例中，導電結構452可以包括：導電凸塊結構(如銅凸塊或者焊料凸塊結構)、導電柱結構、導電線結構或者導電膠結構。在一些實施例中，通孔314穿過DRAM封裝400b和SOC封裝300b的RDL結構316之間的模塑料，DRAM封裝400b的導電結構452由該通孔314耦接至SOC封裝300b的RDL結構316。通孔314圍繞SOC祼晶片302。
實施例提供了半導體封裝結構500a和500b。半導 體封裝結構500a和500b中的任一提供了使用POP半導體封裝結構集成的LPDDR DRAM和寬I/O DRAM混合記憶體。POP半導體封裝結構500a包括：SOC(或寬I/O)DRAM混合封裝300a和堆疊於其上的LPDDR DRAM封裝400a。POP半導體封裝結構500b包括：純的SOC封裝300b和堆疊於其上的LPDDR/寬I/O DRAM混合封裝400b。半導體封裝結構500a和500b具有LPDDR DRAM封裝結構的優點(諸如成本效應、快速轉變，等等)以及寬I/O DRAM封裝結構的優點(諸如高頻寬，低功耗，等等)。半導體封裝結構500a和500b可以滿足成本效應、高頻寬、低功耗和快速轉變的需求。
以上所述僅為本發明的較佳實施例而已，並不用以限制本發明，凡在本發明的精神和原則之內所作的任何修改、等同替換和改進等，均應包含在本發明的保護範圍之內。
500a‧‧‧半導體封裝結構
300a‧‧‧混合的SOC封裝
400a‧‧‧DRAM封裝
200‧‧‧基底
202、420‧‧‧祼晶片接觸面
322、432‧‧‧導電結構
302‧‧‧SOC祼晶片
600‧‧‧DRAM祼晶片
316‧‧‧RDL結構
308、310、314‧‧‧通孔
302a‧‧‧後表面
302b‧‧‧前表面
324‧‧‧頂部表面
304、306‧‧‧連接墊
602‧‧‧TSV內連結構
312、412‧‧‧模塑料
317‧‧‧IMD層
318‧‧‧導電跡線
320‧‧‧RDL接觸墊
321‧‧‧阻焊層
418‧‧‧主體
402、404、406‧‧‧LPDDR DRAM祼晶片
422‧‧‧凸塊接觸面
414、416‧‧‧接合線
424、426、430‧‧‧金屬墊
408、410‧‧‧連接墊
428‧‧‧電路

Claims (22)

  1. 一種半導體封裝結構，包括：一第一半導體封裝和堆疊於該第一半導體封裝上的一第二半導體封裝；該第一半導體封裝，包括：一半導體祼晶片，該半導體祼晶片之上具有一連接墊；以及一第一通孔，設置在該半導體祼晶片之上，並且耦接至該連接墊；該第二半導體封裝，包括：一主體，具有一祼晶片接觸面和位於該祼晶片接觸面對面的一凸塊接觸面；以及一第一動態隨機存取記憶體祼晶片，安裝於該凸塊接觸面之上，並且耦接至該主體；以及一第二動態隨機存取記憶體祼晶片，安裝於該祼晶片接觸面之上，並且由一接合線耦接至該主體；其中，該第一動態隨機存取記憶體祼晶片的輸入/輸出引腳的數量不同於該第二動態隨機存取記憶體祼晶片的輸入/輸出引腳的數量；其中，該第二半導體封裝進一步包括：一第二模塑料，設置在該主體的一凸塊接觸面之上；以及一第二重分佈層結構，位於該第二模塑料之上；其中，該第一動態隨機存取記憶體祼晶片位於該主體和該第二重分佈層結構之間。
  2. 如申請專利範圍第1項所述之半導體封裝結構，其中，該 第一動態隨機存取記憶體祼晶片的輸入/輸出引腳的數量大於該第二動態隨機存取記憶體祼晶片的輸入/輸出引腳的數量的8倍。
  3. 如申請專利範圍第1項所述之半導體封裝結構，其中，該第一動態隨機存取記憶體祼晶片具有一矽通孔內連結構，該矽通孔內連結構穿過該第一動態隨機存取記憶體祼晶片。
  4. 如申請專利範圍第1項所述之半導體封裝結構，其中，該第一半導體封裝進一步包括：一第一重分佈層結構，該第一重分佈層結構上具有一第一導電跡線；其中，該半導體祼晶片耦接於該第一導電跡線。
  5. 如申請專利範圍第4項所述之半導體封裝結構，其中，該第一半導體封裝進一步包括：一第一模塑料，圍繞該半導體祼晶片，並且與該第一重分佈層結構和該半導體祼晶片接觸；以及一第一導電結構，設置在該第一重分佈層結構中遠離該半導體祼晶片的表面上，其中該第一導電結構耦接至該第一導電跡線。
  6. 如申請專利範圍第1項所述之半導體封裝結構，其中，該第二模塑料圍繞該第一動態隨機存取記憶體祼晶片，該第二重分佈層結構上具有一第二導電跡線，該第一動態隨機存取記憶體祼晶片耦接至該第二導電跡線。
  7. 如申請專利範圍第6項所述之半導體封裝結構，其中，該第二半導體封裝通過一第二通孔耦接至該第一導電跡線， 該第二通孔穿過位於該第二半導體封裝和該第一重分佈層結構之間的該第一模塑料。
  8. 如申請專利範圍第7項所述之半導體封裝結構，其中，該第二通孔圍繞該半導體祼晶片。
  9. 如申請專利範圍第6項所述之半導體封裝結構，其中，該第二動態隨機存取記憶體祼晶片通過一第三通孔耦接至該第二重分佈層結構，該第三通孔穿過位於該主體和該第二重分佈層結構之間的該第二模塑料。
  10. 如申請專利範圍第9項所述之半導體封裝結構，其中，該第三通孔圍繞該第一動態隨機存取記憶體祼晶片。
  11. 如申請專利範圍第6項所述之半導體封裝結構，其中，該第二半導體封裝通過一第二導電結構安裝於該第一半導體封裝之上，該第二導電結構位於該第二重分佈層結構之上並且耦接該第二重分佈層結構。
  12. 如申請專利範圍第1項所述之半導體封裝，其中，進一步包括：一基底，該第一和第二半導體封裝通過一第一導電結構安裝於該基底之上。
  13. 一種半導體封裝結構，包括：一片上系統封裝和堆疊於該片上系統封裝上的一動態隨機存取記憶體封裝；該片上系統封裝包括：一邏輯祼晶片，該邏輯祼晶片上具有一第一連接墊；一第一重分佈層結構，耦接至該邏輯祼晶片；以及一模塑料，圍繞該邏輯祼晶片，並且與該第一重分佈層結構和該邏輯祼晶片接觸； 該動態隨機存取記憶體封裝包括：一主體，具有一祼晶片接觸面和在該祼晶片接觸面對面的一凸塊接觸面；以及一動態隨機存取記憶體祼晶片，安裝於該祼晶片接觸面之上，並且由一接合線耦接至該主體；其中，該片上系統封裝和該動態隨機存取記憶體封裝之一進一步包括：嵌於其中的一額外的動態隨機存取記憶體祼晶片；其中，該額外的動態隨機存取記憶體祼晶片具有一矽通孔內連結構，該矽通孔內連結構穿過該額外的動態隨機存取記憶體祼晶片；其中，該片上系統封裝進一步包括：一第一通孔，位於該邏輯祼晶片之上，並且耦接至該第一連接墊；其中，該額外的動態隨機存取記憶體祼晶片嵌入於該片上系統封裝中，並且耦接該第一通孔和該第一重分佈層結構。
  14. 如申請專利範圍第13項所述之半導體封裝結構，其中，該動態隨機存取記憶體祼晶片的輸入/輸出引腳的數量不同於該額外的動態隨機存取記憶體祼晶片的輸入/輸出引腳的數量；或者，該額外的動態隨機存取記憶體祼晶片的輸入/輸出引腳數量大於該動態隨機存取記憶體祼晶片的輸入/輸出引腳的數量的8倍。
  15. 如申請專利範圍第13項所述之半導體封裝結構，其中，該 動態隨機存取記憶體祼晶片封裝通過一第二通孔耦接至該片上系統封裝中的該第一重分佈層結構；該第二通孔穿過位於該動態隨機存取記憶體封裝和該第一重分佈層結構之間的該模塑料。
  16. 如申請專利範圍第15項所述之半導體封裝結構，其中，該第二通孔圍繞該邏輯祼晶片。
  17. 如申請專利範圍第13項所述之半導體封裝結構，其中，該模塑料與該額外的動態隨機存取記憶體祼晶片接觸。
  18. 如申請專利範圍第13項所述之半導體封裝結構，其中，該邏輯祼晶片通過第三通孔耦接至該第一重分佈層結構，該第三通孔穿過該邏輯祼晶片和該第一重分佈層結構之間的該模塑料。
  19. 如申請專利範圍第18項所述之半導體封裝結構，其中，該第三通孔圍繞該第一動態隨機存取記憶體祼晶片。
  20. 如申請專利範圍第13項所述之半導體封裝結構，其中，該動態隨機存取記憶體封裝還包括：一第二重分佈層結構，位於該凸塊接觸面之上。
  21. 如申請專利範圍第13項所述之半導體封裝結構，其中，進一步包括：一基底，該第一和第二半導體封裝通過一導電結構安裝在該基底之上。
  22. 一種半導體封裝結構，包括：一片上系統封裝和堆疊於該片上系統封裝上的一動態隨機存取記憶體封裝；該片上系統封裝包括：一邏輯祼晶片，該邏輯祼晶片上具有一第一連接墊； 一第一重分佈層結構，耦接至該邏輯祼晶片；以及一模塑料，圍繞該邏輯祼晶片，並且與該第一重分佈層結構和該邏輯祼晶片接觸；該動態隨機存取記憶體封裝包括：一主體，具有一祼晶片接觸面和在該祼晶片接觸面對面的一凸塊接觸面；以及一動態隨機存取記憶體祼晶片，安裝於該祼晶片接觸面之上，並且由一接合線耦接至該主體；其中，該片上系統封裝和該動態隨機存取記憶體封裝之一進一步包括：嵌於其中的一額外的動態隨機存取記憶體祼晶片；其中，該額外的動態隨機存取記憶體祼晶片具有一矽通孔內連結構，該矽通孔內連結構穿過該額外的動態隨機存取記憶體祼晶片；該動態隨機存取記憶體封裝還包括：一第二重分佈層結構，位於該凸塊接觸面之上其中，該額外的動態隨機存取記憶體祼晶片設置在該主體和該第二重分佈層之間。
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US9548289B2 (en) 2017-01-17
TW201611233A (zh) 2016-03-16
US10361173B2 (en) 2019-07-23
US20170084583A1 (en) 2017-03-23
CN105428334B (zh) 2019-03-01
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US20160079220A1 (en) 2016-03-17
CN105428334A (zh) 2016-03-23

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