CN112151525A - 半导体裸芯及半导体封装体 - Google Patents
半导体裸芯及半导体封装体 Download PDFInfo
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- CN112151525A CN112151525A CN201910575624.9A CN201910575624A CN112151525A CN 112151525 A CN112151525 A CN 112151525A CN 201910575624 A CN201910575624 A CN 201910575624A CN 112151525 A CN112151525 A CN 112151525A
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- Semiconductor Memories (AREA)
Abstract
公开了一种半导体裸芯。该半导体裸芯包括:基层;至少一个互补金属氧化物半导体电路,布置在基层的第一侧上,并且配置为与至少一个存储器裸芯通信,其中,至少一个存储器裸芯独立于半导体裸芯;控制器电路,布置在基层的第一侧上,并且配置为控制至少一个互补金属氧化物半导体电路和至少一个存储器裸芯;输出端子,布置在至少一个互补金属氧化物半导体电路和控制器电路之上,并与至少一个互补金属氧化物半导体电路和控制器电路电互连;以及导电连接件,布置在输出端子的每一个之上。还公开了一种半导体封装体。
Description
技术领域
本技术总体上涉及一种半导体裸芯及半导体封装体。具体而言,本技术涉及一种CMOS电路和控制器电路集成的半导体裸芯及包含该半导体裸芯的半导体封装体。
背景技术
便携式消费电子器件需求的强劲增长推动了对高容量存储设备的需求。非易失性半导体存储装置,诸如闪存存储卡,已广泛用于满足对数字信息存储和交换的日益增长的需求。它们的便携性、多功能性和坚固耐用的设计以及它们的高可靠性和大容量,使得此类存储装置理想地用于多种电子设备中,包括例如数字相机、数字音乐播放器、视频游戏控制台、PDA和蜂窝电话。
随着需要越来越小电子器件,半导体封装体可以设计为将裸芯经由电子接口连接到外置系统以使得更加紧凑电子器件成为可能并且支撑更大的电路密度。
发明内容
根据一个方面,提供一种半导体裸芯,半导体裸芯包括:至少一个互补金属氧化物半导体(CMOS)电路模块,电耦接到至少一个存储器裸芯,至少一个存储器裸芯独立于半导体裸芯;以及控制器模块,电耦接到互补金属氧化物半导体电路模块,并且配置为控制至少一个互补金属氧化物半导体电路模块和至少一个存储器裸芯。
根据另一个方面,提供一种半导体裸芯,半导体裸芯包括:基层;至少一个互补金属氧化物半导体电路,布置在基层的第一侧上,并且配置为与至少一个存储器裸芯通信,其中,至少一个存储器裸芯独立于半导体裸芯;控制器电路,布置在基层的第一侧上,并且配置为控制至少一个互补金属氧化物半导体电路和至少一个存储器裸芯;输出端子,布置在至少一个互补金属氧化物半导体电路和控制器电路之上,并与至少一个互补金属氧化物半导体电路和控制器电路电互连;以及导电连接件,布置在输出端子的每一个之上。
根据实施例,至少一个互补金属氧化物半导体电路包括地址和/或命令控制电路,并且配置为与至少一个存储器裸芯通信以传输地址和/或命令的信号。
根据实施例,互补金属氧化物半导体电路模块逻辑控制阵列电路模块和/或模拟电路模块。
根据实施例,控制器电路配置为专用集成电路。
根据实施例,控制器电路和至少一个互补金属氧化物半导体电路布置在同一层。
根据实施例,控制器电路和至少一个互补金属氧化物半导体电路上下交叠布置。
根据实施例,导电连接件包括微凸块。
根据实施例,微凸块的材料包括铜、金、镍、锡、铅、银、铂、和/或铝。
根据另一个方面,提供一种半导体封装体,半导体封装体包括:转接器,具有第一表面和与第一表面相对的第二表面;半导体裸芯,布置在转接器的第一表面上;以及至少一个存储器裸芯,布置在转接器的第一表面之上且在半导体裸芯上或布置在转接器的第二表面上;其中,半导体裸芯,包括:基层;至少一个互补金属氧化物半导体电路,布置在基层的第一侧上,并且配置为与至少一个存储器裸芯通信,其中,至少一个存储器裸芯独立于半导体裸芯;控制器电路,布置在基层的第一侧上,并且配置为控制至少一个互补金属氧化物半导体电路和至少一个存储器裸芯;输出端子,布置在至少一个互补金属氧化物半导体电路和控制器电路之上,并与它们电互连;以及导电连接件,布置在输出端子中的每一个之上。
根据实施例,半导体封装体不包括衬底。
根据实施例,至少一个存储器裸芯包括上下堆叠的存储器裸芯。
根据实施例,转接器具有用金属填充的多个穿硅通孔。
根据实施例,封装体还包括分别形成于转接器的第一表面和第二表面上的重新分布层,其与半导体裸芯的导电连接件和至少一个存储器裸芯分别电互连。
根据实施例,半导体封装体还包括底料填充层,底料填充层布置在重新分布层和半导体裸芯之间以覆盖全部导电连接件。
根据实施例,半导体封装体还包括包封在所述转接器上的至少一个存储器裸芯和/或半导体裸芯的模塑料。
根据另一个方面,提供一种制造半导体封装体的方法,其包括以下步骤:a)提供转接器,转接器具有第一表面和与第一表面相对的第二表面;b)提供半导体裸芯;c)将半导体裸芯布置在转接器的第一表面上;d)提供至少一个存储器裸芯,其中,至少一个存储器裸芯独立于半导体裸芯;以及e)将至少一个存储器裸芯布置在半导体裸芯上或者在转接器的第二表面上。
提供半导体裸芯的步骤包括:提供基层;在基层的第一侧上形成至少一个互补金属氧化物半导体电路;在基层的第一侧上形成控制器电路,控制器电路配置为控制至少一个互补金属氧化物半导体电路和至少一个存储器裸芯;在至少一个互补金属氧化物半导体电路和控制器电路之上形成输出端子,并且该输出端子与至少一个互补金属氧化物半导体电路和控制器电路电互连;以及在输出端子中的每一个之上形成导电连接件。
应当理解,可以组合本技术的各方面,使得在一个方面的内容中描述的特征可以在另一个方面来实现。
在本实施例中,将从存储器裸芯中分离出的包含逻辑控制阵列电路模块和/或模拟电路模块的CMOS电路模块与管理至少一个存储器裸芯的控制器模块集成在一个半导体裸芯中。因此,可以显著降低CMOS电路对每一个存储器裸芯的热性能和机械性能的影响。并且由于CMOS电路的数据处理速度和控制器的操作速度远大于存储器裸芯的操作速度,因此,将CMOS电路与控制器集成在一个半导体裸芯中,能够进行更加高效地数据管理操作。
由于每一个存储器裸芯不包含CMOS电路,可以因此进一步增加存储器裸芯的集成密度并降低存储器裸芯的制造成本。另外,集成的半导体裸芯避免了在封装体中使用衬底,进一步减小了封装体的尺寸。衬底通常可以包括电介质基部,其具有一侧或两侧上蚀刻的导电层。而且,由于在一个半导体裸芯中集成了CMOS电路和控制器,半导体裸芯的尺寸可以大于仅包括控制器的裸芯的尺寸,因此可以将该半导体裸芯直接置于存储器裸芯堆叠体下方而避免了使用附加的支撑结构,从而减小了工艺复杂程度。
要理解的是,本实施例的前面的一般性描述和下面的详细的描述二者都是示例性的,并且意图在于提供要求保护的技术的进一步说明。
附图说明
图1是存储器封装体的示意性侧视图;
图2是根据实施例的包含CMOS电路和控制器电路集成的半导体裸芯的系统的框图;
图3是根据实施例的CMOS电路和控制器电路集成的半导体裸芯的模块化框图;
图4A是CMOS电路和控制器电路集成的半导体裸芯的第一实施例的示意性侧视图;
图4B是CMOS电路和控制器电路集成的半导体裸芯的第一实施例的俯视图;
图4C是CMOS电路和控制器电路集成的半导体裸芯的第二实施例的示意性侧视图;
图5A是半导体封装体的第一实施例的示意性侧视图;
图5B是半导体封装体的第二实施例的示意性侧视图;
图6A是半导体封装体的第三实施例的示意性侧视图;
图6B是半导体封装体的第四实施例的示意性侧视图;
图7是图5A所示的半导体封装体的制造方法的流程图;
图8A-8H是示出了图7所示的制造方法的不同阶段的示意性侧视图;
图9是根据图6A所示的半导体封装体的制造方法的流程图;以及
图10A-10F是示出了图9所示的制造方法的不同阶段的示意性侧视图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚,下面将结合本发明实施例的附图,对本发明实施例的技术方案进行清楚、完整地描述。显然,所描述的实施例是本发明的一部分实施例,而不是全部的实施例。基于所描述的本发明的实施例,本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例,都属于本发明保护的范围。除非另外说明,相同的附图标记表示相同的特征,并且附图未按比例绘制。
除非另作定义,此处使用的技术术语或者科学术语应当为本领域普通技术人员所理解的通常意义。本发明专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语可以用于描述各种元件、组件、区域、层、步骤和/或区段,但并不表示任何顺序、数量或者重要性,只是用来区分一个元件、组件、区域、层、步骤和/或区段。同样,“一个”或者“一”等类似词语也不表示数量限制,而是表示存在至少一个。
空间上相关的术语,诸如“在…上”、“在…下”、“上部”、“下部”、“上方”、“下方”、“之上”、“之下”等,可以在本文中出于易于描述的目的来描述一个元件或特征与至少一个其他元件或特征的如图所示的关系。这些空间上相关的术语旨在于涵盖除了附图中所描绘的取向之外在使用或操作中的装置的不同取向。例如,如果装置翻转,则描述为在另一个元件或特征“下”、“下方”的某个元件或特征则将取向在另一个元件的上方。此外,还将理解的是,当元件或特征被描述为“在”两个元件或特征“之间”,可以认为该元件或特征是这两个元件或特征之间的唯一元件或特征,或者还存在至少一个中介的元件或特征。还将理解的是,当元件或特征被描述为“在…上”、“连接到”、“耦接到”、“附接到”另一个元件或特征时,它可以是直接地“在…上”、“连接到”、“耦接到”、“附接到”另一个元件或特征,或者还可以出现至少一个中介的元件或特征。与此相反,当元件或特征被描述为“直接在…上”、“直接地连接到”、“直接地耦接到”、“直接地附接到”另一个元件或特征时,则不存在中介的元件或特征。
在本发明的上下文中,术语“裸芯”、“芯片”、“晶片”等均是指在封装之前的半导体组件的形式,且可以互换使用。
如本领域技术人员将认识到的,可以按任意方式连接、布置、配置这些器件、装置、设备、系统。诸如“包括”、“包含”、“具有”等等的词语是开放性词汇,指“包括但不限于”,且可与其互换使用。这里所使用的术语“或”和“和”指术语“和/或”,且可与其互换使用,除非上下文明确指示不是如此。这里所使用的“诸如”指词组“诸如但不限于”,且可与其互换使用。
另外,在以“至少一个”开始的项的列举中使用的“或”指示分离的列举,以便例如“A、B或C中的至少一个”的列举意味着A或B或C,或者AB或AC或BC,或者ABC(即A和B和C)。此外,措辞“示例的”指示示意性的说明,并不意味着描述的例子是优选的或者比其他例子更好。
以下,将参考附图详细描述实施例。
图1是存储器封装体的示意性侧视图。
如图1所示,该存储器封装体100包括诸如印刷电路板(PCB)的衬底110和在衬底110上设置的存储器裸芯堆叠体。存储器裸芯堆叠体包括多个存储器裸芯120,每个存储器裸芯120包括存储器电路122和CMOS电路层124。该存储器封装体还包括控制器130,其布置在该衬底110上并且在存储器裸芯堆叠体的附近。在此,存储器裸芯通过衬底110电耦接到控制器130。
随着存储器电路122的3D集成密度的提升,在存储器裸芯120中存在的CMOS电路124不仅可能显著增加制造成本,而且还可能带来了热性能的显著变差。例如,因为CMOS电路的处理数据的速度比存储器裸芯的存取数据的速度快得多,导致了存储器裸芯中产生了更多的热量并增加了热循环,引起存储器裸芯堆叠体的热应力增加。
图2是根据实施例的包含CMOS电路和控制器电路的集成裸芯的系统的框图。
在上下文中,为了易于描述,CMOS电路和控制器电路的集成的半导体裸芯缩写为集成的裸芯,或简称裸芯。
如图2所示,该系统200包括主机装置210、集成的裸芯220、以及存储器230。集成的裸芯220通过总线240连接到主机装置210,并且通过字线阵列250和位线阵列260连接到存储器230。
主机装置210可以是包含处理器的任何类型的计算装置,例如智能电视、机顶盒、智能音响、智能手机、桌上型计算机、膝上型计算机、上网本计算机、平板计算机、车载计算机、诸如手表、戒指、手环等的可穿戴装置或任何其它类型的计算装置。包含CMOS电路和控制器集成的裸芯220(对应于图3的裸芯300)将在下文中详细地描述。存储器230可以是单个存储器裸芯,或者包括多个存储器裸芯的存储器裸芯堆叠体和/或存储器裸芯阵列,通常还称为存储单元阵列。在本技术的上下文中,存储器裸芯堆叠体或存储器单元阵列可以配置为由多个存储器串构成的NAND存储器,该多个存储器串由共享单个位线并且作为组访问的多个存储器单元构成。存储器单元可以是一组串行连接的存储器单元。替代地,存储器裸芯堆叠体还可以配置为NOR存储器,其中存储器单元可以配置为每个存储器单元是可访问的。NAND存储器和NOR存储器仅是示例性的,并且还可以配置成其他形式的存储器单元。
总线240可以包括串行高级技术附件(SATA)、高速外围组件互连(PCIe)、用闪存存储(UFS)、嵌入式多媒体卡(eMMC)、或通用串行总线(USB)等。
图3是根据实施例的CMOS电路和控制器集成的半导体裸芯的模块化框图。
参考图3,CMOS电路和控制器电路集成的半导体裸芯300包括控制器模块310和CMOS电路模块320。具体而言,控制器模块310电耦接到CMOS电路模块320,且配置为控制CMOS电路模块320和如图2所示的存储器230。
控制器模块310通过对CMOS电路模块320和存储器230的控制来管理存储器230。控制器模块310例如可以是专用集成电路(ASIC)。更具体地,控制器模块310包括错误检验和校正(ECC)模块、诸如动态随机存取存储器(DRAM)的易失性存储器模块、缓冲器模块、坏块管理模块(BBM)、磨损均衡模块中的至少一个。控制器模块310有助于管理存储器中的数据、坏块、坏道等,避免存储器故障或者性能下降,从而保障数据的安全。
CMOS电路模块320用于通过存储器控制器模块310输出的控制信号与存储器230通信,例如传输数据的地址和命令信号。CMOS电路模块320可以包括例如互补金属氧化物半导体逻辑控制阵列(CLA)的逻辑电路模块322和模拟电路模块324。具体而言,逻辑电路模块322也可以称为数字逻辑电路模块。特别地,逻辑电路模块322可以包括输入/输出逻辑电路、地址和/或命令控制逻辑电路、驱动器、CMOS解码器、复用器中的至少一个。地址和/或命令控制逻辑电路可以包括位线存取和位线地址控制逻辑电路、字线存取和字线地址控制逻辑电路。具体而言,逻辑电路模块可以是指地址和/或命令控制逻辑电路,以用于对外通信。并且模拟电路模块可以包括电源功率控制器、传感放大器、时钟发生器中的至少一个。值得注意的是,地址和/或命令控制逻辑电路的CMOS电路模块与字线和位线并行通讯,而且对于数据和信号具有比存储器230更快的操作速度,以便于将数据和信号快速地提供给存储器以进行存取等操作。
裸芯300还包括主机接口330和存储器接口340。控制器模块310通过主机接口330耦接到如图2所示的主机装置210。CMOS电路模块320通过存储器接口340电耦接到存储器230,控制器模块310通过存储器接口340电耦接到存储器230。如上所述,存储器230可以是包括多个存储器裸芯的存储单元阵列。
根据本公开,将包含逻辑模块和/或模拟电路模块的CMOS电路模块与管理至少一个存储器裸芯的控制器模块集成在独立于存储器芯片的单个半导体裸芯中。因此,可以显著降低CMOS电路对每一个存储器裸芯的热性能和机械性能的影响。并且由于CMOS电路的数据处理速度和控制器的操作速度远大于存储器裸芯的操作速度,因此,将CMOS电路与控制器电路集成在一个半导体裸芯中,能够进行更加高效的数据管理操作。
图4A和图4B是CMOS电路和控制器电路集成的半导体裸芯400的第一实施例的示意性侧视图和俯视图。如图4A所示,CMOS电路和控制器电路集成的半导体裸芯400包括基层410、包含CMOS电路和控制器电路的电路层420、输出端子430、以及导电连接件440。基层410可以包括硅,并且为CMOS电路和控制器电路的电路层420提供支撑。如图所示,CMOS电路和控制器电路层420布置在基层410之上且在同一层中。控制器例如可以包括专用集成电路(ASIC)。
输出端子430形成在电路层420之上,并与ASIC和CMOS电路电互连。具体地,输出端子430暴露于裸芯400的上表面。输出端子430可以包含填充金属的穿硅通孔和/或金属层,并且与ASIC和CMOS电路电互连。导电连接件440形成在裸芯400的上表面上所暴露的每一个输出端子430之上,例如为接合垫的形式。导电连接件440可以是微凸块、球珊阵列(BGA)焊球等。如图4B所示,在CMOS电路和控制器集成的半导体裸芯400中,作为导电连接件440的微凸块可以为圆柱形状,且排列为阵列形式。具体而言,微凸块的截面直径的尺寸取决于暴露的输出端子(即焊垫)的直径大小。该微凸块的截面直径的尺寸小于或等于50μm、特别地小于或等于20μm、更特别地小于或等于10μm、更特别地小于或等于5μm。根据输出端子的结构,微凸块440可以紧密排布,例如相邻微凸块之间的距离小于或等于50μm、特别地小于或等于20μm、甚至更小。微凸块440的材料包括铜、金、镍、锡、铅、银、铂、和/或铝。更具体地,微凸块的材料可以是铜镍锡。本实施例的微凸块具有较好的导电性能、良好的散热性能、较好的抗电子迁移能力、布线密度高和成本更低的优点。使用该微凸块可以大幅薄型化裸芯的封装体积、很大程度上缩减芯片的面积,以便于提高电子装置的集成度。此外,这样的裸芯的设计还可以减少系统寄生电容的干扰、电阻发热和信号延迟的问题。在本实施例中,半导体裸芯中的CMOS电路和控制器电路布置在同一电路层中,降低了制造工艺的复杂度。
图4C是CMOS电路和控制器电路集成的半导体裸芯400’的第二实施例示意性侧视图。如图4C所示,CMOS电路和控制器电路集成的半导体裸芯400’包括基层410’、ASIC电路层422’、CMOS电路层424’、输出端子430’、和导电连接件440’。ASIC电路层422’和CMOS电路层424’上下交叠布置。例如,ASIC电路层422’可以设置在基层410’和CMOS电路层424’之间,即CMOS电路层424’相较于ASIC电路层422’更靠近导电连接件440’。这样,CMOS电路层424’与通过导电连接件440’电连接的存储器裸芯的通信距离更短,且通过增加导电连接件的数量,可以更高效、更快速地与存储器裸芯通信。在替代的实施例中,ASIC电路层422’也可以布置在基层410’和CMOS电路层424’之上。在本实施例中,基层410’、输出端子430’和导电连接件440’与图4A中的基层410、输出端子430和导电连接件440的结构和功能基本相同,因此这里不再重复描述。在本实施例中,ASIC电路层422’和CMOS电路层424’上下交叠布置,可以进一步减小半导体裸芯的足印。
图5A和5B分别是半导体封装体的第一实施例和第二实施例的示意性侧视图,其中半导体封装体配置为混合倒装芯片和存储器裸芯在插入器的同侧。并且图6A和6B分别是半导体封装体的第三实施例和半导体封装体的第四实施例的示意性侧视图,这两个半导体封装体都配置为混合倒装芯片和存储器裸芯在插入器的异侧。图7和图8A-8H分别是如图5A所示的半导体封装体的制作方法的流程图和该制造方法中不同阶段的结构的示意性侧视图。此外,图9和图10A-10F分别是如图6所示的半导体封装体的制造方法的流程图和该制造方法中不同阶段的结构的示意性侧视图。
如图5A所示,半导体封装体500包括转接器510、CMOS电路和控制器电路集成的半导体裸芯520、以及存储器裸芯堆叠体540。半导体封装体500不包含衬底。具体而言,转接器510具有用金属填充的多个穿硅通孔512。与常规的衬底相比较,转接器510具有更小的热膨胀系数,因此具有更好的热性能和机械性能。此外,转接器510可以包括设置在其表面上的重新分布层514a、514b。与具有在电介质基部的一侧或两侧蚀刻导电层的传统的印刷电路板和衬底相比较,具有穿硅通孔512的转接器510的线宽、节点间距更小,且热膨胀系数(CTE)更低,使得封装体更加小型化、热性能更佳。
裸芯520以倒装的方式安装在转接器510上。CMOS电路和控制器电路集成的半导体裸芯520的布置和优点与如图4A和图4C所示的裸芯400和400’的布置和优点实质相同,因而在此不重复描述。注意到,在此省略了控制器电路、CMOS电路、输出端子,仅示出导电连接件522。具体地,导电连接件522可以是微凸块,并且布置在转接器510的重新分布层514a上。更小的微凸块的布置可以缩小封装体的足印面积和体积,提高封装体的集成度。微凸块的组成和优点可以如前文所述。
存储器裸芯堆叠体540布置在裸芯520上。存储器裸芯堆叠体540包括多个台阶式堆叠的存储器裸芯542,该存储器裸芯542不包括CMOS电路。没有CMOS电路的存储器裸芯更易于实现具有增加的存储密度的三维存储器裸芯。裸芯520可以大于常规的控制器裸芯,使得在没有其他支撑物的情况下,裸芯520可以独立且稳定地支撑存储器裸芯堆叠体。
此外,半导体封装体500还可以包括底部填充层530、电互连体550、模塑料560和焊球570。具体而言,底部填充层530配备在裸芯520和转接器510的重新分布层514a之间,并且覆盖全部导电连接件522。底部填充层530降低了裸芯520与转接器510之间因热膨胀系数差异所造成的应力,继而提高封装体结构的可靠性。具体地,底部填充层的材料还可以包括模制底料填充胶、毛细底料填充胶、非导电性胶、非导电性膜、及其组合。
此外,半导体封装体500还可以包括设置在存储器裸芯堆叠体540和转接器510之间的电互连体550。如图所示,存储器裸芯堆叠体540可以通过电互连体550如引线键合体耦接到转接器510的重新分布层514a上。可以想到的,引线键合体仅是示例性的。在替代的实施例中,还可以选择其他电互连体,例如焊料、微凸块、穿硅通孔等。其中,引线键合体的材料可以包括金、铝等。
附加地,半导体封装体500还可以包括包封堆叠在转接器510的表面上的裸芯520和存储器裸芯堆叠体540的模塑料560。模塑料560可以由环氧树脂材料构成。在替代的实施例中,模塑料560还可以包括例如环氧树脂和酚树脂等高分子聚合物、熔融二氧化硅、碳黑和/或金属氢氧化物。模塑料560可以保护半导体封装体500免受诸如温度、湿度、污染物等的环境影响。半导体封装体500还可以包括布置在转接器510的重新分布层514b上的焊球570。焊球570的材料可以包括:铜、金、镍、锡、铅、银、铂和/或铝。
如图5B所示的半导体封装体1100与如图5A所示的半导体封装体500实质相同,以下仅描述二者的不同部分,相同部分在此不再重复。
如图5B所示,半导体封装体1100包括转接器1110、CMOS电路和控制器电路的集成的半导体裸芯1120、以及存储器堆叠体1140a、1140b。
裸芯1120具有控制器电路和CMOS电路,其中控制器电路可以同时管理两个存储器堆叠体1140a、1140b。更具体地,CMOS电路可以控制命令以及两个存储器堆叠体1140a、1140b中的位线地址和字线地址,以对外通信。在其他实施例中,裸芯1120还可以管理和控制三个或更多个存储器堆叠体并且布置在转接器1110的上方,从而实现更大存储容量的存储器。存储器堆叠体1140a、1140b布置在裸芯1120上。存储器堆叠体1140a、1140b可以包括台阶式堆叠的多个存储器裸芯1142a、1142b。图中的堆叠方式仅是示例性的,还可以包括任意方向上偏移的堆叠方式。如图6A所示,半导体封装体600包括转接器610、CMOS电路和控制器电路集成的半导体裸芯620、和存储器裸芯堆叠体640。该半导体封装体600不包含衬底。类似地,转接器610具有用金属填充的多个穿硅通孔612。此外,转接器610包括分别设置在其两面上的重新分布层614a、614b。与传统的印刷电路板和衬底相比较,具有穿硅通孔612的转接器610的线宽、节点间距更小,且热膨胀系数(CTE)更低,使得封装体更加小型化、热性能更佳。
CMOS电路和控制器电路集成的半导体裸芯620与如图4A和图4C所示的裸芯400和400’的布置实质相同,因而在此不重复描述。注意到,在此省略了控制器电路、CMOS电路、输出端子,仅示出导电连接件622。具体地,导电连接件622可以是微凸块,并且布置在转接器610的重新分布层614b上。
存储器裸芯堆叠体640布置在转接器610的关于裸芯620的相对侧、在转接器610的重新分布层614a上。存储器裸芯堆叠体640包括台阶式堆叠的存储器裸芯642,该存储器裸芯642不包括CMOS电路。
半导体封装体600还可以包括电互连体650、模塑料660、底部填充层630、和焊球670。电互连体650配置为布置在存储器裸芯堆叠体640和转接器610之间。如图所示,存储器裸芯堆叠体640可以通过电互连体650如图所示的引线键合体耦接到转接器610的重新分布层614a上。可以想到的,引线键合体仅是示例性的。在替代的实施例中,还可以选择其他电互连体,例如焊料、微凸块、穿硅通孔等。其中引线键合体的材料可以包括金、铝等。
附加地,模塑料660配置为包封堆叠在转接器610的表面上的存储器裸芯堆叠体640。模塑料660可以由环氧树脂材料构成。在替代的实施例中,模塑料660还可以包括例如环氧树脂和酚树脂等高分子聚合物、熔融二氧化硅、碳黑和/或金属氢氧化物。此外,模塑料660可以保护半导体封装体600免受诸如温度、湿度、污染物等的环境影响。
底部填充层630设置在裸芯620和转接器610的重新分布层614b之间,并且覆盖全部导电连接件650。底部填充层630降低了裸芯620与转接器610之间因热膨胀系数差异所造成的应力,提高封装体结构的可靠性。具体地,底部填充层630的材料还可以包括模制底料填充胶(MUF)、毛细底料填充胶(CUF)、非导电性胶、非导电性膜、及其组合。底部填充层630还可以进一步覆盖裸芯620以提供更好的保护。焊球670配置为布置在转接器610的重新分布层614b上。焊球670的材料可以包括:铜、金、镍、锡、铅、银、铂和/或铝。
如图6B所示的半导体封装体1200与图6A所示的半导体封装体600实质相同,以下仅描述二者的不同部分,相同部分在此不再重复。
半导体封装体1200包括转接器1210、CMOS电路和控制器电路的集成的半导体裸芯1220和存储器堆叠体1240。具体地,存储器堆叠体1240布置转接器1210的上表面上,并且包括以倒装芯片的方式上下堆叠或垂直堆叠的多个存储器裸芯1242。具体地,存储器堆叠体1240中的多个存储器裸芯1242中的每一个包含多个穿硅通孔1244,以实现在多个存储器裸芯和转接器之间电互连。替代地,存储器裸芯可以配备有多个存储功能电路层,将多个存储功能电路层上下布置并通过穿硅通孔电互连。值得注意的,与采用引线键合的堆叠体(如图5A和5B)相比较,采用穿硅通孔的上下堆叠的存储器堆叠体1240能够实现更多层数的存储器堆叠体而不会增加芯片的足印面积,从而进一步减小了封装体的足印面积和体积,易于实现三维集成。半导体封装体1200的尺寸可以针对不同封装类型的存储器裸芯堆叠体进行调整,灵活性更强。
除了存储器堆叠体1240,半导体封装体1200还可以包括至少一个存储器堆叠体。至少一个存储器堆叠体布置在转接器1210的上表面,并且借助于在转接器1210的下表面处布置的至少一个混合倒装芯片1230实现对它们的控制。值得注意的是,两个或者更多个存储器堆叠体的堆叠方式可以是不同的。参考图7,在步骤S700中,提供转接器。如图8A所示,在转接器810中形成穿过转接器垂直互连的多个穿硅通孔(TSV)812。转接器810可以是由诸如硅的材料构成,并且穿硅通孔812中的每一个可以首先通过等离子蚀刻或激光打孔形成通孔,然后用例如铜的金属材料填充。可选地,可以在形成通孔之后,沉积介电层、阻挡层和/或种子层。可选地,在金属材料填充之后,再进行化学机械抛光。
在步骤S702中,在转接器的两个表面上分别形成重新分布层(RDL)。如图8B所示,可以例如通过物理或化学蚀刻、金属电镀等工艺方法在转接器810的上下表面分别形成重新分布层814a、814b,用于重新分配转接器810上的导电线路布局,以便于随后适配到混合倒装芯片上的微凸块的布局,并适配到存储器裸芯堆叠体的引线键合体。可以想到的,引线键合体仅是示例性的。在替代的实施例中,还可以选择其他电互连体,例如焊料、微凸块、穿硅通孔等。
然后,在步骤S704中,在晶片上制造CMOS电路和控制器电路集成的半导体裸芯。具体地,可以通过掺杂、扩散、光刻、离子注入和显影等半导体工艺来制造裸芯。
接下来,在步骤S706中,在裸芯400的远离基层410的表面上形成导电连接件430(对应于图8C-8H中的微凸块822)。导电连接件430例如可以是微凸块,其具体组成和优点已经在上文中描述,在此不再重复描述。
在步骤S708中,提供存储器晶片。然后在步骤S710中,背面研磨和锯切存储器晶片,以形成存储器裸芯。该存储器裸芯中不包含CMOS电路。
在步骤S712中,将裸芯820通过热压接合安装在转接器810上。如图8C所示,通过倒装芯片工艺将微凸块822与重新分布层814a接合,裸芯820布置在转接器810上,以便于经由微凸块822来向转接器810输出数据和信号。
在步骤S714中,裸芯820和转接器810之间分配并固化底料填充。具体地,如图8D所示,底料填充层830在裸芯820和重新分布层814a之间形成并固化,以覆盖全部微凸块822之间的间隙。底料填充层的组成和优点已经在上文中描述,在此不再重复描述。
在步骤S716中,在裸芯820上堆叠存储器裸芯842。具体地,如图8E所示,存储器裸芯堆叠体840中的每一个存储器裸芯842向右沿着其表面方向偏移了小距离并以台阶的形式堆叠,以形成存储器裸芯堆叠体840。在其他实施例中,还可以通过其他堆叠形式来形成堆叠体,例如多个存储器裸芯可以沿裸芯表面所在的平面上的任意方向偏移,或者沿着平面上两个或更多个方向进行偏移。另外,还可以采用与混合倒装芯片类似的方法来形成倒装的存储器裸芯堆叠体840,其中单独的存储器裸芯通过穿硅通孔彼此电连接。存储器裸芯堆叠体840的最低层存储器裸芯通过微凸块电互连到转接器810上的重新分布层814a。
在步骤S718中,通过电互连体来将存储器裸芯堆叠体中的每一个存储器裸芯与重新分布层电互连。具体地,如图8F所示,存储器裸芯堆叠体840中的每一个存储器裸芯842通过引线键合体850电互连,并且再通过引线键合体850电互连到重新分布层814a,以用于向转接器810传输数据和信号。
在步骤S720中,进行模制工艺。具体地,如图8G所示,将具有微凸块822的裸芯820、底料填充层830、存储器裸芯堆叠体840和引线键合体850通过模塑料860封装。
在步骤S722中,安装焊球。如图8H所示,焊球870可以安装到重新分布层814b上。焊球870可以用于将半导体封装体800安装到半导体装置(未示出),诸如印刷电路板。替代地,可以将半导体封装体800安装到至少一个其他半导体封装体。焊球的组成已经在上文中描述,在此不再重复描述。
在步骤S724中,通过各种切割方法将得到的半导体封装体单个化,从而形成如图8H所示的半导体封装体800。各种切割方法包括锯切、激光切割、水射流切割、水引导激光切割、干介质切割以及金刚石涂层线切割。虽然直线切割基本上限定了长方体、正方体或斜方体的半导体封装体800,但是,可以想到半导体封装体800还可以具有其他的形状。
下文中将描述如图6A所示的半导体封装体的制造方法,其与上述的如图5所示的半导体封装体的制造方法中的相同步骤的详细描述将被省略。
参考图9,由于步骤S900至S910、和S924的详细内容与步骤S700至S710、和S724的具体内容实质相同,因此步骤S900至S910、和S924的操作流程具体参考步骤S700至S710、和S724的详细描述,在此不再重复描述。
参考图9,在步骤S912中,存储器裸芯堆叠在转接器的上表面上。具体地,如图10A所示,在具有穿硅通孔1012的转接器1010的上部表面处的重新分布层1014a上堆叠存储器裸芯1042。
在步骤S914中,通过电互连体来将存储器裸芯堆叠体中的每一个存储器裸芯与重新分布层电互连。具体地,如图10B所示,存储器裸芯堆叠体1040中的每一个存储器裸芯1042通过引线键合体1050彼此电互连并且通过引线键合体1050电互连到重新分布层1014a上,以与转接器传输数据和信号。
在步骤S916中,进行模制工艺。具体地,如图10C所示,将包含存储器裸芯堆叠体1040和引线键合体1050通过模塑料1060包封。
在步骤S918中,将裸芯1020通过热压接合安装在转接器上。具体地,如图10D所示,通过倒装工艺将微凸块1022电耦接到转接器1010的下表面处的重新分布层1014b,并且裸芯1020布置在转接器1010的下表面上,以便于经由微凸块1022来与转接器1010传输数据和信号。
在步骤S920中,在裸芯1020和转接器之间分配并固化底料填充。具体地,如图10E所示,底料填充层1030在CMOS电路和控制器电路集成的半导体裸芯1020和重新分布层1014b之间形成,以覆盖微凸块1022的间隙。
在步骤S922中,焊球安装。如图10F所示,可以在裸芯1020之外的转接器1010的下表面的部分将焊球1070安装到重新分布层1014b上。焊球1070可以用于进一步安装半导体封装体1000,比如安装到主机装置的印刷电路板上。
已出于例证和描述的目的提出本发明的上述详细描述。它并非旨在是穷尽的或将本发明限制为所公开的精确形式。根据以上教导内容,很多修改形式和变型形式都是可能的。选择所述实施例是为了最佳地阐明本发明的原理以及其实际应用,以由此使得本领域的其他技术人员能够最佳地使用具有适合于所构想的特定用途的各种修改的本发明以及各种实施例。本发明的范围旨在由所附权利要求书限定。
Claims (20)
1.一种半导体裸芯,包括:
基层;
至少一个互补金属氧化物半导体电路,布置在所述基层的第一侧上,并且配置为与至少一个存储器裸芯通信,其中,所述至少一个存储器裸芯独立于所述半导体裸芯;
控制器电路,布置在所述基层的第一侧上,并且配置为控制所述至少一个互补金属氧化物半导体电路和所述至少一个存储器裸芯;
输出端子,布置在所述至少一个互补金属氧化物半导体电路和所述控制器电路之上,并与所述至少一个互补金属氧化物半导体电路和所述控制器电路电互连;以及
导电连接件,布置在所述输出端子的每一个之上。
2.根据权利要求1所述的半导体裸芯,其中所述至少一个互补金属氧化物半导体电路包括地址和/或命令控制电路,并且配置为与所述至少一个存储器裸芯通信以传输地址和/或命令的信号。
3.根据权利要求1所述的半导体裸芯,其中所述至少一个互补金属氧化物半导体电路包括逻辑控制阵列电路和/或模拟电路。
4.根据权利要求1所述的半导体裸芯,其中所述控制器电路配置为专用集成电路。
5.根据权利要求1所述的半导体裸芯,其中所述控制器电路和所述至少一个互补金属氧化物半导体电路布置在同一层。
6.根据权利要求1所述的半导体裸芯,其中所述控制器电路和所述至少一个互补金属氧化物半导体电路上下交叠布置。
7.根据权利要求1所述的半导体裸芯,其中所述导电连接件包括微凸块。
8.一种半导体封装体,包括:
转接器,具有第一表面和与所述第一表面相对的第二表面;
半导体裸芯,布置在所述转接器的第一表面上;以及
至少一个存储器裸芯,布置在所述转接器的第一表面之上且在所述半导体裸芯上或布置在所述转接器的第二表面上;
其中所述半导体裸芯,包括:
基层;
至少一个互补金属氧化物半导体电路,布置在所述基层的第一侧上,并且配置为与所述至少一个存储器裸芯通信,其中,所述至少一个存储器裸芯独立于所述半导体裸芯;
控制器电路,布置在所述基层的第一侧上,并且配置为控制所述至少一个互补金属氧化物半导体电路和所述至少一个存储器裸芯;
输出端子,布置在所述至少一个互补金属氧化物半导体电路和所述控制器电路之上,并与它们电互连;以及
导电连接件,布置在所述输出端子中的每一个之上。
9.根据权利要求8所述的半导体封装体,其中所述半导体封装体不包括衬底。
10.根据权利要求8所述的半导体封装体,其中所述至少一个互补金属氧化物半导体电路包括地址和/或命令控制电路,并且配置为与至少一个存储器裸芯通信以传输地址和/或命令的信号。
11.根据权利要求8所述的半导体封装体,其中所述互补金属氧化物半导体电路包括逻辑控制阵列电路和/或模拟电路。
12.根据权利要求8所述的半导体封装体,其中所述控制器电路配置为专用集成电路。
13.根据权利要求8所述的半导体封装体,其中所述控制器电路和所述至少一个互补金属氧化物半导体电路布置在同一层。
14.根据权利要求8所述的半导体封装体,其中所述控制器电路和所述至少一个互补金属氧化物半导体电路上下交叠布置。
15.根据权利要求8所述的半导体封装体,其中所述导电连接件包括微凸块。
16.根据权利要求8所述的半导体封装体,其中所述至少一个存储器裸芯包括多个上下堆叠的存储器裸芯。
17.根据权利要求8所述的半导体封装体,其中所述存储器裸芯是三维存储器裸芯,并且不包含互补金属氧化物半导体电路。
18.根据权利要求8所述的半导体封装体,还包括分别设置在所述转接器的第一表面和第二表面上的重新分布层,其分别与所述半导体裸芯的导电连接件和所述至少一个存储器裸芯电互连。
19.根据权利要求18所述的半导体封装体,还包括底料填充层,所述底料填充层布置在所述重新分布层和所述半导体裸芯之间以覆盖全部导电连接件。
20.根据权利要求8所述的半导体封装体,还包括包封在所述转接器上的所述至少一个存储器裸芯和/或所述半导体裸芯的模塑料。
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