TW201324730A - 半導體堆疊封裝體及其製造方法 - Google Patents

半導體堆疊封裝體及其製造方法 Download PDF

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Publication number
TW201324730A
TW201324730A TW101132011A TW101132011A TW201324730A TW 201324730 A TW201324730 A TW 201324730A TW 101132011 A TW101132011 A TW 101132011A TW 101132011 A TW101132011 A TW 101132011A TW 201324730 A TW201324730 A TW 201324730A
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semiconductor
semiconductor wafer
interposer
electrode
wafers
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TW101132011A
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TWI562325B (en
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Tac-Keun Oh
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Sk Hynix Inc
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Abstract

提供半導體晶片堆。該半導體晶片堆包括一半導體晶片堆，其包括在中介層之上表面上所垂直堆疊之複數個第一半導體晶片；一第二半導體晶片，其堆疊在相對於該半導體晶片堆之中介層的下表面上；以及一外部電極，其附著至相對於該中介層之該第二半導體晶片的上表面。亦提供包括該半導體晶片堆之電子系統及相關方法。

Description

半導體堆疊封裝體及其製造方法 相關申請案之對照參考資料
本申請案主張2011年12月14日在韓國智慧財產局所提出之韓國申請案第10-2011-0134708號，在此以提及方式併入該韓國申請案所述之全部。
本揭露之示範實施例係有關於半導體封裝體，以及更特別地，是有關於半導體堆疊封裝體及其製造方法。
已隨著較小及較高性能電子產品之需求持續不斷地發展用以生產大容量半導體模組及/或大容量半導體封裝體之各種技術。回應上述需求，已提出垂直地堆疊複數個半導體晶片(例如，記憶體晶片及/或邏輯晶片)之技術。
示範實施例係有關於半導體堆疊封裝體及其製造方法。
再者，實施例係有關於包括半導體堆疊封裝體之電子系統。
依據一些實施例，一種半導體堆疊封裝體包括：一中介層(interposer)；一半導體晶片堆，其包括在該中介層之上表面上所垂直堆疊之複數個第一半導體晶片；一第二半導體晶片，其堆疊在相對於該半導體晶片堆之該中介層的下表面上；以及一外部電極，其附著至相對於該中介層之該第二半導體晶片的上表面。
依據另一實施例，一種半導體堆疊封裝包括：一中介層，在該中介層中插入一第一貫穿電極(through electrode)；一半導體晶片堆，其包括在該中介層之上表面上所垂直堆疊之複數個第一半導體晶片；一第二貫穿電極，其穿過該半導體晶片堆，以電連接至該第一貫穿電極；一第二半導體晶片，其在該中介層之下表面上；以及一第三貫穿電極，其穿過該第二半導體晶片，以電連接至該第一貫穿電極。
該半導體堆疊封裝體可以進一步包括一保護層，其覆蓋該半導體晶片堆。
該複數個第一半導體晶片之每一者可以包括一記憶體晶片。
該第二半導體晶片可以包括一邏輯晶片。
該半導體堆疊封裝可以進一步包括一保護層，其覆蓋該第二半導體晶片。
依據又另一實施例，一種製造半導體堆疊封裝體之方法包括：垂直地堆疊複數個第一半導體晶片於一中介層之上表面上，以形成一半導體晶片堆；以及堆疊一第二半導體晶片於相對於該半導體晶片堆之該中介層的下表面上。
該方法可以進一步包括形成一穿過該中介層之本體的第一貫穿電極。可以在該中介層之上表面上暴露該第一貫穿電極之一端，以構成一第一接觸部分，以及可以在該中介層之下表面上暴露該第一貫穿電極之另一端，以構成一第二接觸部分。
從下面配合所附圖式之詳細敘述將更清楚了解上述及其它態樣、特徵及其它優點。
下面參考所附圖式來描述示範實施例。在沒有偏離此揭露之精神及教示下，許多不同形式及實施例係可能的，以及因此，該揭露不應該被解讀為侷限於在此所述之實施例。更確切地說，提供這些實施例，以便此揭露是完善的，以及這些實施例將對熟習該項技藝者表達該揭露之範圍。在該等圖式中，為了清楚起見，可能誇大層及區域之尺寸及相對尺寸。在整個說明書中，相同元件符號或相同元件標誌表示相同元件。
在此參考為實施例之示意圖式的剖面圖示(及中間結構)來描述示範實施例。就其本身而論，因例如製造技術及/或容限所造成之該等圖示之形狀的變化係可預期的。因此，該等揭露實施例不可解讀為對在此所述之區域的特定形狀之限制，而是要解讀為包含例如因製造所造成之形狀的偏差。
在此所使用之術語係只為了描述特定實施例及沒有意欲做為該等實施例之限制。如在此所使用，除非上下文有明確另外指示，單數形式“一(a,an)”及“該(the)”亦意欲包含複數形式。將進一步了解到，當在此使用術語“具有(has,having)”、“包括(comprises,comprising,includes and/or including)”時，其明確說明陳述特徵、步驟、操作、元件及/或組件之存在，但是沒有排除一或多個其它特徵、步驟、操作、元件、組件及/或其集體之存 在或附加。
將了解到，當提及一元件“耦接至”、“連接至”或“回應於”另一元件或“在”另一元件上時，它可直接“耦接”、“連接”或“回應於”另一元件，或者介入元件亦可以存在的。相較下，當提及一元件“直接耦接至”、“直接連接至”、“直接回應於”另一元件或“直接在”另一元件上時，沒有介入元件之存在。根據在此所使用，術語“及/或”包括該等相關列表項目中之一或多個項目的任何或所有組合。
將了解到，雖然在此可以使用術語第一、第二等來描述各種元件，但是這些元件不應該受這些術語之限制。這些術語只是用以區分一元件與其它元件。因此，一第一元件可被稱為一第二元件而不脫離本實施例之教示。
除非有其它界定，在此所使用之所有術語(包括技術及科學術語)具有相同於這些實施例所屬技藝之一般技術中之一所通常了解之意思。將進一步了解到，像在一般使用字典中所界定之那些術語應該解讀為具有與它們在該相關技藝之上下文中之意思一致的意思，以及除非在此有明確如此界定，將不以理想或過度正式意思來解讀。
第1圖係描述半導體堆疊封裝體之一範例的剖面圖。
參考第1圖，可以藉由在一封裝基板100(例如，一印刷電路板(PCB))上垂直地堆疊複數個半導體晶片，實 現一半導體堆疊封裝體。該複數個半導體晶片可以包括依序堆疊之一第一半導體晶片111、一第二半導體晶片113及一第三半導體晶片115。可以在該等堆疊半導體晶片111、113及115間以及在該第一半導體晶片111與該封裝基板100間配置一底部填充材料120(或一黏著劑)。該複數個堆疊半導體晶片111、113及115可以構成一半導體晶片堆110。該複數個堆疊半導體晶片111、113及115之內部電路可以經由電極130(例如，經由穿過該等堆疊半導體晶片111、113及115之矽介層(TSVs))彼此電連接。在該封裝基板100上安裝該半導體晶片堆110後，可以形成一像環氧樹脂模製化合物(EMC)之模製構件140，以覆蓋該半導體晶片堆110。隨後，可以在相對於該半導體晶片堆110之該封裝基板100的下表面上形成外部電極150(例如，焊球)，藉此實現該半導體堆疊封裝體。
依據第1圖所述之半導體堆疊封裝體，在該封裝基板100上安裝該半導體晶片堆110。因此，在該半導體晶片堆110與該封裝基板100間再插入一額外半導體晶片可能具有一些限制。在該半導體晶片堆110與該封裝基板100間配置一額外半導體晶片之情況中，在該封裝基板100上安裝該額外半導體晶片後，應該在該額外半導體晶片上堆疊該半導體晶片堆110。然而，在此情況下，可能需要一複雜製程及亦可能需要一準確控制製程。
第2至12圖係描述依據一些實施例之製造半導體堆疊封裝體的方法及藉此所製造之半導體堆疊封裝體的剖 面圖。為了容易及方便說明，將結合一半導體晶片堆包括3個半導體晶片之範例來描述本實施例。然而，構成該半導體晶片堆之半導體晶片的數目並非侷限於3個。例如，構成該半導體晶片堆之半導體晶片的數目可以是4個、8個或更多。
參考第2圖，可以在一封裝製程期間使用一中介層200做為一個或一個以上半導體晶片堆之處置構件(handling member)。在本實施例中，將描述該中介層200為一上面安裝該等半導體晶片堆之非撓性基板。然而，在一些實施例中，該中介層200可以是一薄膜狀基板、一帶狀基板或一片狀基板。
該中介層200可以是一半導體基板(例如，一矽基板或一鍺基板)或一絕緣體基板(例如，一碳聚合物基板、一玻璃纖維基板或一樹脂基板)。在一些其它實施例中，該中介層200可以是一金屬基板。在一些其它實施例中，該中介層200可以包括一絕緣體基板及在該絕緣體基板中或上所配置之導電電路內連線。該等導電電路內連線可以由鐵、銅、鎳或金所形成。當該中介層200係一半導體基板時，可以在該半導體基板之一表面上塗佈一像氧化物材料之絕緣層，以使該半導體基板與其它元件電絕緣。當該中介層200係一金屬基板時，亦可以在該金屬基板之一表面上塗佈一絕緣層，以使該金屬基板與其它元件電絕緣。
當該中介層200及在該中介層200上所堆疊之半導體晶片包含相同材料(例如，一矽材料)時，該中介層200 之熱膨脹係數(CTE)可能等於或相似於在該中介層200上之半導體晶片的熱膨脹係數。因此，可減輕或防止在該中介層200與該中介層200上之半導體晶片間所產生之機械應力及/或物理應力。於是，縱使該中介層200及在該中介層200上所堆疊之半導體晶片的溫度係變化的，裂縫(cracks)可能沒有形成於該中介層200及/或該等半導體晶片中。再者，一矽材料呈現絕佳導熱率。因此，在一些實施例中，該中介層200可以包括一矽材料。
可以蝕刻該中介層200，以形成從該中介層200之上表面203延伸至該中介層200之主體區域(bulk region)中的溝槽201。可以使用一濕式蝕刻製程、一乾式蝕刻製程、一雷射鑽孔製程或一微鑽孔製程來形成該等溝槽201。該等溝槽201之深度可以依在該半導體堆疊封裝體之形成後所剩餘之該中介層201的最後厚度而不同。在一些實施例中，可以使該等溝槽201形成以到達該中介層200之下表面205。亦即，該等溝槽201可以對應於完全穿過該中介層200之通孔。然而，雖然一相對厚的中介層200係有助於在一封裝製程期間處置在該中介層200上所安裝之半導體晶片，但是一相對薄的中介層200可以有利於該半導體堆疊封裝體。因此，在一些實施例中，如第2圖所述，該等溝槽201之深度可以小於該中介層200之初始厚度。
一導電層可以填充該等溝槽201，藉此在該等溝槽201之個別溝槽中形成第一貫穿電極210。該等第一貫穿電極210(例如，貫穿矽介層(TSVs))可以做為電接觸結 構。
填充該等溝槽201之導電層可以包括一金屬材料、一摻雜多晶矽材料或一奈米碳管(CNT)材料。該金屬材料可以包括鋁(Al)、鐵(Fe)、銅(Cu)、鎳(Ni)、金(Au)或其金屬合金。此外，可以在該等第一貫穿電極210與該中介層200間配置一像氧化矽材料之絕緣層(未顯示)。可以形成該絕緣層，以防止該等第一貫穿電極210電連接至該中介層200。如果該中介層200係一絕緣體基板，則可以省略在該等第一貫穿電極210與中介層200間形成該絕緣層。
該等第一貫穿電極210之每一者的上部分可以相當於一第一接觸部分211及可以相鄰於該中介層200之上表面203。亦即，可以在該中介層200之上表面203上暴露該等第一貫穿電極210之第一接觸部分211。在一些實施例中，該等第一貫穿電極210之第一接觸部分211可以從該中介層200之上表面203向上突出。使該等第一接觸部分211從該上表面203突出，可以改善該等第一接觸部分211與其它元件間之電性及實體連接的可靠性。
該等第一貫穿電極210之下部分可以相當於第二接觸部分213及可以在一後續製程中電連接至外部裝置。在本實施例中，如第2圖所述，可以在該等溝槽201之下區域中埋置該等第一貫穿電極210之第二接觸部分213。然而，如果該等溝槽201係形成具有一穿過該中介層200之通孔形狀，則可以在該中介層200之下表面205 上暴露該等第二接觸部分213。考量到在一後續製程中所形成之複數個半導體晶片堆的電連接，可以使該等第一貫穿電極210形成為包含有複數個組。
參考第3圖，可以準備複數個第一半導體晶片300。在一後續製程中，可以在該中介層200上堆疊該等第一半導體晶片300，其參考圖2來描述。為了圖示之簡單化，在第3圖中只描述該複數個第一半導體晶片300中之一。
該等第一半導體晶片300可以是揮發性記憶體晶片，例如，動態隨機存取記憶體(DRAM)晶片。然而，該等第一半導體晶片300並非侷限於揮發性記憶體晶片。例如，該等第一半導體晶片300可以是非揮發性記憶體晶片(例如，快閃記憶體晶片)、包括各種邏輯電路之邏輯晶片或網路通信用之通信晶片。將結合DRAM晶片做為該等第一半導體晶片300之一範例來描述本實施例。
可以形成第二貫穿電極310，以穿過該等第一半導體晶片300之每一者。該等第二貫穿電極310可以充當使該等第一半導體晶片300電連接至其它晶片或其它基板之電接觸結構。可以在該等第一半導體晶片300之上表面中形成主動區域(未顯示)及可以在該等主動區域中及上形成積體電路。該等第二貫穿電極310可以電連接至該等第一半導體晶片300之積體電路。該等第二貫穿電極310可以藉由再分佈內連線(redistributed interconnections)(未顯示)電連接至該等第一半導體晶片300之積體電路。該等第二貫穿電極310可以形成於穿 過該等第一半導體晶片300之第一通孔301的個別通孔中。亦即，可以藉由以一導電材料填充該等第一通孔301來形成該等第二貫穿電極310。可以使用一用以形成貫穿矽介層(TSVs)之技術，製造這些第二貫穿電極310。該等第二貫穿電極310可以由一導電材料(例如，一金屬材料、一摻雜多晶矽材料或一奈米碳管(CNT)材料)所形成。該金屬材料可以包括鋁(Al)、鐵(Fe)、銅(Cu)、鎳(Ni)、金(Au)或其金屬合金。
該等第二貫穿電極310之每一者在其兩端上可以分別包括一第三接觸部分312及一第四接觸部分313。該第三及第四接觸部分312及313可以電連接至其它元件。可以在該等第一半導體晶片300之上下表面上暴露該第三及第四接觸部分312及313。在一些實施例中，該第三及第四接觸部分312及313可以從該等第一半導體晶片300之上下表面突出。使該第三及第四接觸部分312及313從該上下表面突出，可以改善該第三及第四接觸部分312及313與其它元件間之電性及實體連接的可靠性。此外，可以以一金凸塊(GSB)、一銅柱凸塊(CPB)或一焊料凸塊覆蓋該第三及第四接觸部分312及313之每一者。
參考第4圖，可以在第2圖所述之中介層200的上表面203上堆疊在參考第3圖所述之第一半導體晶片300中的一對第一晶片410。可以在該等第一貫穿電極210中之第一組貫穿電極210上堆疊該對第一晶片410中之一，以及可以在該等第一貫穿電極210中之第二組貫穿 電極210上堆疊該對第一晶片410中之另一者。雖然結合在該中介層200上垂直地堆疊相同於該等第一半導體晶片300之晶片的範例來描述下面實施例，但是本發明觀念亦可以應用至可以在該中介層200上垂直地堆疊不同功能及/或尺寸之晶片的其它範例。
再者，縱使以下使用術語“該等第一半導體晶片300之一第一晶片410”、“該等第一半導體晶片300之一第二晶片450”、“該等第一半導體晶片300之一第二晶片450”、“該等第一半導體晶片300之一第三晶片470”等來彼此區分，該第一晶片410、該第二晶片450及該第三晶片470可以具有相同於第3圖所述之第一半導體晶片300的構成。縱使以下使用術語“該第二貫穿電極之一第一部分411”、“該第二貫穿電極之一第二部分451”、“該第二貫穿電極之一第三部分471”等來區分，該第一部分411、該第二部分451及該第三部分471可以具有相同於第3圖所述之第二貫穿電極310的構成。亦即，該第一部分411、該第二部分451及該第三部分471之每一者可以包括一對應於第3圖所述之第二貫穿電極310的第三接觸部分312之第三接觸部分412及一對應於第3圖所述之第二貫穿電極310的第四接觸部分313之第四接觸部分413。
再次參考第4圖，可以在該中介層200之上表面203上堆疊一對第一晶片410，以便穿過該等第一晶片410之第二貫穿電極的第一部分411電連接至在該中介層200中所配置之該等第一貫穿電極210的個別電極。當 從一平面圖觀看時，該等第一晶片410可以配置成彼此隔開。可以在該等第一晶片410之上表面上暴露該等第一部分411之第三接觸部分412，以及該等第一部分411之第四接觸部分413可以電連接至該等第一貫穿電極210之第一接觸部分211的個別接觸部分。可以在該中介層200與該等第一晶片410間配置一第一中間絕緣層430。該第一中間絕緣層430可以充當一黏著劑及亦可以使該等第一晶片410與該中介層200電絕緣。
該第一中間絕緣層430可以包括一底部填充層(例如，一樹脂層)、一非導電膜(NCF)、一非導電膠(NCP)、一異向性導電膜(ACF)或一異向性導電膠(ACP)。
參考第5圖，可以在該等第一晶片410之個別晶片上堆疊第二晶片450，以及可以在該等第二晶片450之個別晶片上堆疊第三晶片470。亦可以在該等第一晶片410與該等二晶片450間及在該等第二晶片450與該等第三晶片470間配置其它第一中間絕緣層430。雖然在該等第一晶片410上堆疊該等第二晶片450及該等第三晶片470，但是穿過該等第二晶片450之第二部分451可以與該等第一部分411及穿過該等第三晶片470之第三部分471之個別部分垂直地對準，以及該等第三部分471亦可以與該等第二部分451之個別部分垂直地對準。於是，該等第二部分451可以與該等第一部分411之個別部分電連接，以及該等第三部分471可以與該等第二部分451之個別部分電連接。
依序及垂直堆疊之該第一晶片410、該第二晶片450 及該第三晶片470的一組可以構成一半導體晶片堆400。於是，在本實施例中，如第5圖所述，可以在該中介層200上配置一對半導體晶片堆400，以致於使該對半導體晶片堆400彼此橫向地隔開。雖然該描述實施例顯示在該中介層200上之一對半導體晶片堆400，但是在其它實施例中，可以在該中介層200上配置一對以上之半導體晶片堆400。另外，垂直堆疊之該第一部分411、該第二部分451及該第三部分471的一組可以構成完全穿過該半導體晶片堆400之單一第二貫穿電極401。在每一第二貫穿電極401中，在該第一部分411與該第二部分451間及在該第二部分451與該第三部分471間配置一像凸塊之連接構件(未顯示)。同樣地，亦可以在該等第一貫穿電極210與該等第一部分411間配置另一連接構件。該等連接構件可以改善該等第一部分411與該等第二部分451間、該等第二部分451與該等第三部分471間及該等第一貫穿電極210與該等第一部分411間之電性連接的可靠性。在一些實施例中，當使用一像異向性導電膜(ACF)或異向性導電膠(ACP)之異向性導電層做為該第一中間絕緣層430時，可以不需要像凸塊之連接構件。
參考第6圖，可以形成一第一保護層510，以覆蓋該等半導體晶片堆400。可以形成該第一保護層510，以保護該等半導體晶片堆400不受外部環境之影響。該第一保護層510可以填充該等半導體晶片堆400間之空間，藉此覆蓋該等半導體晶片堆400之所有側壁。該第 一保護層510可以使用一第一模製製程(first molding process)由一環氧樹脂模製化合物(EMC)材料所形成。在一些實施例中，可以使該第一保護層510形成為包括有一熱固性樹脂材料、一氧化矽(silica)材料或一非導電填充材料。在其它實施例中，可以使該第一保護層510形成包括有一絕緣樹脂材料、一非導電膜(NCF)、一非導電膠(NCP)、一異向性導電膜(ACF)或一異向性導電膠(ACP)。
在一些實施例中，可以形成該第一保護層510，以保留該等半導體晶片堆400之暴露上表面及覆蓋該等半導體晶片堆400之側壁。甚至當執行後續製程時，該第一保護層510可以保護該等半導體晶片堆400。因此，亦可以形成該第一保護層510，以完全覆蓋該等半導體晶片堆400之所有表面。
當以該第一保護層510完全覆蓋該等半導體晶片堆400時，該中介層200、該等半導體晶片堆400及該第一保護層510可以充當一具有半成品形狀之晶片堆疊基板501。於是，可以在該晶片堆疊基板501上安裝至少一個額外半導體晶片。
該晶片堆疊基板501可以比該中介層200及/或每一半導體晶片堆400厚，因為除了該中介層200及該等半導體晶片堆400之外，該晶片堆疊基板501還包括該第一保護層510。再者，由於該第一保護層510之存在，該晶片堆疊基板501可以具有一相對高的強度。因此，縱使使用該晶片堆疊基板501來執行後續製程，該第一 保護層510可以抑制或防止製程缺陷(例如，該晶片堆疊基板501之翹曲及/或在該晶片堆疊基板501中之裂縫)之發生或產生。此外，如第6圖所述，可以以該第一保護層510來覆蓋該等半導體晶片堆400之所有表面及相對於該等半導體晶片堆400之該中介層200的下表面205可以保持暴露。因此，可對該中介層200之暴露下表面205額外地施加各種製程而沒有對該等半導體晶片堆400有任何毀損。例如，可在該中介層200之暴露下表面205上堆疊額外半導體晶片而沒有對該等半導體晶片堆400有任何毀損。亦即，當執行該等額外製程時，可改善製程裕度(process margin)。
參考第7圖，可以使該中介層200之下表面205(例如，見未凹陷下表面之視圖的第4圖)凹陷，以移除該中介層200之下部分。在使該中介層200之下表面(亦即，下部分)凹陷前，可以形成該第一保護層510，以覆蓋該等半導體晶片堆400。結果，一相對於該第一接觸部分211之凹陷下表面206可以暴露該等第一貫穿電極210之第二接觸部分213(見圖2)。在該中介層200之下部分的移除後，該等第一貫穿電極210之第二接觸部分213可以從該中介層200之凹陷下表面206向下突出。縱使因該中介層200之下部分的移除而減少該中介層200之厚度，該晶片堆疊基板501仍然可以因該第一保護層510之存在而具有一相對高的強度。在一些實施例中，該下表面205及/或該凹陷下表面206沒有被該第一保護層510所覆蓋。因此，當在該中介層200之凹陷下表面206 上堆疊額外半導體晶片時，可能毀損該等第一半導體晶片410、450及470。
在一些實施例中，可以使用一研磨製程、一化學機械研磨(CMP)製程或一回蝕刻製程，使該中介層200之下表面205凹陷。可以使用一乾式蝕刻製程或一濕式蝕刻製程來執行該回蝕刻製程。
參考第8圖，可以在相對於該等半導體晶片堆400之該中介層200的凹陷下表面206上堆疊第二半導體晶片600，其中相對於該等半導體晶片堆400表示使每一行之第二半導體晶片600配置在該等半導體晶片堆400之每一者的下面(或上方，依觀看位置而定)。當構成該等半導體晶片堆400之該等第一半導體晶片410、450及470係像DRAM晶片之記憶體晶片時，該等第二半導體晶片600可以是控制該等記憶體晶片之控制晶片或邏輯晶片。在一些實施例中，該等第一及第二半導體晶片410、450、470及600可以是相同類型之晶片，但是彼此具有不同尺寸。
該等第二半導體晶片600之每一者可以包括鄰接其上表面605之第五接觸部分611及鄰接相對於該上表面605之下表面的第六接觸部分613。該等第五接觸部分611可以電連接至一外部裝置，以及該等第六接觸部分613可以電連接至該等第一半導體晶片410、450及470。 該等第五及第六接觸部分611及613可以具有連接墊形狀。在另一選擇中，該等第五接觸部分611可以對應於穿過該等第二半導體晶片600之第三貫穿電極610的第 一端，以及該等第六接觸部分613可以對應於穿過該等第二半導體晶片600之第三貫穿電極610的第二端。第8圖描述該等第五接觸部分611及該等第六接觸部分613對應於穿過該等第二半導體晶片600之第三貫穿電極610的第一端及第二端。然而，在一些實施例中，可以在該等第二半導體晶片600之上下表面上配置連接墊，以及該等連接墊可以直接連接至該等第三貫穿電極610之第五及第六接觸部分611及613或可以經由再分佈內連線(未顯示)間接連接至該等第五及第六接觸部分611及613。
如上所述，該等第二半導體晶片600可以堆疊在該中介層200之凹陷下表面206上。特別地，可以在該中介層200之凹陷下表面206上配置該等第二半導體晶片600，以及可以藉由對該等第二及第六接觸部分213及613施加熱及壓力，使該等第六接觸部分613連接至該等第一貫穿電極210之第二接觸部分213且與其結合。可將該等第二半導體晶片600直接安裝在包括該中介層200的該晶片堆疊基板501上。因此，可以使用相同或相似於晶片對晶圓(chip on wafer,COW)接合製程之技術，在該晶片堆疊基板501上安裝該等第二半導體晶片600。依據本實施例，縱使在該中介層200之凹陷下表面206上安裝該等第二半導體晶片600，該等第二半導體晶片600可以電連接至在相對於該凹陷下表面206之該中介層200的上表面上所安裝之該等半導體晶片堆400，其中可以藉由穿過該中介層200之該等第一貫穿電極 210使該等第二半導體晶片600與該等半導體晶片堆400電連接。
參考第9圖，可以在該中介層200之凹陷下表面206上形成一第二保護層530，以覆蓋該等第二半導體晶片600。可以使用一第二模製製程來形成該第二保護層530。該第二模製製程可以實質相同或相似於在該第一保護層510之形成中所使用之該第一模製製程。雖然形成該第二保護層530，但是該晶片堆疊基板501可以充當一支撐該等第二半導體晶片600之基板。在該第二模製製程期間，因為以該第一保護層510覆蓋該等半導體晶片堆400，因此可能不會損壞該等半導體晶片堆400。
如第9圖所述，可以形成該第二保護層530，以覆蓋使該等第二半導體晶片600電連接至一外部裝置之該等第五接觸部分611。然而，在一些實施例中，可以形成該第二保護層530，以覆蓋該等第二半導體晶片600之側壁及暴露該等第五接觸部分611及該等第二半導體晶片600之上表面605。亦即，可以額外地平坦化第9圖所述之第二保護層530，以暴露該等第五接觸部分611及該等二半導體晶片600之上表面605。
參考第10圖，可以圖案化第9圖所述之第二保護層530，以形成選擇性地暴露該等第五接觸部分611之開口531。可以藉由使用一選擇性蝕刻製程或一鑽孔製程選擇性地移除該第二保護層530之一些部分，以形成該等開口531。該鑽孔製程可以包括一雷射鑽孔製程或一微鑽孔製程。
參考第11圖，可以在該等開口531所暴露之該等第五接觸部分611的個別部分上形成外部電極650。該等第五接觸部分611可以對應於該等第三貫穿電極610之端部。然而，在使用電連接至該等第五接觸部分611之再分佈內連線(未顯示)的情況中，該等開口531之形成可以暴露該等再分佈內連線之一些部分及可以在該等再分佈內連線之暴露部分(對應於連接墊)上形成該等外部電極650。可以使該等外部電極650形成為具有焊球形狀、焊料凸塊形狀、導電板形狀或內連線形狀。
參考第12圖，在該第二保護層530與該等外部電極650之形成後，可以選擇性地移除該等半導體晶片堆400間之第一保護層510、該中介層200之一部分及該等第二半導體晶片600間之第二保護層530，以使該等半導體晶片堆400及該等第二半導體晶片600分離成複數個離散半導體堆疊封裝體690。可以藉由一使用鑽石刀或雷射之切割製程來執行該分離製程。
如第12圖所述，依據第2至12圖所述之實施例的半導體堆疊封裝體690之每一者可以建構成包括該等半導體晶片堆400中之一、該等第二半導體晶片600中之一及其間之該中介層200。在每一半導體堆疊封裝體690中，可以使穿過該中介層200之該等第一貫穿電極210電連接至穿過該半導體晶片堆400之該等第二貫穿電極401的個別電極，以及可以使該等第一貫穿電極210電連接至該第二半導體晶片600之第六接觸部分613的個別部分。可以使該第二半導體晶片600之第五接觸部分 611電連接至該等外部電極650。該半導體晶片堆400可以包括具有高整合密度及大資料容量之複數個堆疊半導體晶片(例如，複數個堆疊記憶體晶片)，以及在該中介層200上所安裝之做為單一晶片的該第二半導體晶片600可以是一具有相對高的信號處理速度之邏輯晶片(例如，一控制晶片)。
如果該半導體晶片堆400包括複數個堆疊記憶體晶片及該第二半導體晶片600係一邏輯晶片，該邏輯晶片可以配置成比在該半導體晶片堆400與該外部電極650間之距離更靠近該等外部電極650。該邏輯晶片之定位可以協助該半導體堆疊封裝體690之操作速度及可靠性。於是，當該等半導體晶片111、113及115係記憶體晶片且如第1圖所示只堆疊在該基板100之一表面上時，可以使用該邏輯晶片做為該半導體晶片堆110之最下面的晶片，以改善該半導體堆疊封裝體690之操作速度及可靠性。在此情況下，如第13圖所述，可以依序堆疊一邏輯晶片20及複數個記憶體晶片31。
參考第13圖，具有第一貫穿電極21之該邏輯晶片20可以堆疊在一基板10上，以便與外部電極(未顯示)(例如，附著至相對於該邏輯晶片20之該基板10的下表面之焊球)有相對快速的資料通信。在此情況下，可以在相對於該基板10之該邏輯晶片20上堆疊該複數個記憶體晶片31。因此，可以依據該等堆疊記憶體晶片31之數目來決定穿過該等堆疊記憶體晶片31的第二貫穿電極33的每一者之實質長度。亦即，如果該等堆疊記憶體晶 片31之數目增加，則該等第二貫穿電極33之每一者的垂直長度亦可能增加。因此，當對包括該等堆疊記憶體晶片31之一半導體晶片堆30的上部分施加熱及壓力，以連接及/或接合該等第二貫穿電極33之下部分至該等第一貫穿電極21(見第13圖之結合部分)時，該等第二貫穿電極33之垂直長度可能變成增加，其中藉由該等第二貫穿電極33來傳導熱及壓力。於是，當該等堆疊記憶體晶片31之數目增加時，可能變成更難以可靠性完成該等第一貫穿電極21與該等第二貫穿電極23間之電性及機械結合/連接。
為了甚至在該等堆疊記憶體晶片31之數目增加的情況下可獲得該等第一貫穿電極21與該等第二貫穿電極33間之可靠結合/連接，亦應該增加對該半導體晶片堆30所施加之熱能及壓力。在此情況下，可能因熱能及壓力之增加而損壞鄰接該半導體晶片堆30之上表面所配置之該等記憶體晶片31。結果，該半導體晶片堆30可能故障。
在另一選擇中，為了甚至在該等堆疊記憶體晶片31之數目增加的情況下可獲得該等第一貫穿電極21與該等第二貫穿電極33間之可靠結合/連接，值得考量的是，每當以一在該等堆疊記憶體晶片31間之黏著劑32來堆疊該等堆疊記憶體晶片31之每一者時，在該等可靠結合/連接後執行一電功能測試。然而，在此情況下，可能花相對長的時間來製造該半導體堆疊封裝體。因此，該半導體堆疊封裝體之製造成本可能隨著生產量之下降而增 加。
相較於上面第13圖所述之比較範例，可以藉由在該中介層200之一表面上依序安裝該第一至第三晶片410、450及470(對應於記憶體晶片)及藉由在該中介層200之另一表面上安裝該第二半導體晶片600(對應於一不同於該第一至第三晶片410、450及470之邏輯晶片)來製造第8圖所述之依據該實施例的半導體堆疊封裝體。因此，當在該中介層200上安裝該第二半導體晶片600時，可能不需要過大的熱能及過大的壓力。
此外，如上所述，該第二半導體晶片600可以實質安裝在包括該中介層200及該第一保護層510之該晶片堆疊基板501上。於是，甚至當該第二半導體晶片600係安裝在該晶片堆疊基板501上時，可藉由該中介層200及該第一保護層510來保護該第一至第三晶片410、450及470。相較之下，當使該邏輯晶片20與該半導體晶片堆30結合時，可以在沒有任何其它基板或任何其它支撐物(例如，一保護層)之情況下處置及/或轉移第13圖所述之比較範例的半導體晶片堆30。因此，當使該邏輯晶片20與該半導體晶片堆30結合時或當在該半導體晶片堆30與該邏輯晶片20間之結合後執行一後續功能測試時，可能更易損壞該半導體晶片堆30。然而，依據第2至12圖所述之示範實施例，可以藉由該中介層200及該第一保護層510完全包圍該等半導體晶片堆400。因此，可以使用穿過該中介層200之該等第一貫穿電極210來電測試該等半導體晶片堆400，以及甚至當轉移或處置 該等半導體晶片堆400時，可藉由該中介層200及該第一保護層510來封裝該等半導體晶片堆400。因此，當轉移或處置該晶片堆疊基板501時，可以不損壞該等半導體晶片堆400。
依據第4及5圖之敘述，可以在該中介層200上依序堆疊該第一至第三晶片410、450及470。然而，本發明觀念並非侷限於此。例如，可以主要藉由以相同或相似於第13圖所述之比較範例的方式依序堆疊該第一至第三晶片410、450及470來形成該等半導體晶片堆400，以及可以在該中介層200上直接安裝該等半導體晶片堆400。
第14圖係描述依據本發明觀念之修改實施例的半導體堆疊封裝體及描述製造該等半導體堆疊封裝體之方法的剖面圖。這些修改實施例係相似於第2至12圖所述之先前實施例。因此，為了避免重複說明，下面將主要詳細描述本修改實施例與第2至12圖所述之先前實施例間之差異。
參考第14圖，可以形成一第二保護層535，以覆蓋該第二半導體晶片600之整個側壁607及暴露該第二半導體晶片600之上表面605。例如，可以使該第二保護層535成型或變形成具有一暴露該第二半導體晶片600之上表面605的平面。
依據第2至12圖所述之實施例，該等半導體晶片堆400之每一者可以包括依序堆疊之3個晶片410、450及470。然而，本發明觀念並非侷限於此。例如，依據第 14圖所述之修改實施例，該等半導體晶片堆400之每一者可以進一步包括一堆疊在該第三晶片470上之第四晶片490且在該第三晶片470與該第四晶片490間具有該第一中間絕緣層430。該第四晶片490可以建構成沒有包括任何穿過其本身之貫穿電極。
第15圖係描述包括依據一些實施例之半導體堆疊封裝體的電子系統之一範例的示意方塊圖。可以在電子系統700(例如，電腦、行動電話之類)中使用依據前述實施例之半導體堆疊封裝體。該電子系統700可以建構成包括一主板701及在該主板701上所安裝之各種電子裝置及/或封裝體。該主板701可以是一印刷電路板(PCB)。可以使用第2至12、14及15圖所述之實施例中之一來實現該等電子封裝體中之至少一者。
該電子系統700可以包括一算術處理器703、一記憶體/控制單元705、一儲存單元707、一視訊處理器709及一網路配接器711，它們係安裝在該主板701上，經由一資料匯流排(未顯示)而彼此通信。該算術處理器703可以是一微處理器，以及該記憶體/控制單元705可以是一半導體堆疊封裝體，其包括像DRAM晶片之記憶體晶片及一控制該等記憶體晶片之操作的邏輯晶片。再者，該儲存單元707可以包括一非揮發性記憶體裝置及/或一硬碟，以及該視訊處理器709可以是一半導體堆疊封裝體，其包括像用以暫時儲存視訊資料之視訊DRAM晶片的記憶體晶片及一用以處理/控制在該等視訊DRAM晶片中所儲存之視訊資料的視訊控制器。此外，該網路配 接器711可以對應於一介面單元。亦即，該網路配接器711可以傳送電資料至一外部通信網路或可以從該外部通信網路接收電性資料。
可以將在該儲存單元707中所儲存之程式資料經由該資料匯流排載入該記憶體/控制單元705及可以藉由該算術處理器703來執行在該儲存單元707中所儲存之程式資料。在一些實施例中，該儲存單元707可以建構成包括一具有複數個快閃記憶體裝置之固態硬碟(SSD，亦稱為一固態驅動器)。此外，該電子系統700可以進一步包括一用以接收資料之輸入裝置713及一用以顯示其中所處理之資料的輸出裝置715。該輸入裝置713可以包括一鍵盤或一觸控式顯示螢幕，以及該輸出裝置715可以包括一顯示監視器、一印表機或一顯示螢幕。該電子系統700可以對應於一個人電腦、一伺服器或一行動系統。該行動系統可以包括一膝上型電腦、一手持式電腦或一智慧型手機。
依據上述實施例，可以在一基板(例如，一中介層)之第一表面上依序堆疊複數個第一半導體晶片及可以在相對於該第一表面之該基板的第二表面上堆疊至少一個第二半導體晶片。該第二半導體晶片在功能及/或尺寸上可以不同於該第一半導體晶片。於是，上述實施例可以處理只在該基板之一表面上依序堆疊該第二半導體晶片及該等第一半導體晶片時所發生之問題。
為了說明，上面已揭露本發明觀念之實施例。熟習該項技藝者將察覺到，在不脫離所附申請專利範圍所揭 露之本發明觀念的範圍及精神內，各種修改、附加及替換係可能的。
20‧‧‧邏輯晶片
21‧‧‧第一貫穿電極
30‧‧‧半導體晶片堆
31‧‧‧記憶體晶片
32‧‧‧黏著劑
33‧‧‧第二貫穿電極
100‧‧‧封裝基板
110‧‧‧半導體晶片堆
111‧‧‧第一半導體晶片
113‧‧‧第二半導體晶片
115‧‧‧第三半導體晶片
120‧‧‧底部填充材料
130‧‧‧電極
140‧‧‧模製構件
150‧‧‧外部電極
200‧‧‧中介層
201‧‧‧溝槽
203‧‧‧上表面
205‧‧‧下表面
206‧‧‧凹陷下表面
210‧‧‧第一貫穿電極
211‧‧‧第一接觸部分
213‧‧‧第二接觸部分
300‧‧‧第一半導體晶片
301‧‧‧第一通孔
310‧‧‧第二貫穿電極
312‧‧‧第三接觸部分
313‧‧‧第四接觸部分
400‧‧‧半導體晶片堆
401‧‧‧第二貫穿電極
410‧‧‧第一晶片
411‧‧‧第一部分
412‧‧‧第三接觸部分
413‧‧‧第四接觸部分
430‧‧‧第一中間絕緣層
450‧‧‧第二晶片
451‧‧‧第二部分
470‧‧‧第三晶片
471‧‧‧第三部分
490‧‧‧第四晶片
501‧‧‧晶片堆疊基板
510‧‧‧第一保護層
530‧‧‧第二保護層
531‧‧‧開口
535‧‧‧第二保護層
600‧‧‧第二半導體晶片
605‧‧‧上表面
607‧‧‧側壁
610‧‧‧第三貫穿電極
611‧‧‧第五接觸部分
613‧‧‧第六接觸部分
650‧‧‧外部電極
690‧‧‧半導體堆疊封裝體
700‧‧‧電子系統
701‧‧‧主板
703‧‧‧算術處理器
705‧‧‧記憶體/控制單元
707‧‧‧儲存單元
709‧‧‧視訊處理器
711‧‧‧網路配接器
713‧‧‧輸入裝置
715‧‧‧輸出裝置
第1圖係描述半導體堆疊封裝體之一範例的剖面圖；第2至12圖係描述依據一些示範實施例之製造半導體堆疊封裝體的方法及藉此所製造之半導體堆疊封裝體的剖面圖；第13圖係描述一比較範例之半導體堆疊封裝體的剖面圖，以敘述依據一些實施例之半導體堆疊封裝體及其製造方法之優點；第14圖係描述依據本發明觀念之修改實施例的半導體堆疊封裝體及描述製造該等半導體堆疊封裝體之方法的剖面圖；以及第15圖係描述包括依據一些實施例之半導體堆疊封裝體的電子系統之一範例的示意方塊圖。
200‧‧‧中介層
206‧‧‧凹陷下表面
210‧‧‧第一貫穿電極
213‧‧‧第二接觸部分
400‧‧‧半導體晶片堆
401‧‧‧第二貫穿電極
410‧‧‧第一晶片
411‧‧‧第一部分
430‧‧‧第一中間絕緣層
450‧‧‧第二晶片
451‧‧‧第二部分
470‧‧‧第三晶片
471‧‧‧第三部分
501‧‧‧晶片堆疊基板
510‧‧‧第一保護層
530‧‧‧第二保護層
600‧‧‧第二半導體晶片
605‧‧‧上表面
610‧‧‧第三貫穿電極
611‧‧‧第五接觸部分
613‧‧‧第六接觸部分
650‧‧‧外部電極
690‧‧‧半導體堆疊封裝體

Claims (15)

  1. 一種半導體堆疊封裝體，包括：一中介層；一半導體晶片堆，其包括在該中介層之上表面上所垂直堆疊之複數個第一半導體晶片；一第二半導體晶片，其堆疊在相對於該半導體晶片堆之該中介層的下表面上；以及一外部電極，其附著至相對於該中介層之該第二半導體晶片的上表面。
  2. 如申請專利範圍第1項之半導體堆疊封裝體，進一步包括：一第一貫穿電極，其穿過該中介層；一第二貫穿電極，其穿過該等第一半導體晶片，以使該等第一半導體晶片電連接至該第一貫穿電極；以及一第三貫穿電極，其穿過該第二半導體晶片，以使該第一貫穿電極電連接至該外部電極。
  3. 一種半導體堆疊封裝體，包括：一中介層，在該中介層中插入一第一貫穿電極；一半導體晶片堆，其包括在該中介層之上表面上所垂直堆疊之複數個第一半導體晶片；一第二貫穿電極，其穿過該半導體晶片堆，以電連接至該第一貫穿電極；一第二半導體晶片，其在該中介層之下表面上；以及 一第三貫穿電極，其穿過該第二半導體晶片，以電連接至該第一貫穿電極。
  4. 如申請專利範圍第3項之半導體堆疊封裝體，進一步包括一覆蓋該半導體晶片堆之保護層。
  5. 如申請專利範圍第3項之半導體堆疊封裝體，其中該複數個第一半導體晶片之每一者包括一記憶體晶片。
  6. 如申請專利範圍第3項之半導體堆疊封裝體，其中該第二半導體晶片包括一邏輯晶片。
  7. 如申請專利範圍第3項之半導體堆疊封裝體，進一步包括一覆蓋該第二半導體晶片之保護層。
  8. 如申請專利範圍第7項之半導體堆疊封裝體，其中該保護層覆蓋該第二半導體晶片之側壁及暴露相對於該中介層之該第二半導體晶片的上表面。
  9. 如申請專利範圍第3項之半導體堆疊封裝體，進一步包括一電連接至該第三貫穿電極之外部電極。
  10. 一種製造半導體堆疊封裝體之方法，該方法包括：垂直地堆疊複數個第一半導體晶片於一中介層之上表面上，以形成一半導體晶片堆；以及堆疊一第二半導體晶片於相對於該半導體晶片堆之該中介層的下表面上。
  11. 如申請專利範圍第10項之方法，進一步包括：形成一穿過該中介層之本體的第一貫穿電極，其中在該中介層之上表面上暴露該第一貫穿電極之一端，以構成一第一接觸部分，以及在該中介層之下表面上暴露該第一貫穿電極之另一端，以構成一 第二接觸部分。
  12. 如申請專利範圍第11項之方法，其中該半導體晶片堆係形成為包含有一穿過該複數個第一半導體晶片以使該等第一半導體晶片彼此電連接之第二貫穿電極，以及該第二貫穿電極電連接至該第一貫穿電極。
  13. 如申請專利範圍第11項之方法，其中該第二半導體晶片係形成為包含有一穿過該第二半導體晶片之本體的第二貫穿電極，以及該第二貫穿電極電連接至該第一貫穿電極。
  14. 如申請專利範圍第13項之方法，進一步包括附著一外部電極至該第二貫穿電極。
  15. 如申請專利範圍第10項之方法，其中該中介層係一包括矽材料之基板。
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