JP7042713B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7042713B2 JP7042713B2 JP2018132154A JP2018132154A JP7042713B2 JP 7042713 B2 JP7042713 B2 JP 7042713B2 JP 2018132154 A JP2018132154 A JP 2018132154A JP 2018132154 A JP2018132154 A JP 2018132154A JP 7042713 B2 JP7042713 B2 JP 7042713B2
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- 239000004065 semiconductor Substances 0.000 title claims description 77
- 239000000463 material Substances 0.000 claims description 161
- 125000006850 spacer group Chemical group 0.000 claims description 128
- 239000011347 resin Substances 0.000 claims description 123
- 229920005989 resin Polymers 0.000 claims description 123
- 239000000853 adhesive Substances 0.000 claims description 73
- 230000001070 adhesive effect Effects 0.000 claims description 73
- 239000000758 substrate Substances 0.000 claims description 64
- 229910052751 metal Inorganic materials 0.000 description 29
- 239000002184 metal Substances 0.000 description 29
- 101001139126 Homo sapiens Krueppel-like factor 6 Proteins 0.000 description 18
- 238000000034 method Methods 0.000 description 10
- 229920001187 thermosetting polymer Polymers 0.000 description 10
- 239000011521 glass Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000003822 epoxy resin Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000004048 modification Effects 0.000 description 6
- 238000012986 modification Methods 0.000 description 6
- 229920000647 polyepoxide Polymers 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 239000004593 Epoxy Substances 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 4
- 239000002313 adhesive film Substances 0.000 description 4
- 239000000945 filler Substances 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 239000005011 phenolic resin Substances 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 239000004925 Acrylic resin Substances 0.000 description 2
- 229920000178 Acrylic resin Polymers 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000009477 glass transition Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H—ELECTRICITY
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
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- H01L23/00—Details of semiconductor or other solid state devices
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-
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
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- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
- H01L2221/68331—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding of passive members, e.g. die mounting substrate
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
- H01L2221/68336—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding involving stretching of the auxiliary support post dicing
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
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- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H01L2224/4809—Loop shape
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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Description
図1は、第1実施形態に係る半導体装置1の構成の一例を示す断面図である。本実施形態の半導体装置1は、面実装型の半導体パッケージであり、例えば、BGA(Ball Grid Array package)、MAP(Mold Array Package)またはLGA(Land Grid Array Package)等でよい。半導体装置1は、例えば、NAND型フラッシュメモリ等の半導体記憶装置でもよい。
半導体装置1は、基板10と、接着材料20と、コントローラチップ30と、接着材料40と、スペーサチップ50と、接着材料60と、メモリチップ70と、モールド樹脂80と、金属バンプ90とを備える。
図3(A)の樹脂材料45を形成する際に、樹脂材料45の厚みを図3(B)に示す研磨後の厚みに形成すれば、図3(A)に示す樹脂材料45の形成工程は省略することができる。この場合、樹脂材料45は、半導体ウェハのような円形状の部材の上に、樹脂材料を塗布することによって形成すればよい。あるいは、変形例1の樹脂材料45も、図3(A)の樹脂材料45と同様に、金型等を用いて成形してよい。
樹脂材料45を形成する際に、樹脂材料45を接着材料40上に直接形成してもよい。例えば、シート状の接着材料40上に樹脂材料45を所望の厚みになるように塗布する。次に、接着材料40および樹脂材料45を半導体ウェハと同程度の大きさにカットする。これにより、図3(C)に示す接着材料40および樹脂材料45の積層体が形成される。
第1実施形態では、図3(C)に示すように樹脂材料45に接着材料40を貼付した後に、図3(D)および図3(E)に示すようにダイシングおよびエキスパンドを行っていた。
スリット46を有する樹脂材料45の裏面に接着材料40を貼付する。さらに、樹脂材料45および接着材料40にダイシングテープを貼付し、ダイシングテープ上で樹脂材料45および接着材料40をエキスパンドする。これにより、樹脂材料45および接着材料40は、スリット46に沿って劈開されスペーサチップ50に個片化される。スリット46は、樹脂材料45を金型で成形する際に同時に設ければよい。これにより、ダイシングブレードで樹脂材料45をダイシングすること無く、樹脂材料45をエキスパンド方式で個片化することができる。変形例3でも、第1実施形態と同様のスペーサチップ50を形成することができる。
第1実施形態では、スペーサチップ50の樹脂材料(第1樹脂材料)は、モールド樹脂80と同一の樹脂材料である。しかし、スペーサチップ50は、モールド樹脂80と類似する樹脂材料、あるいは、基板10の絶縁層16と同一または類似する樹脂材料であってもよい。例えば、スペーサチップ50の樹脂材料は、エポキシ樹脂を主成分とし、フェノール樹脂、アクリル樹脂、シリカフィラー、酸化チタンフィラー、ガラスクロスが含まれた材料でもよい。例えば、エポキシ材にガラスクロスを含めると、スペーサチップ50の樹脂材料は、ガラスエポキシ樹脂となる。このようにスペーサチップ50は、モールド樹脂80と類似する樹脂材料、あるいは、基板10の絶縁層16と同一または類似する樹脂材料であっても、モールド樹脂80との密着性が向上し、半導体装置の信頼性を高めることができる。尚、スペーサチップ50をガラスエポキシ基板とした場合、ガラスエポキシ基板の表面および/または裏面に銅箔、あるいは、ソルダレジストが設けられていてもよい。また、ガラスエポキシ基板の表面および/または裏面には、半導体装置の識別マークをエッチングで表示(刻印)してもよい。
図5は、第2実施形態に係る半導体装置2の構成の一例を示す断面図である。半導体装置2は、支柱51、53をさらに備えている。第1支柱としての支柱51は、スペーサチップ50と基板10との間に設けられている。支柱51は、スペーサチップ50の端部が基板10へ向かって落ち込まないようにスペーサチップ50を支持する支柱として機能する。第2支柱としての支柱53は、スペーサチップ50とコントローラチップ30との間に設けられている。支柱53は、スペーサチップ50の中央部が基板10へ向かって落ち込まないようにスペーサチップ50を支持する支柱として機能する。支柱51、53は、スペーサチップ50と同一の樹脂材料(第1樹脂材料)からなる。これにより、支柱51、53とモールド樹脂80との密着性が向上し、支柱51、53とモールド樹脂80との間の剥離が抑制され得る。
図7は、第3実施形態に係る半導体装置3の構成の一例を示す断面図である。第3実施形態による半導体装置3は、スペーサチップ50上に互いに隣接配置された第1および第2積層体ST1、ST2を備えている。第1積層体ST1は、スペーサチップ50上に積層された複数のメモリチップ70からなる。第2積層体ST2は、スペーサチップ50上に第1積層体ST1に隣接して積層された複数のメモリチップ70からなる。即ち、第3実施形態では、メモリチップ70をツインタワー状に積層している。
図8は、第4実施形態に係る半導体装置4の構成の一例を示す断面図である。第4実施形態では、コントローラチップに代えて複数のメモリチップ70がスペーサチップ50の下に積層されている。また、メモリチップ70はスペーサチップ50上にも積層されている。
図9は、第5実施形態に係る半導体装置5の構成の一例を示す断面図である。第5実施形態は、第2積層体ST12の上に、緩衝材95が設けられている点で第4実施形態と異なる。
図10は、第6実施形態に係る半導体装置6の構成の一例を示す断面図である。第6実施形態は、スペーサチップ50が2つに分離されており、コントローラチップ30の両側の基板10上方に配置されている。それに伴い、接着材料40も2つに分離されており、コントローラチップ30の両側に配置されている。即ち、基板10の実装面の上方から見たときに、接着材料40およびスペーサチップ50は、コントローラチップ30の外側の2つの基板領域上に設けられている。接着材料40は、それぞれスペーサチップ50と基板10との間に設けられ、それらの間を接着し、スペーサチップ50を支持している。また、接着材料40は、コントローラチップ30上には設けられていないものの、金属ワイヤ35の一部分を被覆している。
Claims (3)
- 基板と、
前記基板上に設けられた第1半導体チップと、
前記第1半導体チップの上方に設けられた第2半導体チップと、
前記基板の実装面と直交する方向に関し、前記第1半導体チップと前記第2半導体チップの間に設けられ第1樹脂材料からなるスペーサチップと、
前記スペーサチップと前記基板または前記第1半導体チップとの間に設けられた第1接着材料と、
前記スペーサチップと前記第2半導体チップの間に設けられた第2接着材料と、
前記第1および第2半導体チップ、並びに、前記スペーサチップを被覆する第2樹脂材料と、
前記スペーサチップと前記基板との間に設けられ、前記第1樹脂材料からなる複数の第1支柱とを備えた半導体装置。 - 基板と、
前記基板上に設けられた第1半導体チップと、
前記第1半導体チップ上に設けられた第1接着材料と、
前記第1接着材料上に設けられ第1樹脂材料からなるスペーサチップと、
前記スペーサチップ上に設けられた第2接着材料と、
前記第2接着材料上に設けられた第2半導体チップと、
前記第1および第2半導体チップ、並びに、前記スペーサチップを被覆する第2樹脂材料と、
前記スペーサチップと前記基板との間に設けられ、前記第1樹脂材料からなる複数の第1支柱とを備えた半導体装置。 - 前記第1樹脂材料は、前記第2樹脂材料と同一材料である、請求項1または請求項2に記載の半導体装置。
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US16/247,616 US10756060B2 (en) | 2018-07-12 | 2019-01-15 | Semiconductor device |
TW108105866A TWI757587B (zh) | 2018-07-12 | 2019-02-21 | 半導體裝置 |
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US11699685B2 (en) * | 2021-07-14 | 2023-07-11 | Western Digital Technologies, Inc. | Non-cure and cure hybrid film-on-die for embedded controller die |
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US20200020669A1 (en) | 2020-01-16 |
US10756060B2 (en) | 2020-08-25 |
TW202006907A (zh) | 2020-02-01 |
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