JP4652428B2 - 半導体装置およびその製造方法 - Google Patents
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- JP4652428B2 JP4652428B2 JP2008113107A JP2008113107A JP4652428B2 JP 4652428 B2 JP4652428 B2 JP 4652428B2 JP 2008113107 A JP2008113107 A JP 2008113107A JP 2008113107 A JP2008113107 A JP 2008113107A JP 4652428 B2 JP4652428 B2 JP 4652428B2
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- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
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- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Description
また、複数個分の半導体装置に対応したフレーム状の回路基板とフレーム状の接続用回路基板を用いて、複数個分の半導体装置を同時に形成し、最後に半導体装置各個片に切り出す工程によって半導体装置を製造する方法では、樹脂封止する際の金型が必要なく、任意のサイズの半導体装置の製造に対応でき、コスト低減を図ることができる。
尚、以下に示す各実施の形態は、本発明を具体化した例示であって、本発明の技術的範囲を限定するものではない。
本発明の実施の形態1に係る半導体装置の構成を図1に示す。
本発明の実施の形態2に係る半導体装置の構成を図5に示す。
本発明の実施の形態3に係る半導体装置の構成を図7に示す。図7に示す半導体装置は、上記実施の形態1または2で説明したような半導体装置を複数個積層した積層体とし、この積層体自体を一つの半導体装置とした構成例である。
本発明に係る半導体装置の製造方法を、図8(a)〜(d)を参照して以下に説明する。尚、図8(a)〜(d)では、図3に示す構造の半導体装置を製造する場合を例示する。
11 半導体素子
12 回路基板
14 ワイヤ
15 接続用回路基板
17 外部端子接続部
18 導電体端子
19 封止樹脂
20 外部接続端子
21 導電体端子(核を有する導電体端子)
22,23 半導体素子
25 導電体端子
Claims (7)
- 回路基板上に少なくとも一つの半導体素子を載置してなる半導体装置において、
最上層にある上記半導体素子の上面に、外部端子接続部を備えた接続用回路基板が接着剤を介して載置され、
上記最上層にある半導体素子と上記回路基板とはワイヤを介して接続されており、
上記ワイヤの一部は、上記接着剤に覆われており、
上記接続用回路基板の下面と上記回路基板の上面とが導電体端子にて接続され、
上記回路基板と上記接続用回路基板との間は、封止樹脂によって封止されていることを特徴とする半導体装置。 - 上記導電体端子は、核の外側に導電層を有する端子であることを特徴とする請求項1に記載の半導体装置。
- 上記導電体端子は、半導体装置の厚さ方向に複数個の略球形形状の導電体端子を積層してなることを特徴とする請求項1に記載の半導体装置。
- 上記回路基板上に複数の半導体素子を有し、
下段にある半導体素子の上面に、上段にある半導体素子が接着剤を介して載置され、上記下段にある半導体素子と上記回路基板とはワイヤを介して接続されており、当該ワイヤの一部は当該接着剤に覆われていることを特徴とする請求項1に記載の半導体装置。 - 上記請求項1ないし4の何れかに記載の半導体装置上に、他の半導体装置もしくは他の電子部品が積層配置され、
上記半導体装置の上記外部端子接続部と、その上段の他の半導体装置もしくは他の電子部品とが導電体によって接続されていることを特徴とする半導体装置の積層体。 - 回路基板上に半導体素子を載置し、該半導体素子と該回路基板とをワイヤを介して電気的に接続する工程と、
上記回路基板上に導電体端子を載置する工程と、
外部端子接続部を備えた接続用回路基板を、上記半導体素子上に接着剤を介して載置し、当該接着剤により上記ワイヤの一部を覆うと共に、上記接続用回路基板の下面と上記回路基板上に載置された導電体端子とを接続する工程と、
上記回路基板と上記接続用回路基板との間を樹脂封止する工程と、
上記回路基板の下面に外部接続端子を載置する工程を有することを特徴とする半導体装置の製造方法。 - 複数個分の半導体装置に対応する回路基板上に半導体素子を載置し、該半導体素子と該回路基板とをワイヤを介して電気的に接続する工程と、
上記回路基板上に導電体端子を載置する工程と、
外部端子接続部を備えた複数個分の半導体装置に対応する接続用回路基板を、上記半導体素子上に接着剤を介して載置し、当該接着剤により上記ワイヤの一部を覆うと共に、上記接続用回路基板の下面と上記回路基板上に載置された導電体端子とを接続する工程と、
上記回路基板と上記接続用回路基板との間を樹脂封止する工程と、
上記回路基板の下面に外部接続端子を載置する工程と、
上記複数個分がつながった半導体装置から個別の半導体装置を切り出す工程を有することを特徴とする半導体装置の製造方法。
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JP2008113107A JP4652428B2 (ja) | 2008-04-23 | 2008-04-23 | 半導体装置およびその製造方法 |
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JP4652428B2 true JP4652428B2 (ja) | 2011-03-16 |
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JP2016529703A (ja) * | 2013-07-15 | 2016-09-23 | インヴェンサス・コーポレイション | 封止を貫いて延在する接続子によって結合された積重端子を有する超小型電子組立体 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2000294720A (ja) * | 1999-04-07 | 2000-10-20 | Sharp Corp | 半導体集積回路パッケージ |
JP2003218283A (ja) * | 2002-01-22 | 2003-07-31 | Sharp Corp | 半導体装置およびその製造方法 |
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JP2000294720A (ja) * | 1999-04-07 | 2000-10-20 | Sharp Corp | 半導体集積回路パッケージ |
JP2003218283A (ja) * | 2002-01-22 | 2003-07-31 | Sharp Corp | 半導体装置およびその製造方法 |
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