TWI724744B - 半導體裝置及半導體裝置之製造方法 - Google Patents

半導體裝置及半導體裝置之製造方法 Download PDF

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TWI724744B
TWI724744B TW109100861A TW109100861A TWI724744B TW I724744 B TWI724744 B TW I724744B TW 109100861 A TW109100861 A TW 109100861A TW 109100861 A TW109100861 A TW 109100861A TW I724744 B TWI724744 B TW I724744B
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TW202114083A (zh
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三浦正幸
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日商鎧俠股份有限公司
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Abstract

根據一實施形態，於半導體裝置中，基板具有主面。控制晶片具有第1正面及第1背面。控制晶片於第1正面與主面對面之狀態下介隔複數個凸塊電極安裝於主面。第1間隔片具有第2正面及第2背面。第1間隔片之第2背面安裝於主面。第1間隔片之第2正面距主面之高度為第1背面距主面之高度之上限與下限之間的範圍內。第2間隔片具有第3正面及第3背面。第2間隔片之第3背面安裝於主面。第2間隔片之第3正面距主面之高度為第1背面距主面之高度之上限與下限之間的範圍內。

Description

半導體裝置及半導體裝置之製造方法
本實施形態係關於一種半導體裝置及半導體裝置之製造方法。
於半導體裝置中，於基板之主面安裝半導體晶片及間隔片，於間隔片之上安裝其它複數個半導體晶片而構成間隔片構造之安裝形態。此時，較理想為適當地構成間隔片構造之安裝形態。
一實施形態之目的在於提供一種能夠適當地構成間隔片構造之安裝形態之半導體裝置及半導體裝置之製造方法。
根據一實施形態，提供一種具有基板、控制晶片、第1間隔片及第2間隔片之半導體裝置。基板具有主面。控制晶片具有第1正面及第1背面。控制晶片於第1正面與主面對面之狀態下介隔複數個凸塊電極安裝於主面。第1間隔片具有第2正面及第2背面。第1間隔片之第2背面安裝於主面。第1間隔片之第2正面距主面之高度為第1背面距主面之高度之上限與下限之間的範圍內。第2間隔片具有第3正面及第3背面。第2間隔片之第3背面安裝於主面。第2間隔片之第3正面距主面之高度為第1背面距主面之高度之上限與下限之間的範圍內。
以下，參照附圖詳細地對實施形態之半導體裝置進行說明。再者，本發明並不受該些實施形態限定。
(第1實施形態) 第1實施形態之半導體裝置為了滿足SIP(System In Package，系統級封裝)之要求，存在採用混載有控制晶片及複數個記憶體晶片之多晶片模組構成之情形。於多晶片模組構成中，控制晶片根據高速化、低耗電化之要求而將晶片面積抑製得較小，相對於此，記憶體晶片根據大容量化之要求而傾向於增大晶片面積。於半導體裝置中，根據小型安裝化之要求，可採用如下間隔片構造，即，以間隔片填埋控制晶片及記憶體晶片間之面積差，並且將複數個晶片上下重疊而積層配置。
例如，於基板之面積最大之面(主面)以引線接合方式面朝上安裝控制晶片，並且於其周邊安裝複數個間隔片，複數個記憶體晶片經由接著膜積層於控制晶片及間隔片之上，並以引線接合方式面朝上安裝於基板。將該間隔片構造稱為面朝上安裝+面朝上安裝之間隔片構造。
於面朝上安裝+面朝上安裝之間隔片構造中，需要於控制晶片與最下之記憶體晶片之間確保用於控制晶片之接合線之間隙空間。因此，從用來安裝規定片數之記憶體晶片之基板至最上之記憶體晶片的安裝高度容易變高。
或者，於基板之主面以覆晶方式面朝下安裝控制晶片，並且於其周邊安裝複數個間隔片，複數個記憶體晶片經由接著膜積層於控制晶片及間隔片之上，並以引線接合方式面朝上安裝於基板。將該間隔片構造稱為面朝下安裝+面朝上安裝之間隔片構造。
於面朝下安裝+面朝上安裝之間隔片構造中，於控制晶片與最下之記憶體晶片之間不需要用於控制晶片之接合線之間隙空間。因此，面朝下安裝+面朝上安裝之間隔片構造與面朝上安裝+面朝上安裝之間隔片構造相比，能夠降低從用來安裝規定片數之記憶體晶片之基板至最上之記憶體晶片的安裝高度。
於面朝下安裝+面朝上安裝之間隔片構造之半導體裝置中，若根據進一步小型安裝化之要求而將控制晶片薄型化，則存在控制晶片受安裝時之熱變形等影響而彎曲之情形。此時，若基板上之控制晶片之背面與間隔片之正面之高度差較大，則為了吸收該高度差而應積層於其之上之接著膜大幅變厚，從基板至最上之記憶體晶片的安裝高度有變高之可能性。
於此，本實施形態中，於面朝下安裝+面朝上安裝之間隔片構造之半導體裝置中，藉由將各間隔片距基板之主面之高度構成為控制晶片之高度之上限與下限之間的範圍內，而實現接著膜之薄膜化及由此帶來之安裝高度之降低。
具體而言，半導體裝置1可如圖1所示般構成。圖1係表示半導體裝置1之構成之圖。
半導體裝置1具有基板10、控制晶片20、複數個記憶體晶片40-1～40-8、密封樹脂50、外部電極60、複數個間隔片70-1～70-2、及複數個接著膜30-1～30-10。以下，將垂直於基板10之面積最大之面中之一個(正面10a、第1主面)之方向設為Z方向，將於垂直於Z方向之平面內相互正交之2個方向設為X方向及Y方向。
於半導體裝置1中，於基板10之上依次積層控制晶片20及複數個記憶體晶片40-1～40-8，於複數個記憶體晶片40-1～40-8中之最下之記憶體晶片40-1與基板10之間之控制晶片20之側方配置複數個間隔片70-1～70-2。控制晶片20以面朝下狀態覆晶安裝於基板10，複數個記憶體晶片40-1～40-8以面朝上狀態引線接合安裝於基板10。由此，構成面朝下安裝+面朝上安裝之間隔片構造。
基板10於+Z側具有正面(主面)10a，於-Z側具有背面10b。於基板10之正面10a分別安裝有控制晶片20、複數個間隔片70-1～70-2、複數個記憶體晶片40-1～40-8、及複數個接著膜30-1～30-10，於基板10之背面10b安裝有外部電極60。安裝於基板10之正面10a側之控制晶片20、複數個間隔片70-1～70-2、複數個記憶體晶片40-1～40-8、及複數個接著膜30-1～30-10利用密封樹脂50密封。密封樹脂50由以絕緣物為主成分之材料形成，例如可由以具有絕緣性、熱塑性之第1樹脂為主成分之材料形成。安裝於基板10之背面10b側之外部電極60可由以導電物為主成分之材料形成，並且其表面露出，可從外部電連接。
基板10具有阻焊劑層11、預浸料層12、核心層13、導電層14、及通孔電極15。阻焊劑層11可由以絕緣物(例如，絕緣性有機系物質)為主成分之材料形成。預浸料層12可由以絕緣物(例如，絕緣性樹脂)為主成分之材料形成。核心層13可由以絕緣物(例如，絕緣性樹脂)為主成分之材料形成。導電層14可由以導電物(例如，銅)為主成分之材料形成。通孔電極15可由以導電物(例如，銅)為主成分之材料形成。
控制晶片20於-Z側具有正面20a，於+Z側具有背面20b。控制晶片20能夠以覆晶方式安裝於基板10。控制晶片20之正面20a與基板10之正面10a對面。控制晶片20介隔複數個凸塊電極21以面朝下方式(覆晶方式)安裝於基板10之正面10a。即，控制晶片20於正面20a與基板10之正面10a對面之狀態下介隔複數個凸塊電極21安裝於基板10之正面10a。隔於控制晶片20及基板10間之空間中之複數個凸塊電極21之間之間隙由接著樹脂(底部填充膠)22填滿。
控制晶片20主要由以半導體(例如，矽)為主成分之材料形成。凸塊電極21由以金屬(例如，銅)為主成分之材料形成。接著樹脂22由以絕緣物為主成分之材料形成，例如可由以具有絕緣性、接著性之第2樹脂為主成分之材料(例如，以環氧樹脂為主成分之材料)形成。
例如，如圖2、圖3所示，控制晶片20之背面20b由於安裝時之熱變形等影響而以向+Z側凸出之方式彎曲。圖2、圖3係表示間隔片70及控制晶片20之高度之放大剖面圖。關於控制晶片20之背面20b距基板10之正面10a之高度，具有上限高度H20b_max及下限高度H20b_min。背面20b於Y方向之中央附近之部位具有上限高度H20b_max，於+Y側之端部及-Y側之端部具有下限高度H20b_min。
再者，於圖2、圖3中，例示基板10平坦之情形，但於基板10自身因安裝時之熱變形等影響而彎曲之情形時，距基板10之正面10a之高度之基準可採用正面10a之安裝控制晶片20之部位之Z位置。
圖1所示之接著膜30-1覆蓋基板10之正面10a，供積層間隔片70-1。接著膜30-1配置於控制晶片20之周邊，例如配置於控制晶片20之-Y側。接著膜30-1作為將間隔片70-1接著於基板10之正面10a之媒介。接著膜30-1亦稱為DAF(Die Attach Film，晶片接著膜)或DBF(Die Bonding Film，晶片接合膜)。
間隔片70-1具有正面70a及背面70b。間隔片70-1之背面70b經由接著膜30-1安裝於基板10之正面10a，經由接著膜30-3於正面70a積層記憶體晶片40-1。間隔片70-1可由具有足以經由接著膜30-3將記憶體晶片40-1支持於基板10之+Z側之強度之材料形成。間隔片70-1可由以半導體(例如，矽)為主成分之材料形成，亦可由以樹脂(例如，聚醯亞胺樹脂)為主成分之材料形成。
例如，如圖2所示，間隔片70-1之正面70a距基板10之正面10a之高度H70a1為上限高度H20b_max與下限高度H20b_min之間的範圍內。由此，間隔片70-1之高度可視作與控制晶片20之高度大致一致。
圖1所示之接著膜30-2覆蓋基板10之正面10a，供積層間隔片70-2。接著膜30-2配置於控制晶片20之周邊，例如配置於控制晶片20之+Y側。接著膜30-2作為將間隔片70-2接著於基板10之正面10a之媒介。接著膜30-2亦稱為DAF(Die Attach Film)或DBF(Die Bonding Film)。
間隔片70-2具有正面70a及背面70b。間隔片70-2之背面70b經由接著膜30-2安裝於基板10之正面10a，經由接著膜30-2於正面70a積層記憶體晶片40-1。間隔片70-2可由具有足以經由接著膜30-3將記憶體晶片40-1支持於基板10之+Z側之強度之材料形成。間隔片70-2可由以半導體(例如，矽)為主成分之材料形成，亦可由以樹脂(例如，聚醯亞胺樹脂)為主成分之材料形成。
例如，如圖3所示，間隔片70-2之正面70a距基板10之正面10a之高度H70a2為上限高度H20b_max與下限高度H20b_min之間的範圍內。由此，間隔片70-2之高度可視作與控制晶片20之高度大致一致。間隔片70-2之高度亦可與間隔片70-1之高度均等。
圖1所示之接著膜30-3覆蓋控制晶片20之背面20b，覆蓋間隔片70-1之正面70a，覆蓋間隔片70-2之正面70a，供積層記憶體晶片40-1。接著膜30-3配置於控制晶片20及複數個間隔片70-1、70-2與記憶體晶片40-1之間。接著膜30-3將記憶體晶片40-1接著於控制晶片20及複數個間隔片70-1、70-2，亦稱為DAF(Die Attach Film)或DBF(Die Bonding Film)。
例如，如圖2、圖3所示，間隔片70-1之高度可視作與控制晶片20之高度大致一致，間隔片70-2之高度可視作與控制晶片20之高度大致一致，因此，可容易地使接著膜30-3之厚度變薄。例如，接著膜30-3之厚度亦可為控制晶片20之上限高度H20b_max與下限高度H20b_min之差(ΔH20b＝H20b_max－H20b_min)加上特定之厚度裕度而得之尺寸。
複數個記憶體晶片40-1～40-8積層於控制晶片20及複數個間隔片70-1、70-2之+Z側。記憶體晶片40-1～40-8跨及控制晶片20及至少1個間隔片70而配置。於圖1中，例示記憶體晶片40-1～40-8跨及控制晶片20及2個間隔片70而配置之構成。於複數個記憶體晶片40-1～40-8之間介置接著膜30-4～30-10，經由接著膜30-4～30-10相互接著。
各記憶體晶片40-1～40-8具有正面及背面。各記憶體晶片40-1～40-8中，背面接著於接著膜30，於正面配置有電極墊。各記憶體晶片40-1～40-8主要由以半導體(例如，矽)為主成分之材料形成。
複數個記憶體晶片40-1～40-8可分別以引線接合方式安裝於基板10。此時，基板10中之導電層14於正面(+Z側之主面)10a上具有複數個電極圖案，各記憶體晶片40-1～40-8之電極墊可經由接合線41電連接於基板10之正面上之電極圖案。由此，複數個記憶體晶片40-1～40-8可藉由引線接合方式以間隔片構造安裝於基板10。
於半導體裝置1中，比較各接著膜30-1～30-10之厚度，如圖1所示，接著膜30-3之厚度與接著膜30-1及接著膜30-2之厚度相同或較其稍厚。接著膜30-3之厚度與接著膜30-4～30-10之厚度相同或較其稍厚。即，若能夠將接著膜30-3之厚度薄膜化至與複數個記憶體晶片40-1～40-8間之各接著膜30-4～30-10之厚度相同之程度，則能夠容易地降低半導體裝置1之安裝高度。
再者，各接著膜30-1～30-10由以絕緣物為主成分之材料形成，例如可由以具有絕緣性、接著性之第3樹脂為主成分之材料(例如，包含丙烯酸聚合物及環氧樹脂之材料)形成。
如上所述，第1實施形態中，於面朝下安裝+面朝上安裝之間隔片構造之半導體裝置1中，將各間隔片70-1、70-2距基板10之正面10a之高度構成為控制晶片20之高度之上限與下限之間的範圍內。由此，能夠容易地將接著膜30-3薄膜化，因此，能夠容易地降低半導體裝置1之安裝高度。
再者，控制晶片20亦可以向-Z側凸出之方式彎曲。即便於此情形時，藉由將各間隔片70-1、70-2距基板10之正面10a之高度構成為控制晶片20之高度之上限與下限之間的範圍內，能夠實現與實施形態相同之效果。
或者，於半導體裝置1i中，複數個間隔片70i-1、70i-2亦可如圖4所示般佈局。圖4係表示第1實施形態之第1變化例中之間隔片70i-1、70i-2及控制晶片20i之佈局構成之俯視圖。
控制晶片20i於XY俯視下配置於包含基板10之正面10a之中心之區域。間隔片70i-1、70i-2之面積相互均等。間隔片70i-1配置於控制晶片20i之-X側。間隔片70i-2配置於控制晶片20i之+X側。
此時，如圖5所示，複數個記憶體晶片40i-1、40i-2亦可經由接著膜30i-3、30i-4積層於間隔片70i-1及控制晶片20i之+Z側。複數個記憶體晶片40i-3、40i-4亦可經由接著膜30i-5、30i-6積層於間隔片70i-2及控制晶片20i之+Z側。圖5係表示第1實施形態之第1變化例中之間隔片70i-1、70i-2、控制晶片20i及記憶體晶片40i-1～40i-4之積層構成之剖面圖，表示相當於沿著圖4之A-A線切斷之情形之剖面。圖5中，為了簡略化，省略接合線之圖示。
間隔片70i-1可由具有足以經由接著膜30i-3支持記憶體晶片40i-1之強度之材料形成。間隔片70i-1可由以半導體(例如，矽)為主成分之材料形成，亦可由以樹脂(例如，聚醯亞胺樹脂)為主成分之材料形成。間隔片70i-2可由具有足以經由接著膜30i-5支持記憶體晶片40i-3之強度之材料形成。間隔片70i-2可由以半導體(例如，矽)為主成分之材料形成，亦可由以樹脂(例如，聚醯亞胺樹脂)為主成分之材料形成。
各記憶體晶片40i-1～40i-4經由接合線電連接於圖4所示之基板10之正面10a上之複數個電極圖案101-1～101-2k(k為任意之2以上之整數)。於XY俯視下，間隔片70i-1配置於複數個電極圖案101-1～101-k與控制晶片20i之間。間隔片70i-2配置於複數個電極圖案101-(k+1)～101-2k與控制晶片20i之間。
控制晶片20i例如具有矩形之外形，具有4邊20i1～20i4。邊20i1於Y方向上延伸，相對於邊20i2於X方向上隔開並且相向，於±Y方向之兩端與邊20i3、20i4交叉。邊20i2於Y方向上延伸，相對於邊20i1於X方向上隔開並且相向，於±Y方向之兩端與邊20i3、20i4交叉。邊20i3於X方向上延伸，相對於邊20i4於Y方向上隔開並且相向，於±X方向之兩端與邊20i2、20i1交叉。邊20i4於X方向上延伸，相對於邊20i3於Y方向上隔開並且相向，於±X方向之兩端與邊20i2、20i1交叉。
間隔片70i-1以與邊20i1並排之方式配置。間隔片70i-1具有以沿著Y方向之方向為長邊方向之矩形之外形，沿著邊20i1延伸。間隔片70i-2以與邊20i2並排之方式配置。間隔片70i-2具有以沿著Y方向之方向為長邊方向之矩形之外形，沿著邊20i2延伸。間隔片70i-1及間隔片70i-2之外形尺寸亦可相互均等。可將間隔片70i-1及間隔片70i-2之面積設為相互均等。
如此，於半導體裝置1i中，由於能夠將間隔片70i-1及間隔片70i-2之面積設為相互均等，因此能夠提高間隔片70i-1及間隔片70i-2之材料(例如，矽等半導體)之使用效率。
又，藉由將間隔片70i-1及間隔片70i-2之外形尺寸設為相互均等，能夠減少間隔片70i-1及間隔片70i-2之厚度之不均，就該觀點而言，由於能夠將接著膜30i-3、30i-5之厚度薄膜化，因此能夠容易地降低半導體裝置1i之安裝高度。
或者，於半導體裝置1j中，複數個間隔片70j-1～70j-4亦可如圖6所示般佈局。圖6係表示第1實施形態之第2變化例中之間隔片70j-1～70j-4及控制晶片20i之佈局構成之俯視圖。
複數個間隔片70j-1～70j-4之面積相互均等。複數個間隔片70j-1～70j-4之外形尺寸亦可相互均等。間隔片70j-1及間隔片70j-3配置於控制晶片20i之-X側。間隔片70j-2及間隔片70j-4配置於控制晶片20i之+X側。
間隔片70j-1及間隔片70j-3係將間隔片70i-1(參照圖4)之Y方向之中央附近之部分去除而進行2分割所得。由於在Y方向上之間隔片70j-1及間隔片70j-3之間存在間隙之空間，因此，於製造半導體裝置1j時，能夠容易地經由該間隙將密封樹脂50填滿間隔片70j-1及間隔片70j-3與控制晶片20i之間之空間。
間隔片70j-2及間隔片70j-4係將間隔片70i-2(參照圖4)之Y方向之中央附近之部分去除而進行2分割所得。由於在Y方向之間隔片70j-2及間隔片70j-4之間存在間隙之空間，因此，於製造半導體裝置1j時，能夠容易地經由該間隙將密封樹脂50填滿間隔片70j-1及間隔片70j-3與控制晶片20i之間之空間。
此時，間隔片70j-1～70j-4、控制晶片20i及記憶體晶片40i-1～40i-4之積層構成亦可與圖5相同。
如此，於半導體裝置1j中，由於能夠將間隔片70j-1～70j-4之面積設為相互均等，因此能夠提高間隔片70j-1～70j-4之材料之使用效率。
又，藉由將間隔片70j-1～70j-4之外形尺寸設為相互均等，能夠減少間隔片70j-1～70j-4之厚度之不均，就該觀點而言，由於能夠將接著膜30i-3、30i-5之厚度薄膜化，因此能夠容易地降低半導體裝置1j之安裝高度。
或者，於半導體裝置1k中，複數個間隔片70k-1～70k-5亦可如圖7所示般佈局。圖7係表示第1實施形態之第3變化例中之間隔片70k-1～70k-5及控制晶片20i之佈局構成之俯視圖。
控制晶片20i於XY俯視下配置於包含基板10之正面10a之中心之區域。間隔片70k-1～70k-5之面積相互均等。間隔片70k-1配置於控制晶片20i之-X側。間隔片70k-2配置於控制晶片20i之+X側。間隔片70k-3配置於控制晶片20i之+X側，並配置於間隔片70k-2之+Y側。間隔片70k-4配置於控制晶片20i之-Y側。間隔片70k-5配置於控制晶片20i之+Y側。
此時，如圖8所示，複數個記憶體晶片40k-1～40k-4亦可經由接著膜30k-6～30k-9積層於間隔片70k-1～70k-5及控制晶片20i之+Z側。再者，各間隔片70k-1～70k-5經由接著膜30k-1～30k-5配置於基板這一點與實施形態相同。圖8係表示第1實施形態之第3變化例中之間隔片70k-1～70k-5、控制晶片20i及記憶體晶片40k-1～40k-4之積層構成之剖面圖，表示相當於沿著圖7之B-B線切斷之情形之剖面。圖8中，為了簡略化，省略接合線之圖示。
各間隔片70k-1～70k-5可由具有足以經由接著膜30k-6支持記憶體晶片40k-1之強度之材料形成。各間隔片70k-1～70k-5可由以半導體(例如，矽)為主成分之材料形成，亦可由以樹脂(例如，聚醯亞胺樹脂)為主成分之材料形成。
各記憶體晶片40k-1～40k-4經由接合線電連接於圖7所示之基板10之正面10a上之複數個電極圖案101-1～101-2k(k為任意之2以上之整數)。於XY俯視下，間隔片70k-1配置於複數個電極圖案101-1～101-k與控制晶片20i之間。間隔片70k-2、70k-3分別配置於複數個電極圖案101-(k+1)～101-2k與控制晶片20i之間。間隔片70k-4於控制晶片20i之-Y側配置於複數個電極圖案101-1～101-k與複數個電極圖案101-(k+1)～101-2k之間。間隔片70k-5於控制晶片20i之+Y側配置於複數個電極圖案101-1～101-k與複數個電極圖案101-(k+1)～101-2k之間。
間隔片70k-1以與控制晶片20i之邊20i1並排之方式配置。間隔片70k-1具有以沿著Y方向之方向為長邊方向之矩形之外形，沿著邊20i1延伸。間隔片70k-2、70k-3分別以與邊20i2並排之方式配置。間隔片70k-2、70k-3具有以沿著Y方向之方向為長邊方向之矩形之外形，沿著邊20i2延伸。間隔片70k-4以與邊20i4並排之方式配置。間隔片70k-4具有以沿著X方向之方向為長邊方向之矩形之外形，沿著邊20i4延伸。間隔片70k-5以與邊20i3並排之方式配置。間隔片70k-5具有以沿著X方向之方向為長邊方向之矩形之外形，沿著邊20i3延伸。
間隔片70k-1～70k-5之外形尺寸亦可相互均等。可將間隔片70k-1～70k-5之面積設為相互均等。
如此，於半導體裝置1k中，由於能夠將間隔片70k-1～70k-5之面積設為相互均等，因此能夠提高間隔片70k-1～70k-5之材料(例如，矽等半導體)之使用效率。
又，藉由將間隔片70k-1～70k-5之外形尺寸設為相互均等，能夠減少間隔片70k-1～70k-5之厚度之不均，就該觀點而言，由於能夠將接著膜30k-6之厚度薄膜化，因此能夠容易地降低半導體裝置1k之安裝高度。
或者，於半導體裝置1n中，如圖9所示，亦可於控制晶片20n之背面20bn配置間隔片90n。圖9係表示第1實施形態之第4變化例中之間隔片70i-1、70i-2、90n、控制晶片20n及記憶體晶片40i-1～40i-4之積層構成之剖面圖，表示相當於沿著圖4之A-A線切斷之情形之剖面。圖9中，為了簡略化，省略接合線之圖示。間隔片90n由能夠減小控制晶片20n之背面20bn與密封樹脂50之熱膨脹率差之材料(例如，具有半導體與第1樹脂之中間熱膨脹率之材料、或能夠減小因熱膨脹率差而產生之應力之材料)形成，例如可由以聚醯亞胺樹脂為主成分之材料形成。間隔片90n與控制晶片20n之背面20bn藉由未圖示之接著膜而接著。複數個記憶體晶片40i-1、40i-2經由接著膜30i-3、30i-4積層於間隔片70i-1及間隔片90n之+Z側。
於半導體裝置1n之製造步驟中，間隔片90n貼附於包含單片化前之控制晶片20n之晶圓，其後，間隔片90n及控制晶片20n作為一體進行單片化，其後，間隔片90n及控制晶片20n作為一體安裝於基板10。因此，作為圖2、圖3所示之下限高度H20b_min、上限高度H20b_max，可設為間隔片90n及控制晶片20n成為一體之構件之+Z側之面(即，間隔片90n之+Z側之面)之高度。
於圖5之構成中，控制晶片20i之背面20bi與密封樹脂50之密接力較小，存在密封後密封樹脂50從背面20bi剝離之可能性。
相對於此，於圖9之構成中，能夠經由間隔片90n提高控制晶片20n之背面20bn與密封樹脂50之密接性，能夠抑制密封後密封樹脂50從背面20bi側(間隔片90n之+Z側之面)剝離。
(第2實施形態) 對第2實施形態之半導體裝置進行說明。以下，以與第1實施形態不同之部分為中心進行說明。
於第1實施形態中，半導體裝置1之製造方法無特別限定。
例如，於製造半導體裝置1時，介隔複數個凸塊電極將控制晶片20安裝(mount)於基板10，並且於將底部填充膠填充至複數個凸塊電極之間隙後安裝(mount)間隔片70。
於安裝控制晶片20時，於填充接著樹脂22後，接著樹脂22之熔融片(Bleed)有時於控制晶片20之周圍流出。其後，若於熔融片(Bleed)上安裝間隔片70，則有間隔片70向基板10之密接性劣化而剝離之擔憂。當間隔片70剝離時，由此會導致對其它晶片施加應力等，因而存在如下可能性，即，記憶體晶片之電極墊與基板上之電極圖案之間之接合線之電連接路徑中之任一者因斷線及/或剝離等被阻斷等，產生電連接不良。
又，根據熔融片(Bleed)之厚度，高度方向之不均可能增大。即，基板10上之控制晶片20之上表面與間隔片70之上表面之高度差變大，為了吸收該高度差而應積層於其上之接著膜30大幅變厚，從基板10至最上之記憶體晶片40之安裝高度有變高之可能性。
於此，於第2實施形態中，如圖10所示，於半導體裝置1之製造方法中，藉由於基板10上安裝間隔片70後安裝控制晶片20，抑制接著樹脂22之熔融片(Bleed)介置於間隔片70與基板10之間。圖10係表示第2實施形態之半導體裝置1之製造方法之步驟剖面圖。
於圖10(a)之步驟中，於基板10之正面10a之應安裝間隔片70-1、70-2之區域配置接著膜30-1、30-2。然後，於接著膜30-1、30-2之+Z側配置間隔片70-1、70-2。由此，間隔片70-1、70-2經由接著膜30-1、30-2接著安裝(mount)於基板10之正面10a。
於圖10(b)之步驟中，於基板10之正面10a之間隔片70-1、70-2之間之區域，介隔複數個凸塊電極21配置控制晶片20。此時，於控制晶片20之正面20a與基板10之正面10a對向之狀態下，於基板10之正面10a配置控制晶片20。然後，於基板10之正面10a與控制晶片20之正面20a之間之複數個凸塊電極21之間隙填充接著樹脂22。其後，複數個凸塊電極21經由基板10被加熱至第1溫度並於某種程度上熔融。
此時，雖然存在流出接著樹脂22之熔融片(Bleed)22a之可能性，但由於間隔片70已經經由接著膜30安裝於基板10之正面10a，因此，間隔片70與基板10之間未介置接著樹脂22之熔融片(Bleed)。
於圖10(c)之步驟中，接合頭210對控制晶片20之背面20b加壓，複數個凸塊電極21壓抵於基板10之正面10a上之電極。與此同時，複數個凸塊電極21經由基板10被加熱至高於第1溫度之第2溫度而與正面10a上之電極接合。
此時，第2溫度亦可設為高於接著樹脂22之玻璃轉移點之溫度。若將接著樹脂22加熱至低於玻璃轉移點之溫度，則存在接著樹脂22熱縮而使基板10彎曲之可能性。另一方面，若將接著樹脂22加熱至高於玻璃轉移點之溫度，則接著樹脂22成為非晶狀態而能夠釋放熱縮之應力，因此能夠將基板10恢復至平坦。
於圖10(d)之步驟中，於控制晶片20及間隔片70-1、70-2之+Z側配置接著膜30-3。然後，於接著膜30-3之+Z側配置記憶體晶片40-1。由此，記憶體晶片40-1經由接著膜30-3接著安裝(mount)於控制晶片20及間隔片70-1、70-2之+Z側。
其後，記憶體晶片40-2～40-8經由接著膜30-4～30-10接著安裝(mount)於更+Z側。由此，能夠獲得圖1所示之半導體裝置1。
如上所述，於第2實施形態中，將間隔片70安裝於基板10之正面10a，其後，將控制晶片20安裝於基板10之正面10a。由此，能夠抑制接著樹脂22之熔融片(Bleed)介置於間隔片70與基板10之間，因此能夠抑制電連接不良，能夠容易地降低半導體裝置1之安裝高度。
再者，於圖10(a)、圖10(b)之步驟中，將各間隔片70距基板10之主面10a之高度構成為控制晶片20之高度之上限與下限之間的範圍內。因此，於圖10(c)之步驟中，存在接合頭210無法對控制晶片20之背面20b之低於間隔片70之正面70a之部分加壓之可能性，從而存在凸塊電極21與基板10之正面10a上之電極之接合不充分之可能性。
考慮到這一點，於半導體裝置中，亦可將各間隔片距基板之主面之高度構成為低於控制晶片之高度之下限。
例如，亦可如圖11、圖12所示般構成間隔片70p-1、70p-2。圖11係表示第2實施形態之變化例中之間隔片70p-1及控制晶片20之高度之放大剖面圖。圖12係表示第2實施形態之變化例中之間隔片70p-2及控制晶片20之高度之放大剖面圖。間隔片70p-1之正面70ap距基板10之正面10a之高度H70ap1低於控制晶片20之背面20b之下限高度H20b_min。間隔片70p-2之正面70ap距基板10之正面10a之高度H70ap2低於控制晶片20之背面20b之下限高度H20b_min。由此，於圖10(c)之步驟中，接合頭210能夠容易地對控制晶片20之背面20b加壓。
此時，下限高度H20b_min及高度H70ap2之差亦可小於上限高度H20b_max及下限高度H20b_min之差。即，以下數式1亦可成立。H20b_min－H70ap2＜H20b_max－H20b_min･･･數式1
由此，於圖10(c)之步驟中，接合頭210能夠容易地對控制晶片20之背面20b加壓，並且能夠抑制控制晶片20之背面與間隔片之正面之高度差。
對本發明之若干實施形態進行了說明，但該些實施形態只係作為例子提出，並不意圖限定發明之範圍。該些新穎之實施形態能夠以其它各種方式實施，且能夠於不脫離發明之主旨之範圍內進行各種省略、替換、變更。該些實施形態及其變化包含於發明之範圍及主旨中，並且包含於權利要求書中記載之發明及其均等之範圍內。
相關申請案之引用 本申請案基於2019年09月17日提出申請之現有之日本專利申請案第2019-168746號之優先權之利益，且謀求其利益，其整體內容藉由引用而包含於此。
1:半導體裝置 1i:半導體裝置 1j:半導體裝置 1n:半導體裝置 10:基板 10a:正面 10b:背面 11:阻焊劑層 12:預浸料層 13:核心層 14:導電層 15:通孔電極 20:控制晶片 20a:正面 20b:背面 20bi:背面 20bn:背面 20i:控制晶片 20i1:邊 20i2:邊 20i3:邊 20i4:邊 20n:控制晶片 21:凸塊電極 22:接著樹脂 22a:熔融片 30-1:接著膜 30-2:接著膜 30-3:接著膜 30-4:接著膜 30-5:接著膜 30-6:接著膜 30-7:接著膜 30-8:接著膜 30-9:接著膜 30-10:接著膜 30i-3:接著膜 30i-4:接著膜 30i-5:接著膜 30i-6:接著膜 30k-1:接著膜 30k-2:接著膜 30k-3:接著膜 30k-4:接著膜 30k-5:接著膜 30k-6:接著膜 30k-7:接著膜 30k-8:接著膜 30k-9:接著膜 40-1:記憶體晶片 40-2:記憶體晶片 40-3:記憶體晶片 40-4:記憶體晶片 40-5:記憶體晶片 40-6:記憶體晶片 40-7:記憶體晶片 40-8:記憶體晶片 40i-1:記憶體晶片 40i-2:記憶體晶片 40i-3:記憶體晶片 40i-4:記憶體晶片 40k-1:記憶體晶片 40k-2:記憶體晶片 40k-3:記憶體晶片 40k-4:記憶體晶片 41:接合線 50:密封樹脂 60:外部電極 70-1:間隔片 70-2:間隔片 70a:正面 70ap:正面 70b:背面 70i-1:間隔片 70i-2:間隔片 70j-1:間隔片 70j-2:間隔片 70j-3:間隔片 70j-4:間隔片 70k-1:間隔片 70k-2:間隔片 70k-3:間隔片 70k-4:間隔片 70k-5:間隔片 70p-1:間隔片 70p-2:間隔片 90n:間隔片 101-1:電極圖案 101-2:電極圖案 101-k:電極圖案 101-(k+1):電極圖案 101-2k:電極圖案 210:接合頭 A:線 B:線 H20b_max:上限高度 H20b_min:下限高度 H70a1:高度 H70a2:高度 H70ap1:高度 X:方向 Y:方向 Z:方向
圖1係表示第1實施形態之半導體裝置之構成之剖面圖。  圖2係表示第1實施形態之間隔片及控制晶片之高度之放大剖面圖。  圖3係表示第1實施形態之間隔片及控制晶片之高度之放大剖面圖。  圖4係表示第1實施形態之第1變化例中之間隔片及控制晶片之佈局構成之俯視圖。  圖5係表示第1實施形態之第1變化例中之間隔片、控制晶片及記憶體晶片之積層構成之剖面圖。  圖6係表示第1實施形態之第2變化例中之間隔片及控制晶片之佈局構成之俯視圖。  圖7係表示第1實施形態之第3變化例中之間隔片及控制晶片之佈局構成之俯視圖。  圖8係表示第1實施形態之第3變化例中之間隔片、控制晶片及記憶體晶片之積層構成之剖面圖。  圖9係表示第1實施形態之第4變化例中之間隔片、控制晶片及記憶體晶片之積層構成之剖面圖。
圖10(a)～(d)係表示第2實施形態之半導體裝置之製造方法之步驟剖面圖。  圖11係表示第2實施形態之變化例中之間隔片及控制晶片之高度之放大剖面圖。  圖12係表示第2實施形態之變化例中之間隔片及控制晶片之高度之放大剖面圖。
1:半導體裝置 10:基板 10a:正面 10b:背面 11:阻焊劑層 12:預浸料層 13:核心層 14:導電層 15:通孔電極 20:控制晶片 20a:正面 20b:背面 21:凸塊電極 22:接著樹脂 30-1:接著膜 30-2:接著膜 30-3:接著膜 30-4:接著膜 30-5:接著膜 30-6:接著膜 30-7:接著膜 30-8:接著膜 30-9:接著膜 30-10:接著膜 40-1:記憶體晶片 40-2:記憶體晶片 40-3:記憶體晶片 40-4:記憶體晶片 40-5:記憶體晶片 40-6:記憶體晶片 40-7:記憶體晶片 40-8:記憶體晶片 41:接合線 50:密封樹脂 60:外部電極 70-1:間隔片 70-2:間隔片 70a:正面 70b:背面 X:方向 Y:方向 Z:方向

Claims (9)

  1. 一種半導體裝置，其具備： 基板，其於主面設置有第1端子； 第1半導體晶片，其於第1正面設置有與上述第1端子連接之凸塊電極，具有與上述第1正面為相反側之第1背面，上述第1正面與上述主面對面； 第1間隔片，其具有第2正面及與上述主面對面之第2背面，上述第2正面距上述主面之高度為上述第1背面距上述主面之高度之上限與下限之間的範圍內；及 第2間隔片，其具有第3正面及與上述主面對面之第3背面，上述第3正面距上述主面之高度為上述第1背面距上述主面之高度之上限與下限之間的範圍內。
  2. 如請求項1之半導體裝置，其中上述第1間隔片之面積與上述第2間隔片之面積於俯視下相互大致均等， 上述第1半導體晶片之外緣具有第1邊及與上述第1邊相向之第2邊， 上述第1間隔片於俯視下與上述第1邊並排， 上述第2間隔片於俯視下與上述第2邊並排。
  3. 如請求項1之半導體裝置，其中上述第1間隔片之面積與上述第2間隔片之面積於俯視下相互大致均等， 上述第1半導體晶片之外緣具有第1邊及與上述第1邊交叉之第2邊， 上述第1間隔片於俯視下與上述第1邊並排， 上述第2間隔片於俯視下與上述第2邊並排。
  4. 如請求項1至3中任一項之半導體裝置，其中於上述主面進而設置有第2端子，且進而具備： 第1膜，其設置於上述主面與上述第1間隔片之間； 第2膜，其設置於上述主面與上述第2間隔片之間； 第3膜，其至少覆蓋上述第1背面及上述第2正面； 第2半導體晶片，其具有設置有第1焊墊電極之第4正面及面向上述第3接著膜之第4背面；及 第1接合線，其將上述第2端子與上述第1焊墊電極連接；且 上述第3膜之厚度與上述第1膜之厚度大致均等，或大於上述第1膜之厚度， 上述第3膜之厚度與上述第2膜之厚度大致均等，或大於上述第2膜之厚度。
  5. 如請求項4之半導體裝置，其進而具備： 第4膜，其覆蓋上述第4正面； 第3半導體晶片，其具有設置有第2焊墊電極之第5正面及面向上述第4膜之第5背面；及 第2接合線，其將上述第2端子與上述第2焊墊電極連接；且 上述第3膜之厚度與上述第4膜之厚度大致均等，或大於上述第4膜之厚度。
  6. 一種半導體裝置，其具備： 基板，其於主面設置有第1端子； 第1半導體晶片，其於第1正面設置有與上述第1端子連接之凸塊電極，具有與上述第1正面為相反側之第1背面，上述第1正面與上述主面對面； 第1間隔片，其具有第2正面及與上述主面對面之第2背面，上述第2正面距上述主面之高度低於上述第1背面距上述主面之高度之下限；及 第2間隔片，其具有第3正面及與上述主面對面之第3背面，上述第3正面距上述主面之高度低於上述第1背面距上述主面之高度之下限。
  7. 如請求項6之半導體裝置，其中於上述主面設置有第2端子，且進而具備： 膜，其至少覆蓋上述第1背面及上述第2正面或上述第3正面； 第2半導體晶片，其具有設置有焊墊電極之第4正面及面向上述膜之第4背面；及 接合線，其將上述第2端子與上述焊墊電極連接。
  8. 一種半導體裝置之製造方法，其具備： 將第1間隔片設置於基板之主面，將第2間隔片設置於上述基板之主面；及 於設置上述第1間隔片及上述第2間隔片後， 於第1半導體晶片之正面與上述主面對面之狀態下介隔複數個凸塊電極將上述第1半導體晶片設置於上述主面。
  9. 如請求項8之半導體裝置之製造方法，其中將上述第1半導體晶片設置於上述主面包括： 於上述第1半導體晶片之正面與上述基板之主面對向之狀態下介隔上述複數個凸塊電極將上述第1半導體晶片配置於上述主面；及 利用接合工具之頭將上述第1半導體晶片之背面向上述基板側按壓。
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