TW201742200A - 晶片封裝體及其製造方法 - Google Patents

晶片封裝體及其製造方法 Download PDF

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Publication number
TW201742200A
TW201742200A TW105143527A TW105143527A TW201742200A TW 201742200 A TW201742200 A TW 201742200A TW 105143527 A TW105143527 A TW 105143527A TW 105143527 A TW105143527 A TW 105143527A TW 201742200 A TW201742200 A TW 201742200A
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Taiwan
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chip package
layer
substrate
protective layer
cover plate
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TW105143527A
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English (en)
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沈佳倫
林柏伸
詹昂
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精材科技股份有限公司
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Publication of TW201742200A publication Critical patent/TW201742200A/zh

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Abstract

本發明揭露一種晶片封裝體，包括一基底。基底具有一前表面、一背表面及一側表面。一重佈線層位於背表面上，且與基底內的一感測或元件區電性連接。一保護層覆蓋重佈線層，且延伸到側表面上。一蓋板位於前表面上，且橫向地突出於側表面上的保護層。蓋板具有面向前表面的一第一表面及背向前表面的一第二表面，且蓋板的一底部自第一表面朝第二表面變寬。本發明亦揭露一種晶片封裝體的製造方法。

Description

晶片封裝體及其製造方法
本發明係有關於一種晶片封裝技術，特別為有關於採用晶圓級封裝技術的一種晶片封裝體及其製造方法。
一般而言，晶圓級封裝製程包括在晶圓階段完成封裝步驟，再予以切割成獨立的晶片封裝體。晶片封裝體除了將晶片保護於其中，使其免受外界環境污染外，還提供晶片內部電子元件與外界之電性連接通路。
然而，在進行切割製程期間，晶圓內及/或晶圓上的膜層容易因切割偏移而破裂受損，且經切割處可能出現不均勻的凹陷或凸起，導致切割出的晶片封裝體的品質及可靠度不佳。再者，晶圓的切割道的尺寸取決於切割刀具的尺寸，故單一晶圓能切割出的晶片封裝體的數量有所限制，且切割刀具的切割速度慢，故切割製程所需的製程時間長，因此難以進一步降低製造成本及製造時間。
因此，有必要尋求一種新穎的晶片封裝體及其製造方法，其能夠解決或改善上述的問題。
本發明實施例係提供一種晶片封裝體，包括一基底、一重佈線層、一保護層及一蓋板。基底具有一前表面、一 背表面及一側表面。重佈線層位於背表面上，且與基底內的一感測或元件區電性連接。保護層覆蓋重佈線層，且延伸到側表面上。蓋板位於前表面上，且橫向地突出於側表面上的保護層。蓋板具有面向前表面的一第一表面及背向前表面的一第二表面，且蓋板的一底部自第一表面朝第二表面變寬。
本發明實施例係提供一種晶片封裝體的製造方法，包括提供一基底。基底具有一前表面、一背表面及一側表面。晶片封裝體的製造方法也包括在背表面上形成一重佈線層。重佈線層與基底內的一感測或元件區電性連接。晶片封裝體的製造方法還包括形成一保護層，保護層覆蓋重佈線層，且延伸到側表面上。再者，晶片封裝體的製造方法包括在前表面上提供一蓋板，蓋板橫向地突出於側表面上的保護層。蓋板具有面向前表面的一第一表面及背向前表面的一第二表面，且蓋板的一底部自第一表面朝第二表面變寬。
100‧‧‧基底
100a‧‧‧前表面
100b‧‧‧背表面
100c‧‧‧側表面
110‧‧‧感測或元件區
120‧‧‧晶片區
130‧‧‧絕緣層
140‧‧‧導電墊
150‧‧‧光學部件
160‧‧‧間隔層
165‧‧‧黏著層
170‧‧‧蓋板
170a‧‧‧第一表面
170b‧‧‧第二表面
170c‧‧‧側表面
170d‧‧‧側表面
170e‧‧‧側表面
180‧‧‧空腔
190‧‧‧第一開口
200‧‧‧第二開口
210‧‧‧絕緣層
220‧‧‧重佈線層
230‧‧‧保護層
230c‧‧‧側表面
240‧‧‧孔洞
250‧‧‧導電結構
260‧‧‧凹口
270‧‧‧凹口
280‧‧‧刻痕
P‧‧‧部分
SC‧‧‧切割道
第1A至1H圖係繪示出根據本發明一實施例之晶片封裝體的製造方法的剖面示意圖。
第2圖係繪示出根據本發明一實施例之晶片封裝體的局部剖面示意圖。
第3圖係繪示出根據本發明一實施例之晶片封裝體的平面示意圖。
第4A至4E圖係繪示出根據本發明另一實施例之晶片封裝體的製造方法的剖面示意圖。
以下將詳細說明本發明實施例之製作與使用方式。然應注意的是，本發明提供許多可供應用的發明概念，其可以多種特定型式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式，非用以限制本發明之範圍。此外，在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明，不代表所討論之不同實施例及/或結構之間具有任何關連性。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。
本發明一實施例之晶片封裝體可用以封裝微機電系統晶片。然其應用不限於此，例如在本發明之晶片封裝體的實施例中，其可應用於各種包含主動元件或被動元件(active or passive elements)、數位電路或類比電路(digital or analog circuits)等積體電路的電子元件(electronic components)，例如是有關於光電元件(opto electronic devices)、微機電系統(Micro Electro Mechanical System，MEMS)、生物辨識元件(biometric device)、微流體系統(micro fluidic systems)、或利用熱、光線、電容及壓力等物理量變化來測量的物理感測器(Physical Sensor)。特別是可選擇使用晶圓級封裝(wafer scale package，WSP)製程對影像感測元件、發光二極體(light-emitting diodes，LEDs)、太陽能電池(solar cells)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、指紋辨識器(fingerprint recognition device)、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力感測器(process sensors)或噴墨頭(ink printer heads)等半導體晶片進行封裝。
其中上述晶圓級封裝製程主要係指在晶圓階段完成封裝步驟後，再予以切割成獨立的封裝體，然而，在一特定實施例中，例如將已分離之半導體晶片重新分布在一承載晶圓上，再進行封裝製程，亦可稱之為晶圓級封裝製程。另外，上述晶圓級封裝製程亦適用於藉堆疊(stack)方式安排具有積體電路之多片晶圓，以形成多層積體電路(multi-layer integrated circuit devices)之晶片封裝體。
以下配合第1A至1H圖說明本發明一實施例之晶片封裝體的製造方法，其中第1A至1H圖係繪示出根據本發明一實施例之晶片封裝體的製造方法的剖面示意圖。
請參照第1A圖，提供一基底100，其具有一前表面100a及一背表面100b，且包括複數晶片區120。為簡化圖式，此處僅繪示出一完整的晶片區120及與其相鄰的晶片區120的一部分。在一些實施例中，基底100可為一矽基底或其他半導體基底。在一些實施例中，基底100為一矽晶圓，以利於進行晶圓級封裝製程。
基底100的前表面100a上具有一絕緣層130。一般而言，絕緣層130可由層間介電層(interlayer dielectric，ILD)、金屬間介電層(inter-metal dielectric，IMD)及覆蓋之鈍化層(passivation)組成。為簡化圖式，此處僅繪示出單層絕緣層130。在一些實施例中，絕緣層130可包括無機材料，例如氧化 矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合或其他適合的絕緣材料。
在一些實施例中，每一晶片區120的絕緣層130內具有一個或一個以上的導電墊140。在一些實施例中，導電墊140可為單層導電層或具有多層之導電層結構。為簡化圖式，此處僅以單層導電層作為範例說明。在一些實施例中，每一晶片區120的絕緣層130內包括一個或一個以上的開口，露出對應的導電墊140。
在一些實施例中，每一晶片區120內具有一感測或元件區110。感測或元件區110可鄰近於絕緣層130及基底100的前表面100a，且可透過內連線結構(未繪示)與導電墊140電性連接。感測或元件區110內包括一感測元件。在一些實施例中，感測或元件區110內包括感光元件或其他適合的光電元件。在其他實施例中，感測或元件區110內可包括感測生物特徵的元件(例如，一指紋辨識元件)、感測環境特徵的元件(例如，一溫度感測元件、一溼度感測元件、一壓力感測元件、一電容感測元件)或其他適合的感測元件。
在一些實施例中，可依序進行半導體裝置的前段(front end)製程(例如，在基底100內製作感測或元件區110)及後段(back end)製程(例如，在基底100上製作絕緣層130、內連線結構及導電墊140)來提供前述結構。換句話說，以下晶片封裝體的製造方法係用於對完成後段製程的基底進行後續的封裝製程。
在一些實施例中，每一晶片區120內具有一光學部 件150設置於基底100的前表面100a上，且對應於感測或元件區110。在一些實施例中，光學部件150可為微透鏡陣列、濾光層、其組合或其他適合的光學部件。
接著，在一蓋板170上形成一間隔層(或稱作圍堰(dam))160，透過間隔層160將蓋板170接合至基底100的前表面100a上，且間隔層160在每一晶片區120內的基底100與蓋板170之間形成一空腔180，使得光學部件150位於空腔180內，並透過蓋板170保護空腔180內的光學部件150。在其他實施例中，可先在基底100的前表面100a上形成間隔層160，之後將蓋板170接合至基底100上。在一些實施例中，蓋板170可包括玻璃、氮化鋁(AlN)、或其他適合的透明材料。在一些實施例中，蓋板170的厚度可大約為700μm或其他適合的厚度。
在一些實施例中，間隔層160大致上不吸收水氣。在一些實施例中，間隔層160不具有黏性，因此可透過額外的黏著膠將蓋板170貼附於基底100上。在一些其他實施例中，間隔層160可具有黏性，因此可透過間隔層160將蓋板170貼附於基底100上，如此一來間隔層160可不與任何的黏著膠接觸，以確保間隔層160之位置不因黏著膠而移動。同時，由於不需使用黏著膠，可避免黏著膠溢流而污染光學部件150。
在一些實施例中，可透過沉積製程(例如，塗佈製程、物理氣相沈積製程、化學氣相沈積製程或其他適合的製程)形成間隔層160。在一些實施例中，間隔層160可包括環氧樹脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂 (polyimide)、苯環丁烯(butylcyclobutene，BCB)、聚對二甲苯(parylene)、萘聚合物(polynaphthalenes)、氟碳化物(fluorocarbons)、丙烯酸酯(acrylates))或其他適合的絕緣材料。或者，間隔層160可包括光阻材料，且可透過曝光及顯影製程而圖案化，以露出光學部件150。
請參照第1B圖，以蓋板170作為承載基板，對基底100的背表面100b進行薄化製程(例如，蝕刻製程、銑削(milling)製程、磨削(grinding)製程或研磨(polishing)製程)，以減少基底100的厚度。
接著，透過微影製程及蝕刻製程(例如，乾蝕刻製程、濕蝕刻製程、電漿蝕刻製程、反應性離子蝕刻製程或其他適合的製程)，在每一晶片區120的基底100內同時形成複數第一開口190及第二開口200，第一開口190及第二開口200自基底100的背表面100b露出絕緣層130。在其他實施例中，可分別透過刻痕(notching)製程以及微影及蝕刻製程形成第二開口200以及第一開口190。
在一些實施例中，第一開口190對應於導電墊140而貫穿基底100，且第一開口190鄰近於前表面100a的口徑小於其鄰近於背表面100b的口徑，因此第一開口190具有傾斜的側表面，進而降低後續形成於第一開口190內的膜層的製程難度，並提高可靠度。舉例來說，由於第一開口190鄰近於前表面100a的口徑小於其鄰近於背表面100b的口徑，因此後續形成於第一開口190內的膜層(例如，後續形成的絕緣層210及重佈線層220)能夠較輕易地沉積於第一開口190與絕緣層130之間 的轉角，以避免影響電性連接路徑或產生漏電流的問題。
在一些實施例中，第二開口200沿著相鄰晶片區120之間的切割道SC延伸且貫穿基底100，使得每一晶片區120內的基底100彼此分離。第二開口200鄰近於前表面100a的口徑小於其鄰近於背表面100b的口徑，因此第二開口200具有傾斜的側表面，亦即每一晶片區120內的基底100具有傾斜的一側表面100c。
在一些實施例中，相鄰兩晶片區120內的多個第一開口190沿著第二開口200間隔排列，且第一開口190與第二開口200透過基底100的一部分(例如，側壁部分)互相間隔且完全隔離。在一些實施例中，第二開口200可沿著晶片區120延伸而環繞第一開口190。在某些其他實施例中，第一開口190與第二開口200連通。例如，第一開口190鄰近於背表面100b的部分與第二開口200鄰近於背表面100b的部分彼此連通，使得基底100具有一側壁部分低於背表面100b。換句話說，上述側壁部分的厚度小於基底100的厚度。由於第一開口190與第二開口200彼此連通，而並非透過基底100的一部分完全隔離，因此能夠防止應力累積於第一開口190與第二開口200之間的基底100，且可藉由第二開口200緩和及釋放應力，進而避免基底100的側壁部分出現破裂。
請參照第1C圖，可透過沉積製程(例如，塗佈製程、物理氣相沈積製程、化學氣相沈積製程或其他適合的製程)，在基底100的背表面100b上形成一絕緣層210，絕緣層210順應性沉積於第一開口190及第二開口200的側壁及底部上。在 一些實施例中，絕緣層210可包括環氧樹脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的絕緣材料。
接著，可透過微影製程及蝕刻製程，去除第一開口190底部的絕緣層210及其下方的絕緣層130，使得第一開口190延伸至絕緣層130內而露出對應的導電墊140。
之後，可透過沉積製程(例如，塗佈製程、物理氣相沉積製程、化學氣相沉積製程、電鍍製程、無電鍍製程或其他適合的製程)、微影製程及蝕刻製程，在絕緣層210上形成圖案化的重佈線層220。重佈線層220順應性延伸至第一開口190及第二開口200的側壁及底部，亦即重佈線層220順應性延伸至基底100的側表面100c。
在本實施例中，重佈線層220可透過絕緣層210與基底100電性隔離，且可經由第一開口190直接電性接觸或間接電性連接露出的導電墊140。因此，第一開口190內的重佈線層220也稱為矽通孔電極(through silicon via，TSV)。在一些實施例中，重佈線層220可包括鋁、銅、金、鉑、鎳、錫、前述之組合、導電高分子材料、導電陶瓷材料(例如，氧化銦錫或氧化銦鋅)或其他適合的導電材料。
請參照第1D圖，沿著切割道SC形成與第二開口200連通的一凹口260。凹口260穿過第二開口200內的重佈線層220及絕緣層210，且穿過絕緣層130，而進一步延伸到間隔層160內。凹口260切斷重佈線層220，使得相鄰晶片區120之間的重 佈線層220彼此分離。在其他實施例中，凹口260可能貫穿間隔層160。在一些實施例中，可進行切割製程來形成凹口260，但並不限定於此。舉例來說，利用切割刀具切割重佈線層220、絕緣層210、絕緣層130以及間隔層160，以形成凹口260。
請參照第1E圖，可透過沉積製程，在基底100的背表面100b及側表面100c上形成一保護層230，以覆蓋重佈線層220。在一些實施例中，保護層230填滿第二開口200。保護層230更填入凹口260，且覆蓋重佈線層220的末端。保護層230也覆蓋絕緣層210的末端、絕緣層130的側表面以及間隔層160的局部側表面。
在一些實施例中，保護層230未填入第一開口190，使得一孔洞240形成於第一開口190內的重佈線層220與保護層230之間。由於保護層230部分填充於第一開口190而留下孔洞240，因此後續製程中遭遇熱循環(Thermal Cycle)時，孔洞240能夠作為保護層230與重佈線層220之間的緩衝，以降低保護層230與重佈線層220之間由於熱膨脹係數不匹配所引發不必要的應力，且防止外界溫度或壓力劇烈變化時保護層230會過度拉扯重佈線層220，進而可避免靠近導電墊結構的重佈線層220剝離甚至斷路的問題。在一些其他實施例中，保護層230可局部填充第一開口190或完全填滿第一開口190。
在一些實施例中，保護層230可包括環氧樹脂、綠漆、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其 他適合的絕緣材料。
接著，可透過微影製程及蝕刻製程，在基底100的背表面100b上的保護層230內形成開口，以露出圖案化的重佈線層220的一部分。接著，可透過電鍍製程、網版印刷製程或其他適合的製程，在保護層230的開口內填入導電結構250(例如，焊球、凸塊或導電柱)，以與露出的重佈線層220電性連接。在一些實施例中，導電結構250可包括錫、鉛、銅、金、鎳、或前述之組合。
請參照第1F圖，沿著切割道SC形成一凹口270。凹口270穿過第二開口200及凹口260內的保護層230，且穿過間隔層160，而進一步延伸到蓋板170內。凹口270自蓋板170面向前表面100a的一第一表面170a向蓋板170內側延伸。在一些實施例中，從上視方向來看，凹口270沿著切割道SC環繞保護層230及導電結構250。在一些實施例中，蓋板170內的凹口270具有三角形的剖面輪廓，但凹口270可具有其他形狀的剖面輪廓，而並不限定於此。在一些實施例中，可進行雷射鑽孔製程或其他適合的製程來形成凹口270。
在一些實施例中，凹口270的寬度小於凹口260的寬度，且凹口270的深度大於凹口260的深度。在形成凹口270之後，保護層230仍然覆蓋重佈線層220的末端、絕緣層210的末端、絕緣層130的側表面以及間隔層160的局部側表面。
請參照第1G圖，在蓋板170內形成一刻痕(notch)280，其自蓋板170背向前表面100a的一第二表面170b延伸。在一些實施例中，刻痕280大致上對準於凹口270。在一些 實施例中，刻痕280具有三角形的剖面輪廓，但刻痕280可具有其他形狀的剖面輪廓，而並不限定於此。在一些實施例中，可進行利用劃線(scribing)技術或其他適合的方法形成刻痕280。舉例來說，使用(鑽石)刀輪(cutter wheel)或其他適合的劃線器(scriber)沿著切割道SC在蓋板170的第二表面170b劃線而形成刻痕280。
之後，利用斷裂(breaking cut)技術，使用劈刀(breaker)或其他適合的方式將蓋板170沿著凹口270及刻痕280垂直地斷裂，以將每一晶片區120的蓋板170彼此分離，進而形成複數獨立的晶片封裝體，如第1H圖所示。
根據本發明的上述實施例，在蓋板170的第一表面170a形成凹口270且在蓋板170的第二表面170b形成刻痕280，之後利用斷裂技術將每一晶片區120的蓋板170分離，以形成獨立的晶片封裝體。如此一來，蓋板170能夠直接沿著凹口270及刻痕280均勻地斷裂，因而具有平直的側表面。凹口270提升了斷裂技術的精準度而有利於蓋板170的分離，例如可避免蓋板170的側表面出現不均勻的凹陷及/或凸起，也防止蓋板170的表面出現崩裂(chipping)的問題。
再者，在形成保護層230之前沿著切割道SC預先形成凹口260，後續形成的保護層230填入凹口260內，接著透過形成凹口270(例如，進行雷射鑽孔製程)將每一晶片區120的保護層230彼此分離，其中凹口270的尺寸小於凹口260的尺寸。如此一來，能夠避免保護層230過度地破裂受損，以確保分離後的晶片封裝體的側表面能夠受到保護層230良好地保護，且 能夠防止晶片封裝體內的膜層(例如，重佈線層220、絕緣層210、絕緣層130及間隔層160)在上述分離的過程中受到破壞，因此可提升晶片封裝體的品質及可靠度。
請參照第1H、2及3圖，其中第2圖係繪示出第1H圖中晶片封裝體的一部份P的剖面示意圖，且第3圖係繪示出根據本發明一實施例之晶片封裝體的平面示意圖。為了說明本發明實施例，此處使用具有前照式(frontside illumination，FSI)感測裝置的晶片封裝體作為範例。然而，本發明實施例也可適用於具有背照式(backside illumination，BSI)感測裝置的晶片封裝體，亦不限定於任何特定的應用。
透過上述製造方法所形成的晶片封裝體中，與感測或元件區110及導電墊140電性連接的重佈線層220位於基底100的背表面100b上，且進一步延伸到側表面100c。保護層230不僅覆蓋背表面100b上的重佈線層220，還覆蓋側表面100c上的重佈線層220，且更延伸超出基底100的前表面100a。蓋板170位於基底100的前表面100a上，且橫向地突出於側表面100c上的保護層230。換句話說，蓋板170的寬度大於基底100的寬度，也大於保護層230的寬度，且蓋板170的側表面與保護層230的側表面非共平面。
如第2圖所示，蓋板170具有面向前表面100a的第一表面170a、背向前表面100a的第二表面170b、及側表面170c。再者，凹口270的形成使得蓋板170的底部具有鄰接第一表面170a及側表面170c的一側表面170d，且刻痕280的形成使得蓋板170的頂部具有鄰接第二表面170b及側表面170c的一側 表面170e。在一些實施例中，側表面170c鄰接蓋板170的底部及頂部，且大致上垂直於第一表面170a及/或第二表面170b。再者，側表面170d傾斜於第一表面170a及/或第二表面170b，側表面170e傾斜於第一表面170a及/或第二表面170b，且側表面170d及/或側表面170e傾斜於側表面170c。在一些實施例中，側表面170d的一法向量大致上平行於側表面170e。
如第1H及2圖所示，凹口270的形成使得蓋板170的底部自第一表面170a朝第二表面170b變寬，且刻痕280的形成使得蓋板170的頂部自第二表面170b朝第一表面170a變寬。在一些實施例中，蓋板170的底部自第一表面170a朝第二表面170b漸進地變寬。再者，蓋板170的頂部自第二表面170b朝第一表面170a漸進地變寬。在一些實施例中，蓋板170的底部變寬的程度(gradient)大致上等同於蓋板170的頂部變寬的程度。再者，蓋板170夾設於底部與頂部的中間部分大致上具有均勻且一致的厚度，也就是說，中間部分的側表面170c為平坦的表面。
如第1H及2圖所示，在一些實施例中，側表面100c上的保護層230具有平坦的一側表面230c。在一些實施例中，側表面230c大致上垂直於第一表面170a及/或第二表面170b，且側表面230c大致上平行於側表面170c，如第3圖所示。在一些實施例中，側表面170d傾斜於側表面230c，且側表面170e傾斜於側表面230c。再者，在一些實施例中，第一表面170a的一邊緣大致上對準於側表面230c，且第二表面170b的一邊緣大致上對準於側表面230c。換句話說，側表面170d的一邊緣大致上對 準於側表面230c，且側表面170e的一邊緣大致上對準於側表面230c。在一些實施例中，從上視方向來看，側表面170d環繞保護層230，如第3圖所示。
以下配合第4A至4E圖說明本發明另一實施例之晶片封裝體的製造方法。第4A至4E圖係繪示出根據本發明另一實施例之晶片封裝體的製造方法的剖面示意圖，其中相同於第1A至1H圖中的部件係使用相同的標號並省略其說明。
請參照第4A圖，可透過與第1A圖相同或相似之步驟提供基底100，其中每一晶片區120內的基底100的前表面100a上具有絕緣層130，且絕緣層130上具有光學部件150。接著，可透過一黏著層165將蓋板170接合至基底100。在一些實施例中，形成於蓋板170與基底100之間的黏著層165完全覆蓋基底100的前表面100a，因此光學部件150、絕緣層130、導電墊140及感測或元件區110也被黏著層165所覆蓋。在一些實施例中，黏著層165為雙面膠材或其他適合的黏著材料。
請參照第4B圖，可透過與第1B圖相同或相似之步驟，對基底100進行薄化製程，且在基底100內形成第一開口190及第二開口200。接著，可透過與第1C圖相同或相似之步驟，在基底100的背表面100b上形成絕緣層210及重佈線層220。
請參照第4C圖，可透過與第1D圖相同或相似之步驟，形成凹口260。凹口260穿過第二開口200內的重佈線層220及絕緣層210，且穿過絕緣層130，而進一步延伸到黏著層165內。在其他實施例中，凹口260可能貫穿黏著層165，且使得後續形成的保護層230直接接觸蓋板170。接著，可透過與第1E 圖相同或相似之步驟，在基底100的背表面100b上、第二開口200內及凹口260內形成保護層230。在一些實施例中，保護層230遠離基底100的表面為平坦的。在一些其他實施例中，保護層230遠離基底100的表面為不平坦的，例如保護層230覆蓋第一開口190及/或第二開口200的表面可能為凹陷的表面。
請參照第4D圖，可透過與第1F及1G圖相同或相似之步驟，形成凹口270及刻痕280。凹口270穿過第二開口200及凹口260內的保護層230，且貫穿黏著層165，而進一步延伸到蓋板170內。在一些實施例中，在形成凹口270之後形成刻痕280。在一些其他實施例中，可能在刻痕280之後形成凹口270。
透過雷射鑽孔製程而非使用切割刀具的切割製程來形成凹口270，可增加形成凹口270的精準度，避免凹口270的位置偏移而破壞其他膜層(例如，重佈線層220、絕緣層210、絕緣層130及間隔層160)，也能夠防止用於保護上述其他膜層的保護層230被過度移除，以確保上述其他膜層的側表面能夠受到良好的保護。
接著，可透過與第1H圖相同或相似之步驟，利用斷裂技術將每一晶片區120的蓋板170彼此分離，進而形成複數獨立的晶片封裝體，如第4E圖所示。
根據本發明的一些實施例，採用雷射鑽孔製程及斷裂技術取代使用切割刀具的切割製程，不僅可避免切割偏移的問題，更使得晶圓的切割道的尺寸不會受限於切割刀具的尺寸(切割道的寬度可縮小至80μm以下，例如可為大約60μm或更小)，因此能夠大幅增加切割道的設計彈性，且單一晶圓能切 割出的晶片封裝體的數量也能進一步增加。再者，相較於使用切割刀具，利用雷射鑽孔製程及斷裂技術分離晶圓所需的製程時間短且製程費用也較低，因此能夠有效降低製造成本及製造時間。
可以理解的是，上述晶片封裝體的製造方法並不限定於具有光學感測裝置的晶片封裝體，其亦可應用於其他類型的晶片封裝體。舉例來說，上述形成凹口及刻痕的方法以及分離出多個晶片封裝體的方法可應用於具有生物特徵感測元件(例如，指紋辨識元件)或環境特徵感測元件(例如，溫度感測元件、溼度感測元件、壓力感測元件、電容感測元件)的晶片封裝體、或其他適合的晶片封裝體。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可更動與組合上述各種實施例。
100‧‧‧基底
100a‧‧‧前表面
100b‧‧‧背表面
100c‧‧‧側表面
130‧‧‧絕緣層
160‧‧‧間隔層
170‧‧‧蓋板
170a‧‧‧第一表面
170b‧‧‧第二表面
170c‧‧‧側表面
170d‧‧‧側表面
170e‧‧‧側表面
200‧‧‧第二開口
210‧‧‧絕緣層
220‧‧‧重佈線層
230‧‧‧保護層
230c‧‧‧側表面
P‧‧‧部分

Claims (20)

  1. 一種晶片封裝體，包括：一基底，具有一前表面、一背表面及一側表面；一重佈線層，位於該背表面上，且與該基底內的一感測或元件區電性連接；一保護層，覆蓋該重佈線層，且延伸到該側表面上；以及一蓋板，位於該前表面上，且橫向地突出於該側表面上的該保護層，其中該蓋板具有面向該前表面的一第一表面及背向該前表面的一第二表面，且該蓋板的一底部自該第一表面朝該第二表面變寬。
  2. 如申請專利範圍第1項所述之晶片封裝體，其中該蓋板的該底部的一側表面鄰接且傾斜於該第一表面。
  3. 如申請專利範圍第1項所述之晶片封裝體，其中該蓋板的一頂部自該第二表面朝該第一表面變寬。
  4. 如申請專利範圍第3項所述之晶片封裝體，其中該蓋板的該頂部的一側表面鄰接且傾斜於該第二表面。
  5. 如申請專利範圍第1項所述之晶片封裝體，其中該蓋板的一側表面鄰接該底部且大致上垂直於該第一表面及/或該第二表面。
  6. 如申請專利範圍第1項所述之晶片封裝體，其中該基底的該背表面上的該保護層具有平坦的一側表面，且該蓋板的該第一表面的邊緣大致上對準於該保護層的該側表面。
  7. 如申請專利範圍第1項所述之晶片封裝體，其中從上視方向來看，該蓋板的該底部的一側表面環繞該保護層。
  8. 如申請專利範圍第1項所述之晶片封裝體，其中該重佈線層進一步延伸到該基底的該側表面上，且該保護層覆蓋位於該側表面上的該重佈線層的一末端。
  9. 如申請專利範圍第1項所述之晶片封裝體，更包括一絕緣層，位於該基底與該蓋板之間，其中該絕緣層內具有一導電墊與該感測或元件區及該重佈線層電性連接，且其中該保護層覆蓋該絕緣層的一側表面。
  10. 如申請專利範圍第1項所述之晶片封裝體，更包括一間隔層或一黏著層，位於該基底與該蓋板之間，且具有一側表面被該保護層所覆蓋。
  11. 一種晶片封裝體的製造方法，包括：提供一基底，其中該基底具有一前表面、一背表面及一側表面；在該背表面上形成一重佈線層，其中該重佈線層與該基底內的一感測或元件區電性連接；形成一保護層，其中該保護層覆蓋該重佈線層，且延伸到該側表面上；以及在該前表面上提供一蓋板，其中該蓋板橫向地突出於該側表面上的該保護層，且其中該蓋板具有面向該前表面的一第一表面及背向該前表面的一第二表面，且該蓋板的一底部自該第一表面朝該第二表面變寬。
  12. 如申請專利範圍第11項所述之晶片封裝體的製造方法，其中該重佈線層進一步延伸到該側表面上，且其中該晶片封裝體的製造方法更包括在形成該保護層之前切割該重佈線 層，使得該側表面上的該重佈線層具有一末端，且該保護層覆蓋該末端。
  13. 如申請專利範圍第11項所述之晶片封裝體的製造方法，更包括形成一凹口，其中該凹口位於該背表面上的該保護層內且延伸到該蓋板內，使得該蓋板的該底部自該第一表面朝該第二表面變寬。
  14. 如申請專利範圍第13項所述之晶片封裝體的製造方法，其中形成該凹口的步驟包括進行雷射鑽孔製程。
  15. 如申請專利範圍第13項所述之晶片封裝體的製造方法，更包括在形成該重佈線層之前，在該基底與該蓋板之間形成一間隔層或一黏著層，其中該凹口延伸穿過該間隔層或該黏著層。
  16. 如申請專利範圍第13項所述之晶片封裝體的製造方法，更包括在該蓋板內形成一刻痕，使得該蓋板的一頂部自該第二表面朝該第一表面變寬，且其中該刻痕大致上對準於該凹口。
  17. 如申請專利範圍第16項所述之晶片封裝體的製造方法，其中利用劃線技術形成該刻痕。
  18. 如申請專利範圍第16項所述之晶片封裝體的製造方法，其中在形成該凹口之後，形成該刻痕。
  19. 如申請專利範圍第16項所述之晶片封裝體的製造方法，更包括利用斷裂技術使得該蓋板沿著該凹口及該刻痕而斷裂。
  20. 如申請專利範圍第19項所述之晶片封裝體的製造方法，其 中該蓋板沿著該凹口及該刻痕大致上垂直地斷裂。
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