CN107221540B - 晶片封装体及其制造方法 - Google Patents

晶片封装体及其制造方法 Download PDF

Info

Publication number
CN107221540B
CN107221540B CN201710165062.1A CN201710165062A CN107221540B CN 107221540 B CN107221540 B CN 107221540B CN 201710165062 A CN201710165062 A CN 201710165062A CN 107221540 B CN107221540 B CN 107221540B
Authority
CN
China
Prior art keywords
substrate
layer
dielectric layer
region
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710165062.1A
Other languages
English (en)
Other versions
CN107221540A (zh
Inventor
何彦仕
林佳升
李柏汉
孙唯伦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
XinTec Inc
Original Assignee
XinTec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by XinTec Inc filed Critical XinTec Inc
Publication of CN107221540A publication Critical patent/CN107221540A/zh
Application granted granted Critical
Publication of CN107221540B publication Critical patent/CN107221540B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14632—Wafer-level processed structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687—Wafer level processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H01L2223/5446—Located in scribe lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/05611—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05669—Platinum [Pt] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/05686—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Electromagnetism (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明提供一种晶片封装体及其制造方法，该晶片封装体包括一基底，具有一第一表面及与其相对的一第二表面，其中基底具有一晶片区及沿晶片区的边缘延伸的一切割道区。晶片封装体还包括一介电层，设置于基底的第一表面上，其中对应于切割道区的介电层内具有一通槽，且通槽沿切割道区的延伸方向延伸。本发明可维持或改善晶片封装体可靠度及效能，避免基底翘曲，且可进一步缩小晶片封装体的尺寸。

Description

晶片封装体及其制造方法
技术领域
本发明有关于一种晶片封装技术，特别为有关于一种具有低介电常数(low-k)介电材料保护结构的晶片封装体及其制造方法。
背景技术
光电元件(例如，影像感测元件)在撷取影像等应用中扮演着重要的角色，其已广泛地应用于例如数字相机(digital camera)、数字录影机(digital video recorder)、手机(mobile phone)等电子产品中，而晶片封装制程是形成电子产品过程中的重要步骤。晶片封装体除了将感测晶片保护于其中，使其免受外界环境污染外，还提供感测晶片内部电子元件与外界的电性连接通路。
然而，在具有感测晶片的晶片封装体制造中，影响封装体可靠度的其中一个原因就是形成于晶片封装体的低介电常数介电材料(如，金属化层/内连接层的绝缘部)内的裂缝。举例来说，当晶圆切割成独立的晶片封装体时，晶片封装体的低介电常数介电材料因切割制程所引发的应力而于其内形成裂缝。如此一来，造成晶片封装体可靠度及效能下降。
因此，有必要寻求一种新颖的晶片封装体及其制造方法，其能够解决或改善上述的问题。
发明内容
本发明提供一种晶片封装体，包括一基底，具有一第一表面及与其相对的一第二表面，其中基底具有一晶片区及沿晶片区的边缘延伸的一切割道区。晶片封装体还包括一介电层，设置于基底的第一表面上，其中对应于切割道区的介电层内具有一通槽，且通槽沿切割道区的延伸方向延伸。
本发明还提供一种晶片封装体的制造方法，包括：提供一基底，基底具有一第一表面及与其相对的一第二表面，且具有一晶片区及沿晶片区的边缘延伸的一切割道区；于基底的第一表面上形成一介电层；以及于对应于切割道区的介电层内形成一通槽，其中通槽沿切割道区的延伸方向延伸。
本发明可维持或改善晶片封装体可靠度及效能，避免基底翘曲，且可进一步缩小晶片封装体的尺寸。
附图说明
图1A至1I是绘示出根据本发明一实施例的晶片封装体的制造方法剖面示意图。
图2是绘示出图1I中晶片封装体的一部分的介电层仰视示意图。
图3A至3E是绘示出根据本发明另一实施例的晶片封装体的制造方法剖面示意图。
图4是绘示出图3E中晶片封装体的一部分的介电层仰视示意图。
附图中符号的简单说明如下：
10、20：晶片封装体；100：基底；100a：第一表面；100b：第二表面；101、112a：边缘；103、105、150a：开口；110：介电层；118：底胶材料层；112：密封环；114：导电垫；116：通槽；120：粘着层；130：承载基底；140：绝缘衬层；145：重布线层；150：钝化护层；155：空孔；160：导电结构；220：间隔层；230：盖板；C：晶片区；D：距离；SC：切割道区；W：宽度。
具体实施方式
以下将详细说明本发明实施例的制作与使用方式。然而应注意的是，本发明提供许多可供应用的发明概念，其可以多种特定型式实施。文中所举例讨论的特定实施例仅为制造与使用本发明的特定方式，非用以限制本发明的范围。此外，在不同实施例中可能使用重复的标号或标示。这些重复仅为了简单清楚地叙述本发明，不代表所讨论的不同实施例及/或结构之间具有任何关联性。再者，当述及一第一材料层位于一第二材料层上或之上时，包括第一材料层与第二材料层直接接触或间隔有一或更多其他材料层的情形。
本发明一实施例的晶片封装体可用以封装微机电系统晶片。然其应用不限于此，例如在本发明的晶片封装体的实施例中，其可应用于各种包含有源元件或无源元件(active or passive elements)、数字电路或模拟电路(digital or analog circuits)等集成电路的电子元件(electronic components)，例如是有关于光电元件(optoelectronic devices)、微机电系统(Micro Electro Mechanical System,MEMS)、生物辨识元件(biometric device)、微流体系统(micro fluidic systems)、或利用热、光线、电容及压力等物理量变化来测量的物理感测器(Physical Sensor)。特别是可选择使用晶圆级封装(wafer scale package,WSP)制程对影像感测元件、发光二极管(light-emittingdiodes,LEDs)、太阳能电池(solar cells)、射频元件(RF circuits)、加速计(accelerators)、陀螺仪(gyroscopes)、指纹辨识器(fingerprint recognition device)、微制动器(micro actuators)、表面声波元件(surface acoustic wave devices)、压力感测器(process sensors)或喷墨头(ink printer heads)等半导体晶片进行封装。
其中上述晶圆级封装制程主要是指在晶圆阶段完成封装步骤后，再予以切割成独立的封装体，然而，在一特定实施例中，例如将已分离的半导体晶片重新分布在一承载晶圆上，再进行封装制程，亦可称之为晶圆级封装制程。另外，上述晶圆级封装制程亦适用于通过堆迭(stack)方式安排具有集成电路的多片晶圆，以形成多层集成电路(multi-layerintegrated circuit devices)的晶片封装体。
请参照图1I及2，图1I绘示出根据本发明一实施例的晶片封装体10的剖面示意图，而图2是绘示出图1I中晶片封装体10的一部分的介电层110的仰视示意图。在本实施例中，晶片封装体10包括一基底100及设置于基底100上的一金属化层(或称作内连接层)。
在一实施例中，基底100可为一硅基底或其他半导体基底。基底100具有一第一表面100a及与其相对的一第二表面100b。再者，基底100内包括一晶片区C及沿晶片区C的边缘101(以虚线表示)延伸的一切割道区SC。亦即，切割道区SC沿晶片区C的边缘101围绕晶片区C(其中边缘101也为晶片区C与切割道区SC之间的分界线)。晶片区C内可包括一感测元件(未绘示)邻近于基底100的第一表面100a。举例来说，晶片区C内包括影像感测元件或其他适合的感测元件。在其他实施例中，晶片区C内可包括感测生物特征的元件(例如，一指纹辨识元件)、感测环境特征的元件(例如，一温度感测元件、一湿度感测元件、一压力感测元件、一电容感测元件)或其他适合的感测元件。
一金属化层位于基底100的第一表面100a上。一般而言，金属化层包括绝缘部及位于绝缘部内的导电特征部件。在本实施例中，金属化层的绝缘部可包括层间介电层(interlayer dielectric,ILD)、金属间介电层(inter-metal dielectric,IMD)、钝化护层(passivation)或前述的组合。为简化图式，此处仅绘示出单层介电层110。在一实施例中，介电层110可包括低介电常数材料。在其他实施例中，介电层110可包括无机材料，例如氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合或其他适合的绝缘材料。此处，晶片封装体10包括一晶片/晶粒，而晶片/晶粒包括基底100及介电层110。
在本实施例中，对应于切割道区SC的介电层110内具有一通槽(through groove)116邻近于晶片区C。在一实施例中，通槽116贯穿介电层110而露出基底100的第一表面100a。在其他实施例中，贯穿介电层110的通槽116进一步延伸入基底100内至一深度，其约在1微米(μm)至2微米的范围。在一实施例中，通槽116具有一宽度W(绘示于图1B)，其约在5微米至15微米的范围。通槽116沿切割道区SC的延伸方向延伸，如图2所示。亦即，通槽116也是沿晶片区C的边缘101围绕晶片区C。在其他实施例中，通槽116内可完全填满一底胶材料层(未绘示)。
在本实施例中，设置于基底100的第一表面100a上的介电层110内具有导电特征部件，例如一密封环112及一或多个导电垫114且对应于晶片区C。在一实施例中，密封环112的一边缘112a(绘示于图1A)大体上对准于切割道区SC与晶片区C之间的分界线(即，晶片区C的边缘101)，且密封环112沿切割道区SC的延伸方向延伸。亦即，密封环112也是沿晶片区C的边缘101围绕晶片区C。在一实施例中，通槽116与密封环112之间的距离D(绘示于图1B)约在5微米至10微米的范围。
再者，导电垫114可为单层导电层或为多层的导电层结构。为简化图式，此处仅绘示出单层导电垫114作为范例说明。在一实施例中，晶片区C内的感测元件可通过介电层110内的内连线结构(未绘示)而与导电垫114电性连接。
一或多个开口103自基底100的第二表面100b延伸至基底100的第一表面100a，使开口101贯穿基底100且露出邻近于基底100的第一表面100a的对应的导电垫114。在本实施例中，开口101位于第二表面100b的宽度(或口径)大于其位于第一表面100a的宽度(或口径)。因此，开口101具有倾斜的侧壁。再者，一开口105沿着基底100的侧壁延伸而围绕晶片区C且贯穿基底100。在此情形中，开口105具有倾斜的侧壁。亦即，基底100具有倾斜的边缘侧壁。在本实施例中，开口103的俯视轮廓不同于开口105的俯视轮廓。举例来说，开口103可具有圆形的俯视轮廓，而开口105具有环形的俯视轮廓，如方环形。可以理解的是，开口103及开口105可具有其他形状的俯视轮廓，而并不限定于此。
在本实施例中，晶片封装体10还包括一绝缘衬层140设置于基底100的第二表面100b上，且顺应性地延伸至开口103的侧壁及开口105的侧壁及底部上，并露出导电垫114。在一实施例中，绝缘衬层140可包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。
在本实施例中，晶片封装体10还包括一图案化的重布线层145设置于基底100的第二表面100b上方的绝缘衬层140上，且顺应性地延伸至开口103的侧壁及底部。重布线层145通过绝缘衬层140与基底100电性隔离，且经由开口103直接电性接触或间接电性连接露出的导电垫114。因此，开口101内的重布线层145也称为基底通孔电极(through substratevia,TSV)。在一实施例中，重布线层145可包括铝、铜、金、铂、镍、锡、前述的组合、导电高分子材料、导电陶瓷材料(例如，铟锡氧化物或铟锌氧化物)或其他适合的导电材料。
在本实施例中，晶片封装体10还包括一钝化护层150设置于基底100的第二表面100b上方，且填入开口103，以覆盖重布线层145。在一实施例中，钝化护层150可包括环氧树脂、绿漆(solder mask)、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、或丙烯酸酯)或其他适合的绝缘材料。
在本实施例中，钝化护层150未填满开口103，使得一空孔155形成于开口103内的重布线层145与钝化护层150之间。因此，后续制程中进行热处理时，空孔155能够作为钝化护层150与重布线层145之间的缓冲，以降低钝化护层150与重布线层145之间由于热膨胀系数不匹配所引发不必要的应力。再者，当外界温度或压力剧烈变化时，可避免钝化护层150会过度拉扯重布线层145，进而可防止靠近导电垫结构的重布线层145剥离或发生断裂。在一实施例中，空孔155与钝化护层150之间的界面具有拱形轮廓。
基底100的第二表面100b上的钝化护层150具有开口150a，以露出部分的重布线层145。再者，多个导电结构160(例如，焊球、凸块或导电柱)设置于钝化护层150的开口150a内，以与露出的重布线层145电性连接。在一实施例中，导电结构160可包括锡、铅、铜、金、镍、或前述的组合。
请参照图3E及4，图3E绘示出根据本发明另一实施例的晶片封装体20的剖面示意图，而图4是绘示出图3E中晶片封装体20的一部分的介电层110的仰视示意图，其中相同于图1I及2中的部件使用相同的标号并省略其说明。在本实施例中，晶片封装体20的结构类似于图1I中的晶片封装体10的结构。
在本实施例中，晶片封装体20中的通槽116内完全填满一底胶材料层118。再者，晶片封装体20还包括一盖板230及一间隔层(或称作围堰(dam))220。盖板230设置于基底100的第一表面100a上方。在本实施例中，盖板230可包括玻璃、石英、透明高分子材料或其他适合的透明材料。
间隔层220设置于介电层110与盖板230之间且覆盖导电垫114。在本实施例中，盖板230、间隔层220及介电层110在晶片区C上共同围绕出一空腔(未绘示)，使得空腔对应于基底100的感测元件。在其他实施例中，间隔层220覆盖对应于感测元件的介电层110，使盖板230与介电层110之间不具有空腔。在一实施例中，间隔层220大致上不吸收水气且不具有粘性。在此情形中，可通过额外的粘着胶将盖板230贴附于介电层110上。在其他实施例中，间隔层220可具有黏性。在此情形中，可通过间隔层220将盖板230贴附于介电层110上。如此一来，间隔层220可不与任何的粘着胶接触，以确保间隔层220的位置不因粘着胶而移动。在一实施例中，间隔层220可包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂(polyimide)、苯环丁烯(butylcyclobutene,BCB)、聚对二甲苯(parylene)、萘聚合物(polynaphthalenes)、氟碳化物(fluorocarbons)、丙烯酸酯(acrylates))、光阻材料或其他适合的绝缘材料。
在上述实施例中，晶片封装体10及20包括前照式(front side illumination,FSI)感测装置，然而在其他实施例中，晶片封装体10及20亦可包括背照式(back sideillumination,BSI)感测装置。
图1A至1I是绘示出根据本发明一实施例的晶片封装体10的制造方法的剖面示意图。请参照图1A，提供一基底100，其具有一第一表面100a及与其相对的一第二表面100b。基底100内包括多个晶片区C及沿每一晶片区C的边缘101(以虚线表示)延伸的一切割道区SC。为简化图式，此处仅绘示出位于割道区SC两侧的一对不完整的晶片区C。在一实施例中，基底100可为一硅基底或其他半导体基底。在另一实施例中，基底100为一硅晶圆，以利于进行晶圆级封装制程。
在本实施例中，每一晶片区C的基底100内包括一感测元件(未绘示)。感测元件可邻近于基底100的第一表面100a。在一实施例中，感测元件包括影像感测元件、感测生物特征的元件(例如，一指纹辨识元件)、感测环境特征的元件(例如，一温度感测元件、一湿度感测元件、一压力感测元件、一电容感测元件)或其他适合的感测元件。
接着，于基底100的该第一表面100a上形成一介电层110。介电层110可包括层间介电层、金属间介电层、钝化护层或其组合。为简化图式，此处仅绘示出一平整层。在一实施例中，介电层110可包括低介电常数材料。在其他实施例中，介电层110可包括无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合或其他适合的绝缘材料)。
接着，于对应晶片区C的介电层110内形成导电特征部件，例如一密封环112及一或多个导电垫114。在一实施例中，密封环112的一边缘112a大体上对准于切割道区SC与晶片区C之间的分界线(即，晶片区C的边缘101)，且密封环112沿切割道区SC的延伸方向延伸。
再者，导电垫114可为单层导电层或为多层的导电层结构。为简化图式，此处仅绘示出单层导电垫114作为范例说明。在一实施例中，晶片区C内的感测元件可通过介电层110内的内连线结构(未绘示)而与导电垫114电性连接。
接着，请参照图1B，于对应于切割道区SC的介电层110内形成一通槽116，其沿切割道区SC的延伸方向延伸，且露出基底100的第一表面100a。在其他实施例中，贯穿介电层110的通槽116可进一步延伸入基底100内至一深度，其约在1微米至2微米的范围。在一实施例中，可通过激光开槽(laser grooving)形成通槽116。在本实施例中，通槽116邻近于晶片区C的密封环112。举例来说，通槽116与密封环112之间的距离D约在5微米至10微米的范围。再者，通槽116具有一宽度W在5微米至15微米的范围。在其他实施例中，通槽116内可完全填满一底胶材料层(未绘示)。
在本实施例中，可依序进行半导体装置的前段(front end)制程(例如，在基底100内制作晶片区C及后段(back end)制程(例如，在基底100上制作介电层110、内连线结构及导电垫114)来制作前述结构。换句话说，以下晶片封装体的制造方法用于对完成后段制程的基底进行后续的封装制程。
请参照图1C，通过一粘着层120(例如，胶带)将介电层110贴合于一承载基底130(例如，玻璃)。之后，对基底100的第二表面100b进行薄化制程(例如，蚀刻制程、铣削(milling)制程、磨削(grinding)制程或研磨(polishing)制程)，以减少基底100的厚度。
接着，请参照图1D，通过微影制程及蚀刻制程(例如，干蚀刻制程、湿蚀刻制程、等离子蚀刻制程、反应性离子蚀刻制程或其他适合的制程)，于每一晶片区C的基底100内形成开口103，且在切割道区SC的基底100内形成开口105。开口103及开口105自基底100的第二表面100b延伸至基底100的第一表面100a而贯穿基底100且露出介电层110。在其他实施例中，可分别通过刻痕(notching)制程以及微影及蚀刻制程形成开口103及开口105。
在本实施例中，开口103对应于导电垫114，且开口103位于第二表面100b的宽度(或口径)大于其位于第一表面100a的宽度(或口径)，因此开口103具有倾斜的侧壁。倾斜的侧壁有助于后续形成于开口103内的膜层(例如，绝缘层及重布线层)的沉积，进而提高晶片封装体的可靠度。举例来说，由于开口103位于第一表面100a的宽度小于其位于第二表面100b的口径，因此后续形成于开口103内的膜层能够轻易地沉积于开口103的转角，以避免膜层在上述转角处发生断裂。
在本实施例中，开口105沿着相邻晶片区C之间的切割道SC延伸且贯穿基底100，使得每一晶片区C的基底100彼此分离。开口105具有倾斜的侧壁，使每一晶片区C的基底100具有倾斜的边缘侧壁。
接着，请参照图1E，可通过沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程或其他适合的制程)，在基底100的第二表面100b上形成一绝缘衬层140，绝缘衬层140顺应性地沉积于开口103及开口105的侧壁及底部上。在一实施例中，绝缘衬层140可包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、或丙烯酸酯)或其他适合的绝缘材料。接着，可通过微影制程及蚀刻制程，去除开口103底部的绝缘衬层140而露出对应的导电垫114。
接着，请参照图1F，可依序通过沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程、电镀制程、无电镀制程或其他适合的制程)、微影制程及蚀刻制程，于基底100的第二表面100b上方的绝缘衬层140上形成图案化的重布线层145。重布线层145顺应性地延伸至开口103的侧壁及底部。重布线层145通过绝缘衬层140与基底100电性隔离，且经由开口103直接电性接触或间接电性连接露出的导电垫114。在一实施例中，重布线层145可包括铝、铜、金、铂、镍、锡、前述的组合、导电高分子材料、导电陶瓷材料(例如，铟锡氧化物或铟锌氧化物)或其他适合的导电材料。
接着，请参照图1G，可通过沉积制程，在基底100的第二表面100b上形成一钝化护层150，且填入开口103，以覆盖重布线层145。在一实施例中，钝化护层150可包括环氧树脂、绿漆、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、或丙烯酸酯)或其他适合的绝缘材料。
在本实施例中，钝化护层150仅部分填充开口103，使得一空孔155形成于开口103内的重布线层145与钝化护层150之间。在一实施例中，空孔155与钝化护层150之间的界面具有拱形轮廓。在其他实施例中，钝化护层150亦可填满开口103。接着，可通过微影制程及蚀刻制程，在基底100的第二表面100b上的钝化护层150内形成多个开口150a，以露出部分的重布线层145。
之后，可通过电镀制程、网版印刷制程或其他适合的制程，在钝化护层150的开口150a内填入导电结构160(例如，焊球、凸块或导电柱)，以与露出的重布线层145电性连接。在一实施例中，导电结构160可包括锡、铅、铜、金、镍、或前述的组合。
接着，请参照图1H，自开口105底部依序切割绝缘衬层140及下方的介电层110，以将各个晶片区C分离。举例来说，可使用切割刀具或激光进行切割制程。在本实施例中，当使用切割刀具切割介电层110时，切割刀具会于介电层110内产生应力而于介电层110内形成裂缝(未绘示)。然而，由于介电层110内具有通槽116，因此裂缝仅延伸至通槽116而不会进一步延伸至对应于晶片区C的介电层110内。
在进行切割制程之后，自介电层110表面去除粘着层120及承载基底130，以形成独立的晶片封装体10。如图1I所示。
可以理解的是，虽然图1A至1I的实施例为具有前照式感测装置的晶片封装体的制造方法，然而关于晶片的外部电性连接路径(例如，基底内的开口、重布线层、保护层或其中的导电结构)的制作方法亦可应用于背照式感测装置的制程中。
图3A至3E是绘示出根据本发明另一实施例的晶片封装体20的制造方法的剖面示意图，其中相同于图1A至1I中的部件使用相同的标号并省略其说明。如图3A所示，提供如图1B实施例所示的结构。接着，于通槽116内完全填满一底胶材料层118。
接着，请参照图3B，提供一盖板230。在本实施例中，盖板230可包括玻璃、石英、透明高分子材料或其他适合的透明材料。之后，在盖板230上形成一间隔层220，并通过间隔层220将盖板230接合至基底100的第一表面100a上。间隔层220在晶片区C的基底100与盖板230之间形成一空腔(未绘示)。在其他实施例中，可先在基底100的第一表面100a上方的介电层110上形成间隔层220，之后将盖板230接合至基底100上。在其他实施例中，基底100与盖板230之间不具有空腔。
在一实施例中，可通过沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程或其他适合的制程)形成间隔层220。再者，间隔层220可包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、或丙烯酸酯)或其他适合的绝缘材料。在其他实施例中，间隔层220可包括光阻材料，且可通过微影制程而图案化，以形成空腔。
接着，请参照图3C，以盖板230作为承载基板，对基底100的第二表面100b进行薄化制程，以减少基底100的厚度。接着，通过微影制程及蚀刻制程，于每一晶片区C的基底100内形成开口103，且在切割道区SC的基底100内形成开口105，如图1D的实施例所示。
接着，请参照图3D，可利用相同或相似于图1E至1G的实施例所述的方法，于图3C所示的结构上依序形成绝缘衬层140、重布线层145、钝化护层150及位于钝化护层150的开口150a内的导电结构160。
接着，请参照图3E，自开口105底部依序切割绝缘衬层140、介电层110、间隔层220以及盖板230，以将各个晶片区C分离，以形成独立的晶片封装体20。举例来说，可使用切割刀具或激光进行切割制程。在本实施例中，当使用切割刀具切割介电层110时，切割刀具会于介电层110内产生应力而于介电层110内形成裂缝(未绘示)。然而，由于介电层110内具有通槽116及底胶材料层118，因此裂缝仅延伸至通槽116而不会进一步延伸至对应于晶片区C的介电层110内。
可以理解的是，虽然图3A至3E的实施例为具有前照式感测装置的晶片封装体的制造方法，然而关于晶片的外部电性连接路径(例如，基底内的开口、重布线层、保护层或其中的导电结构)的制作方法亦可应用于背照式感测装置的制程中。
根据本发明的上述实施例，由于介电层内的通槽有效阻挡裂缝进一步延伸至对应于晶片区的介电层内，因此可维持或改善晶片封装体可靠度及效能。再者，由于通槽可有效阻挡裂缝延伸，因此无须在切割道区进行预切割(pre-sawing)制程以及在切割道区的基底侧壁形成钝化护层来保护介电层。如此一来，可顺利去除形成于介电层上的粘着层及承载基底。或着，可避免因钝化护层形成于切割道区的基底侧壁所产生的基底翘曲(substratewarpage)问题。另外，由于无须进行预切割制程，因此不存在预切割制程与切割制程之间发生偏移的问题。如此一来，可进一步缩小晶片封装体的尺寸。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。

Claims (20)

1.一种晶片封装体，其特征在于，包括：
基底，具有第一表面及与该第一表面相对的第二表面，其中该基底具有晶片区及沿该晶片区的边缘延伸的切割道区；
介电层，设置于该基底的该第一表面上，其中对应于该切割道区的该介电层内具有通槽，且该通槽沿该切割道区的延伸方向延伸，且该通槽由该第一表面延伸入该基底内；以及
导电结构，设置于该基底的该第二表面上。
2.根据权利要求1所述的晶片封装体，其特征在于，还包括密封环，该密封环设置于该介电层内，其中该密封环的一边缘对准于该切割道区与该晶片区之间的分界线，且该密封环沿该切割道区的延伸方向延伸。
3.根据权利要求2所述的晶片封装体，其特征在于，该通槽与该密封环之间的距离在5微米至10微米的范围。
4.根据权利要求1所述的晶片封装体，其特征在于，该通槽具有宽度，该宽度在5微米至15微米的范围。
5.根据权利要求1所述的晶片封装体，其特征在于，还包括底胶材料层，该底胶材料层完全填满该通槽。
6.根据权利要求5所述的晶片封装体，其特征在于，还包括：
盖板，设置于该基底的该第一表面上方；以及
间隔层，设置于该介电层与该盖板之间。
7.根据权利要求1所述的晶片封装体，其特征在于，还包括：
导电垫，设置于该介电层内且对应于该晶片区；
重布线层，设置于该基底的该第二表面上，且延伸至该基底的开口内而电性连接该导电垫；以及
钝化护层，设置于该基底的该第二表面上方，且填入该基底的该开口内，以覆盖该重布线层，
其中该导电结构穿过该钝化护层而电性连接至该重布线层。
8.根据权利要求1所述的晶片封装体，其特征在于，该介电层包括低介电常数材料。
9.根据权利要求1所述的晶片封装体，其特征在于，该通槽延伸入该基底内的深度在1微米至2微米的范围。
10.一种晶片封装体的制造方法，其特征在于，包括：
提供基底，该基底具有第一表面及与该第一表面相对的第二表面，且具有晶片区及沿该晶片区的边缘延伸的切割道区；
于该基底的该第一表面上形成介电层；
于对应于该切割道区的该介电层内形成通槽，其中该通槽沿该切割道区的延伸方向延伸，且该通槽由该第一表面延伸入该基底内；以及
于该基底的该第二表面上形成导电结构。
11.根据权利要求10所述的晶片封装体的制造方法，其特征在于，还包括于该介电层内形成密封环，其中该密封环的一边缘对准于该切割道区与该晶片区之间的分界线，且该密封环沿该切割道区的延伸方向延伸。
12.根据权利要求11所述的晶片封装体的制造方法，其特征在于，该通槽与该密封环之间的距离在5微米至10微米的范围。
13.根据权利要求10所述的晶片封装体的制造方法，其特征在于，该通槽具有宽度，该宽度在5微米至15微米的范围。
14.根据权利要求10所述的晶片封装体的制造方法，其特征在于，通过激光开槽形成该通槽。
15.根据权利要求10所述的晶片封装体的制造方法，其特征在于，还包括于对应于该晶片区的该介电层内形成导电垫。
16.根据权利要求15所述的晶片封装体的制造方法，其特征在于，还包括于该通槽内完全填满底胶材料层。
17.根据权利要求16所述的晶片封装体的制造方法，其特征在于，还包括：
于该基底的该第一表面上方形成间隔层；以及
于该间隔层上方形成盖板，使该间隔层形成于该介电层与该盖板之间。
18.根据权利要求15所述的晶片封装体的制造方法，其特征在于，还包括：
于该基底内形成开口，以露出该导电垫；
于该基底的该第二表面上形成重布线层，且延伸至该基底的该开口内而电性连接该导电垫；以及
于该基底的该第二表面上方形成钝化护层，且填入该基底的该开口，以覆盖该重布线层，
其中该导电结构形成于该钝化护层内，以电性连接至该重布线层。
19.根据权利要求10所述的晶片封装体的制造方法，其特征在于，该介电层包括低介电常数材料。
20.根据权利要求10所述的晶片封装体的制造方法，其特征在于，该通槽延伸入该基底内的深度在1微米至2微米的范围。
CN201710165062.1A 2016-03-21 2017-03-20 晶片封装体及其制造方法 Active CN107221540B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201662311287P 2016-03-21 2016-03-21
US62/311,287 2016-03-21

Publications (2)

Publication Number Publication Date
CN107221540A CN107221540A (zh) 2017-09-29
CN107221540B true CN107221540B (zh) 2020-09-22

Family

ID=59847584

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710165062.1A Active CN107221540B (zh) 2016-03-21 2017-03-20 晶片封装体及其制造方法

Country Status (3)

Country Link
US (1) US10153237B2 (zh)
CN (1) CN107221540B (zh)
TW (1) TW201735382A (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10153237B2 (en) * 2016-03-21 2018-12-11 Xintec Inc. Chip package and method for forming the same
US10014234B2 (en) 2016-12-02 2018-07-03 Globalfoundries Inc. Semiconductor device comprising a die seal including long via lines
TWI638410B (zh) * 2017-11-14 2018-10-11 蔡宜興 降低封裝基板翹曲的方法及半成品結構
KR102600001B1 (ko) 2018-10-18 2023-11-08 삼성전자주식회사 스크라이브 레인을 포함하는 반도체 칩
CN111199887B (zh) * 2018-11-16 2021-09-14 典琦科技股份有限公司 芯片封装体的制造方法
TWI670779B (zh) * 2018-11-16 2019-09-01 典琦科技股份有限公司 晶片封裝體的製造方法
CN111463134A (zh) * 2019-01-18 2020-07-28 典琦科技股份有限公司 芯片封装体的制造方法
CN112103302A (zh) * 2019-06-18 2020-12-18 中芯国际集成电路制造(上海)有限公司 封装结构及其封装方法
US11031325B2 (en) * 2019-10-18 2021-06-08 Taiwan Semiconductor Manufacturing Co., Ltd. Low-stress passivation layer
CN116207182B (zh) * 2023-01-29 2024-03-12 北京智创芯源科技有限公司 芯片制备方法及电子器件

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101459055A (zh) * 2007-12-12 2009-06-17 卡西欧计算机株式会社 半导体器件的制造方法
CN103000586A (zh) * 2011-09-14 2013-03-27 南亚科技股份有限公司 裂缝停止结构及其形成方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7602065B2 (en) * 2007-11-30 2009-10-13 Taiwan Semiconductor Manufacturing Co., Ltd. Seal ring in semiconductor device
JP5583320B2 (ja) * 2007-12-05 2014-09-03 ピーエスフォー ルクスコ エスエイアールエル 半導体ウエハ及びその製造方法
US7704804B2 (en) * 2007-12-10 2010-04-27 International Business Machines Corporation Method of forming a crack stop laser fuse with fixed passivation layer coverage
US8426947B2 (en) * 2010-08-02 2013-04-23 Headway Technologies, Inc. Laminated semiconductor wafer, laminated chip package and method of manufacturing the same
JP2013157385A (ja) * 2012-01-27 2013-08-15 Semiconductor Components Industries Llc 半導体装置及びその自動外観検査方法
US8999816B1 (en) * 2014-04-18 2015-04-07 Applied Materials, Inc. Pre-patterned dry laminate mask for wafer dicing processes
US9711463B2 (en) * 2015-01-14 2017-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. Dicing method for power transistors
US10153237B2 (en) * 2016-03-21 2018-12-11 Xintec Inc. Chip package and method for forming the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101459055A (zh) * 2007-12-12 2009-06-17 卡西欧计算机株式会社 半导体器件的制造方法
CN103000586A (zh) * 2011-09-14 2013-03-27 南亚科技股份有限公司 裂缝停止结构及其形成方法

Also Published As

Publication number Publication date
CN107221540A (zh) 2017-09-29
TW201735382A (zh) 2017-10-01
US10153237B2 (en) 2018-12-11
US20170271276A1 (en) 2017-09-21

Similar Documents

Publication Publication Date Title
CN107221540B (zh) 晶片封装体及其制造方法
TWI629759B (zh) 晶片封裝體及其製造方法
US10056419B2 (en) Chip package having chip connected to sensing device with redistribution layer in insulator layer
US10157811B2 (en) Chip package and method for forming the same
US9196754B2 (en) Chip package and fabrication method thereof
US10424540B2 (en) Chip package and method for forming the same
US10109663B2 (en) Chip package and method for forming the same
US9997473B2 (en) Chip package and method for forming the same
US9177919B2 (en) Chip package and method for forming the same
US9379072B2 (en) Chip package and method for forming the same
CN110943052B (zh) 晶片封装体及其制造方法
US20170186712A1 (en) Chip package and method for forming the same
TW201715662A (zh) 晶片封裝體及其製造方法
US20150041995A1 (en) Chip package and fabrication method thereof
TW201642450A (zh) 晶片封裝體及其製造方法
CN110797358B (zh) 晶片封装体及其制造方法
US20160233260A1 (en) Chip package and method for forming the same
CN116504761A (zh) 晶片封装体及其制造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant