TW201735382A - 晶片封裝體及其製造方法 - Google Patents

晶片封裝體及其製造方法 Download PDF

Info

Publication number
TW201735382A
TW201735382A TW106109106A TW106109106A TW201735382A TW 201735382 A TW201735382 A TW 201735382A TW 106109106 A TW106109106 A TW 106109106A TW 106109106 A TW106109106 A TW 106109106A TW 201735382 A TW201735382 A TW 201735382A
Authority
TW
Taiwan
Prior art keywords
substrate
chip package
layer
dielectric layer
region
Prior art date
Application number
TW106109106A
Other languages
English (en)
Inventor
何彥仕
林佳昇
李柏漢
孫唯倫
Original Assignee
精材科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 精材科技股份有限公司 filed Critical 精材科技股份有限公司
Publication of TW201735382A publication Critical patent/TW201735382A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14632—Wafer-level processed structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687—Wafer level processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H01L2223/5446—Located in scribe lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/05611—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05669—Platinum [Pt] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/05686—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Electromagnetism (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本發明揭露一種晶片封裝體，包括一基底，具有一第一表面及與其相對的一第二表面，其中基底具有一晶片區及沿晶片區的邊緣延伸的一切割道區。晶片封裝體更包括一介電層，設置於基底的第一表面上，其中對應於切割道區的介電層內具有一通槽，且通槽沿切割道區的延伸方向延伸。本發明亦揭露一種晶片封裝體的製造方法。

Description

晶片封裝體及其製造方法
本發明係有關於一種晶片封裝技術，特別為有關於一種具有低介電常數(low-k)介電材料保護結構的晶片封裝體及其製造方法。
光電元件(例如，影像感測元件)在擷取影像等應用中扮演著重要的角色，其已廣泛地應用於例如數位相機(digital camera)、數位錄影機(digital video recorder)、手機(mobile phone)等電子產品中，而晶片封裝製程是形成電子產品過程中之重要步驟。晶片封裝體除了將感測晶片保護於其中，使其免受外界環境污染外，還提供感測晶片內部電子元件與外界之電性連接通路。
然而，在具有感測晶片的晶片封裝體製造中，影響封裝體可靠度的其中一個原因就是形成於晶片封裝體的低介電常數介電材料(如，金屬化層/內連接層的絕緣部)內的裂縫。舉例來說，當晶圓切割成獨立的晶片封裝體時，晶片封裝體的低介電常數介電材料因切割製程所引發的應力而於其內形成裂縫。如此一來，造成晶片封裝體可靠度及效能下降。
因此，有必要尋求一種新穎的晶片封裝體及其製造方法，其能夠解決或改善上述的問題。
本發明實施例係提供一種晶片封裝體，包括一基底，具有一第一表面及與其相對的一第二表面，其中基底具有一晶片區及沿晶片區的邊緣延伸的一切割道區。晶片封裝體更包括一介電層，設置於基底的第一表面上，其中對應於切割道區的介電層內具有一通槽，且通槽沿切割道區的延伸方向延伸。本發明亦揭露一種晶片封裝體的製造方法。
本發明實施例係提供一種晶片封裝體的製造方法，包括：提供一基底，基底具有一第一表面及與其相對的一第二表面，且具有一晶片區及沿晶片區的邊緣延伸的一切割道區；於基底的第一表面上形成一介電層；以及於對應於切割道區的介電層內形成一通槽，其中通槽沿切割道區的延伸方向延伸。
10、20‧‧‧晶片封裝體
100‧‧‧基底
100a‧‧‧第一表面
100b‧‧‧第二表面
101、112a‧‧‧邊緣
103、105、150a‧‧‧開口
110‧‧‧介電層
118‧‧‧底膠材料層
112‧‧‧密封環
114‧‧‧導電墊
116‧‧‧通槽
120‧‧‧黏著層
130‧‧‧承載基底
140‧‧‧絕緣襯層
145‧‧‧重佈線層
150‧‧‧鈍化護層
155‧‧‧空孔
160‧‧‧導電結構
220‧‧‧間隔層
230‧‧‧蓋板
C‧‧‧晶片區
D‧‧‧距離
SC‧‧‧切割道區
W‧‧‧寬度
第1A至1I圖係繪示出根據本發明一實施例之晶片封裝體的製造方法剖面示意圖。
第2圖係繪示出第1I圖中晶片封裝體的一部分的介電層底視示意圖。
第3A至3E圖係繪示出根據本發明另一實施例之晶片封裝體的製造方法剖面示意圖。
第4圖係繪示出第3E圖中晶片封裝體的一部分的介電層底視示意圖。
以下將詳細說明本發明實施例之製作與使用方 式。然應注意的是，本發明提供許多可供應用的發明概念，其可以多種特定型式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式，非用以限制本發明之範圍。此外，在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明，不代表所討論之不同實施例及/或結構之間具有任何關連性。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。
本發明一實施例之晶片封裝體可用以封裝微機電系統晶片。然其應用不限於此，例如在本發明之晶片封裝體的實施例中，其可應用於各種包含主動元件或被動元件(active or passive elements)、數位電路或類比電路(digital or analog circuits)等積體電路的電子元件(electronic components)，例如是有關於光電元件(opto electronic devices)、微機電系統(Micro Electro Mechanical System,MEMS)、生物辨識元件(biometric device)、微流體系統(micro fluidic systems)、或利用熱、光線、電容及壓力等物理量變化來測量的物理感測器(Physical Sensor)。特別是可選擇使用晶圓級封裝(wafer scale package,WSP)製程對影像感測元件、發光二極體(light-emitting diodes,LEDs)、太陽能電池(solar cells)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、指紋辨識器(fingerprint recognition device)、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力感測器(process sensors)或噴墨頭(ink printer heads)等半導體晶片進 行封裝。
其中上述晶圓級封裝製程主要係指在晶圓階段完成封裝步驟後，再予以切割成獨立的封裝體，然而，在一特定實施例中，例如將已分離之半導體晶片重新分布在一承載晶圓上，再進行封裝製程，亦可稱之為晶圓級封裝製程。另外，上述晶圓級封裝製程亦適用於藉堆疊(stack)方式安排具有積體電路之多片晶圓，以形成多層積體電路(multi-layer integrated circuit devices)之晶片封裝體。
請參照第1I及2圖，第1I圖繪示出根據本發明一實施例之晶片封裝體10的剖面示意圖，而第2圖係繪示出第1I圖中晶片封裝體10的一部分的介電層110的底視示意圖。在本實施例中，晶片封裝體10包括一基底100及設置於基底100上的一金屬化層(或稱作內連接層)。
在一實施例中，基底100可為一矽基底或其他半導體基底。基底100具有一第一表面100a及與其相對的一第二表面100b。再者，基底100內包括一晶片區C及沿晶片區C的邊緣101(以虛線表示之)延伸的一切割道區SC。亦即，切割道區SC沿晶片區C的邊緣101圍繞晶片區C(其中邊緣101也為晶片區C與切割道區SC之間的分界線)。晶片區C內可包括一感測元件(未繪示)鄰近於基底100的第一表面100a。舉例來說，晶片區C內包括影像感測元件或其他適合的感測元件。在其他實施例中，晶片區C內可包括感測生物特徵的元件(例如，一指紋辨識元件)、感測環境特徵的元件(例如，一溫度感測元件、一溼度感測元件、一壓力感測元件、一電容感測元件)或其他適合的 感測元件。
一金屬化層位於基底100的第一表面100a上。一般而言，金屬化層包括絕緣部及位於絕緣部內的導電特徵部件。在本實施例中，金屬化層的絕緣部可包括層間介電層(interlayer dielectric,ILD)、金屬間介電層(inter-metal dielectric,IMD)、鈍化護層(passivation)或前述之組合。為簡化圖式，此處僅繪示出單層介電層110。在一實施例中，介電層110可包括低介電常數材料。在其他實施例中，介電層110可包括無機材料，例如氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合或其他適合的絕緣材料。此處，晶片封裝體10包括一晶片/晶粒，而晶片/晶粒包括基底100及介電層110。
在本實施例中，對應於切割道區SC的介電層110內具有一通槽(through groove)116鄰近於晶片區C。在一實施例中，通槽116貫穿介電層110而露出基底100的第一表面100a。在其他實施例中，貫穿介電層110的通槽116進一步延伸入基底100內至一深度，其約在1微米(μm)至2微米的範圍。在一實施例中，通槽116具有一寬度W(繪示於第1B圖)，其約在5微米至15微米的範圍。通槽116沿切割道區SC的延伸方向延伸，如第2圖所示。亦即，通槽116也是沿晶片區C的邊緣101圍繞晶片區C。在其他實施例中，通槽116內可完全填滿一底膠材料層(未繪示)。
在本實施例中，設置於基底100的第一表面100a上的介電層110內具有導電特徵部件，例如一密封環112及一或多個導電墊114且對應於晶片區C。在一實施例中，密封環112的 一邊緣112a(繪示於第1A圖)大體上對準於切割道區SC與晶片區C之間的分界線(即，晶片區C的邊緣101)，且密封環112沿切割道區SC的延伸方向延伸。亦即，密封環112也是沿晶片區C的邊緣101圍繞晶片區C。在一實施例中，通槽116與密封環112之間的距離D(繪示於第1B圖)約在5微米至10微米的範圍。
再者，導電墊114可為單層導電層或為多層的導電層結構。為簡化圖式，此處僅繪示出單層導電墊114作為範例說明。在一實施例中，晶片區C內的感測元件可透過介電層110內的內連線結構(未繪示)而與導電墊114電性連接。
一或多個開口103自基底100的第二表面100b延伸至基底100的第一表面100a，使開口101貫穿基底100且露出鄰近於基底100的第一表面100a的對應的導電墊114。在本實施例中，開口101位於第二表面100b的寬度(或口徑)大於其位於第一表面100a的寬度(或口徑)。因此，開口101具有傾斜的側壁。再者，一開口105沿著基底100的側壁延伸而圍繞晶片區C且貫穿基底100。在此情形中，開口105具有傾斜的側壁。亦即，基底100具有傾斜的邊緣側壁。在本實施例中，開口103的上視輪廓不同於開口105的上視輪廓。舉例來說，開口103可具有圓形的上視輪廓，而開口105具有環形的上視輪廓，如方環形。可以理解的是，開口103及開口105可具有其他形狀的上視輪廓，而並不限定於此。
在本實施例中，晶片封裝體10更包括一絕緣襯層140設置於基底100的第二表面100b上，且順應性地延伸至開口103的側壁及開口105的側壁及底部上，並露出導電墊114。在 一實施例中，絕緣襯層140可包括環氧樹脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的絕緣材料。
在本實施例中，晶片封裝體10更包括一圖案化的重佈線層145設置於基底100的第二表面100b上方的絕緣襯層140上，且順應性地延伸至開口103的側壁及底部。重佈線層145透過絕緣襯層140與基底100電性隔離，且經由開口103直接電性接觸或間接電性連接露出的導電墊114。因此，開口101內的重佈線層145也稱為基底通孔電極(through substrate via,TSV)。在一實施例中，重佈線層145可包括鋁、銅、金、鉑、鎳、錫、前述之組合、導電高分子材料、導電陶瓷材料(例如，銦錫氧化物或銦鋅氧化物)或其他適合的導電材料。
在本實施例中，晶片封裝體10更包括一鈍化護層150設置於基底100的第二表面100b上方，且填入開口103，以覆蓋重佈線層145。在一實施例中，鈍化護層150可包括環氧樹脂、綠漆(solder mask)、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、或丙烯酸酯)或其他適合的絕緣材料。
在本實施例中，鈍化護層150未填滿開口103，使得一空孔155形成於開口103內的重佈線層145與鈍化護層150之間。因此，後續製程中進行熱處理時，空孔155能夠作為鈍化護層150與重佈線層145之間的緩衝，以降低鈍化護層150與 重佈線層145之間由於熱膨脹係數不匹配所引發不必要的應力。再者，當外界溫度或壓力劇烈變化時，可避免鈍化護層150會過度拉扯重佈線層145，進而可防止靠近導電墊結構的重佈線層145剝離或發生斷裂。在一實施例中，空孔155與鈍化護層150之間的界面具有拱形輪廓。
基底100的第二表面100b上的鈍化護層150具有開口150a，以露出部分的重佈線層145。再者，複數導電結構160(例如，焊球、凸塊或導電柱)設置於鈍化護層150的開口150a內，以與露出的重佈線層145電性連接。在一實施例中，導電結構160可包括錫、鉛、銅、金、鎳、或前述之組合。
請參照第3E及4圖，第3E圖繪示出根據本發明另一實施例之晶片封裝體20的剖面示意圖，而第4圖係繪示出第3E圖中晶片封裝體20的一部分的介電層110的底視示意圖，其中相同於第1I及2圖中的部件係使用相同的標號並省略其說明。在本實施例中，晶片封裝體20之結構類似於第1I圖中的晶片封裝體10之結構。
在本實施例中，晶片封裝體20中的通槽116內完全填滿一底膠材料層118。再者，晶片封裝體20更包括一蓋板230及一間隔層(或稱作圍堰(dam))220。蓋板230設置於基底100的第一表面100a上方。在本實施例中，蓋板230可包括玻璃、石英、透明高分子材料或其他適合的透明材料。
間隔層220設置於介電層110與蓋板230之間且覆蓋導電墊114。在本實施例中，蓋板230、間隔層220及介電層110在晶片區C上共同圍繞出一空腔(未繪示)，使得空腔對應於 基底100的感測元件。在其他實施例中，間隔層220覆蓋對應於感測元件的介電層110，使蓋板230與介電層110之間不具有空腔。在一實施例中，間隔層220大致上不吸收水氣且不具有黏性。在此情形中，可透過額外的黏著膠將蓋板230貼附於介電層110上。在其他實施例中，間隔層220可具有黏性。在此情形中，可透過間隔層220將蓋板230貼附於介電層110上。如此一來，間隔層220可不與任何的黏著膠接觸，以確保間隔層220之位置不因黏著膠而移動。在一實施例中，間隔層220可包括環氧樹脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂(polyimide)、苯環丁烯(butylcyclobutene,BCB)、聚對二甲苯(parylene)、萘聚合物(polynaphthalenes)、氟碳化物(fluorocarbons)、丙烯酸酯(acrylates))、光阻材料或其他適合的絕緣材料。
在上述實施例中，晶片封裝體10及20包括前照式(front side illumination,FSI)感測裝置，然而在其他實施例中，晶片封裝體10及20亦可包括背照式(back side illumination,BSI)感測裝置。
第1A至1I圖係繪示出根據本發明一實施例之晶片封裝體10的製造方法的剖面示意圖。請參照第1A圖，提供一基底100，其具有一第一表面100a及與其相對的一第二表面100b。基底100內包括複數個晶片區C及沿每一晶片區C的邊緣101(以虛線表示之)延伸的一切割道區SC。為簡化圖式，此處僅繪示出位於割道區SC兩側的一對不完整的晶片區C。在一實 施例中，基底100可為一矽基底或其他半導體基底。在另一實施例中，基底100為一矽晶圓，以利於進行晶圓級封裝製程。
在本實施例中，每一晶片區C的基底100內包括一感測元件(未繪示)。感測元件可鄰近於基底100的第一表面100a。在一實施例中，感測元件包括影像感測元件、感測生物特徵的元件(例如，一指紋辨識元件)、感測環境特徵的元件(例如，一溫度感測元件、一溼度感測元件、一壓力感測元件、一電容感測元件)或其他適合的感測元件。
接著，於基底100的該第一表面100a上形成一介電層110。介電層110可包括層間介電層、金屬間介電層、鈍化護層或其組合。為簡化圖式，此處僅繪示出一平整層。在一實施例中，介電層110可包括低介電常數材料。在其他實施例中，介電層110可包括無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合或其他適合的絕緣材料)。
接著，於對應晶片區C的介電層110內形成導電特徵部件，例如一密封環112及一或多個導電墊114。在一實施例中，密封環112的一邊緣112a大體上對準於切割道區SC與晶片區C之間的分界線(即，晶片區C的邊緣101)，且密封環112沿切割道區SC的延伸方向延伸。
再者，導電墊114可為單層導電層或為多層的導電層結構。為簡化圖式，此處僅繪示出單層導電墊114作為範例說明。在一實施例中，晶片區C內的感測元件可透過介電層110內的內連線結構(未繪示)而與導電墊114電性連接。
接著，請參照第1B圖，於對應於切割道區SC的介 電層110內形成一通槽116，其沿切割道區SC的延伸方向延伸，且露出基底100的第一表面100a。在其他實施例中，貫穿介電層110的通槽116可進一步延伸入基底100內至一深度，其約在1微米1微米至2微米的範圍。在一實施例中，可藉由雷射開槽(laser grooving)形成通槽116。在本實施例中，通槽116鄰近於晶片區C的密封環112。舉例來說，通槽116與密封環112之間的距離D約在5微米至10微米的範圍。再者，通槽116具有一寬度W在5微米至15微米的範圍。在其他實施例中，通槽116內可完全填滿一底膠材料層(未繪示)。
在本實施例中，可依序進行半導體裝置的前段(front end)製程(例如，在基底100內製作晶片區C及後段(back end)製程(例如，在基底100上製作介電層110、內連線結構及導電墊114)來製作前述結構。換句話說，以下晶片封裝體的製造方法係用於對完成後段製程的基底進行後續的封裝製程。
請參照第1C圖，藉由一黏著層120(例如，膠帶)將介電層110貼合於一承載基底130(例如，玻璃)。之後，對基底100的第二表面100b進行薄化製程(例如，蝕刻製程、銑削(milling)製程、磨削(grinding)製程或研磨(polishing)製程)，以減少基底100的厚度。
接著，請參照第1ID圖，透過微影製程及蝕刻製程(例如，乾蝕刻製程、濕蝕刻製程、電漿蝕刻製程、反應性離子蝕刻製程或其他適合的製程)，於每一晶片區C的基底100內形成開口103，且在切割道區SC的基底100內形成開口105。開口103及開口105自基底100的第二表面100b延伸至基底100的 第一表面100a而貫穿基底100且露出介電層110。在其他實施例中，可分別透過刻痕(notching)製程以及微影及蝕刻製程形成開口103及開口105。
在本實施例中，開口103對應於導電墊114，且開口103位於第二表面100b的寬度(或口徑)大於其位於第一表面100a的寬度(或口徑)，因此開口103具有傾斜的側壁。傾斜的側壁有助於後續形成於開口103內的膜層(例如，絕緣層及重佈線層)的沉積，進而提高晶片封裝體的可靠度。舉例來說，由於開口103位於第一表面100a的寬度小於其位於第二表面100b的口徑，因此後續形成於開口103內的膜層能夠輕易地沉積於開口103的轉角，以避免膜層在上述轉角處發生斷裂。
在本實施例中，開口105沿著相鄰晶片區C之間的切割道SC延伸且貫穿基底100，使得每一晶片區C的基底100彼此分離。開口105具有傾斜的側壁，使每一晶片區C的基底100具有傾斜的邊緣側壁。
接著，請參照第1E圖，可透過沉積製程(例如，塗佈製程、物理氣相沈積製程、化學氣相沈積製程或其他適合的製程)，在基底100的第二表面100b上形成一絕緣襯層140，絕緣襯層140順應性地沉積於開口103及開口105的側壁及底部上。在一實施例中，絕緣襯層140可包括環氧樹脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、或丙烯酸酯)或其他適合的絕緣材料。接著，可透過微影製程及蝕刻製程，去除開口103底部的 絕緣襯層140而露出對應的導電墊114。
接著，請參照第1F圖，可依序透過沉積製程(例如，塗佈製程、物理氣相沉積製程、化學氣相沉積製程、電鍍製程、無電鍍製程或其他適合的製程)、微影製程及蝕刻製程，於基底100的第二表面100b上方的絕緣襯層140上形成圖案化的重佈線層145。重佈線層145順應性地延伸至開口103的側壁及底部。重佈線層145透過絕緣襯層140與基底100電性隔離，且經由開口103直接電性接觸或間接電性連接露出的導電墊114。在一實施例中，重佈線層145可包括鋁、銅、金、鉑、鎳、錫、前述之組合、導電高分子材料、導電陶瓷材料(例如，銦錫氧化物或銦鋅氧化物)或其他適合的導電材料。
接著，請參照第1G圖，可透過沉積製程，在基底100的第二表面100b上形成一鈍化護層150，且填入開口103，以覆蓋重佈線層145。在一實施例中，鈍化護層150可包括環氧樹脂、綠漆、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、或丙烯酸酯)或其他適合的絕緣材料。
在本實施例中，鈍化護層150僅部分填充開口103，使得一空孔155形成於開口103內的重佈線層145與鈍化護層150之間。在一實施例中，空孔155與鈍化護層150之間的界面具有拱形輪廓。在其他實施例中，鈍化護層150亦可填滿開口103。接著，可透過微影製程及蝕刻製程，在基底100的第二表面100b上的鈍化護層150內形成複數開口150a，以露出部分 的重佈線層145。
之後，可透過電鍍製程、網版印刷製程或其他適合的製程，在鈍化護層150的開口150a內填入導電結構160(例如，焊球、凸塊或導電柱)，以與露出的重佈線層145電性連接。在一實施例中，導電結構160可包括錫、鉛、銅、金、鎳、或前述之組合。
接著，請參照第1H圖，自開口105底部依序切割絕緣襯層140及下方的介電層110，以將各個晶片區C分離。舉例來說，可使用切割刀具或雷射進行切割製程。在本實施例中，當使用切割刀具切割介電層110時，切割刀具會於介電層110內產生應力而於介電層110內形成裂縫(未繪示)。然而，由於介電層110內具有通槽116，因此裂縫僅延伸至通槽116而不會進一步延伸至對應於晶片區C的介電層110內。
在進行切割製程之後，自介電層110表面去除黏著層120及承載基底130，以形成獨立的晶片封裝體10。如第1I圖所示。
可以理解的是，雖然第1A至1I圖的實施例為具有前照式感測裝置之晶片封裝體的製造方法，然而關於晶片的外部電性連接路徑(例如，基底內的開口、重佈線層、保護層或其中的導電結構)的製作方法亦可應用於背照式感測裝置的製程中。
第3A至3E圖係繪示出根據本發明另一實施例之晶片封裝體20的製造方法的剖面示意圖，其中相同於第1A至1I圖中的部件係使用相同的標號並省略其說明。如第3A圖所示， 提供如第1B圖實施例所示之結構。接著，於通槽116內完全填滿一底膠材料層118。
接著，請參照第3B圖，提供一蓋板230。在本實施例中，蓋板230可包括玻璃、石英、透明高分子材料或其他適合的透明材料。之後，在蓋板230上形成一間隔層220，並透過間隔層220將蓋板230接合至基底100的第一表面100a上。間隔層220在晶片區C的基底100與蓋板230之間形成一空腔(未繪示)。在其他實施例中，可先在基底100的第一表面100a上方的介電層110上形成間隔層220，之後將蓋板230接合至基底100上。在其他實施例中，基底100與蓋板230之間不具有空腔。
在一實施例中，可透過沉積製程(例如，塗佈製程、物理氣相沈積製程、化學氣相沈積製程或其他適合的製程)形成間隔層220。再者，間隔層220可包括環氧樹脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、或丙烯酸酯)或其他適合的絕緣材料。在其他實施例中，間隔層220可包括光阻材料，且可透過微影製程而圖案化，以形成空腔。
接著，請參照第3C圖，以蓋板230作為承載基板，對基底100的第二表面100b進行薄化製程，以減少基底100的厚度。接著，透過微影製程及蝕刻製程，於每一晶片區C的基底100內形成開口103，且在切割道區SC的基底100內形成開口105，如第1D圖的實施例所示。
接著，請參照第3D圖，可利用相同或相似於第1E 至1G圖的實施例所述的方法，於第3C圖所示的結構上依序形成絕緣襯層140、重佈線層145、鈍化護層150及位於鈍化護層150的開口150a內的導電結構160。
接著，請參照第3E圖，自開口105底部依序切割絕緣襯層140、介電層110、間隔層220以及蓋板230，以將各個晶片區C分離，以形成獨立的晶片封裝體20。舉例來說，可使用切割刀具或雷射進行切割製程。在本實施例中，當使用切割刀具切割介電層110時，切割刀具會於介電層110內產生應力而於介電層110內形成裂縫(未繪示)。然而，由於介電層110內具有通槽116及底膠材料層118，因此裂縫僅延伸至通槽116而不會進一步延伸至對應於晶片區C的介電層110內。
可以理解的是，雖然第3A至3E圖的實施例為具有前照式感測裝置之晶片封裝體的製造方法，然而關於晶片的外部電性連接路徑(例如，基底內的開口、重佈線層、保護層或其中的導電結構)的製作方法亦可應用於背照式感測裝置的製程中。
根據本發明的上述實施例，由於介電層內的通槽有效阻擋裂縫進一步延伸至對應於晶片區的介電層內，因此可維持或改善晶片封裝體可靠度及效能。再者，由於通槽可有效阻擋裂縫延伸，因此無須在切割道區進行預切割(pre-sawing)製程以及在切割道區的基底側壁形成鈍化護層來保護介電層。如此一來，可順利去除形成於介電層上的黏著層及承載基底。或著，可避免因鈍化護層形成於切割道區的基底側壁所產生的基底翹曲(substrate warpage)問題。另外，由於無須進行預 切割製程，因此不存在預切割製程與切割製程之間發生偏移的問題。如此一來，可進一步縮小晶片封裝體的尺寸。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可更動與組合上述各種實施例。
10‧‧‧晶片封裝體
100‧‧‧基底
100a‧‧‧第一表面
100b‧‧‧第二表面
101‧‧‧邊緣
103、105、150a‧‧‧開口
110‧‧‧介電層
112‧‧‧密封環
114‧‧‧導電墊
116‧‧‧通槽
140‧‧‧絕緣襯層
145‧‧‧重佈線層
150‧‧‧鈍化護層
155‧‧‧空孔
160‧‧‧導電結構
C‧‧‧晶片區
SC‧‧‧切割道區

Claims (22)

  1. 一種晶片封裝體，包括：一基底，具有一第一表面及與其相對的一第二表面，其中該基底具有一晶片區及沿該晶片區的邊緣延伸的一切割道區；以及一介電層，設置於該基底的該第一表面上，其中對應於該切割道區的該介電層內具有一通槽，且該通槽沿該切割道區的延伸方向延伸。
  2. 如申請專利範圍第1項所述之晶片封裝體，更包括一密封環，設置於該介電層內，其中該密封環的一邊緣對準於該切割道區與該晶片區之間的分界線，且該密封環沿該切割道區的延伸方向延伸。
  3. 如申請專利範圍第2項所述之晶片封裝體，其中該通槽與該密封環之間的距離在5微米至10微米的範圍。
  4. 如申請專利範圍第1項所述之晶片封裝體，其中該通槽具有一寬度在5微米至15微米的範圍。
  5. 如申請專利範圍第1項所述之晶片封裝體，更包括一底膠材料層，完全填滿該通槽。
  6. 如申請專利範圍第5項所述之晶片封裝體，更包括：一蓋板，設置於該基底的該第一表面上方；以及一間隔層，設置於該介電層與該蓋板之間。
  7. 如申請專利範圍第1項所述之晶片封裝體，更包括：一導電墊，設置於該介電層內且對應於該晶片區；一重佈線層，設置於該基底的該第二表面上，且延伸至該 基底的一開口內而電性連接該導電墊；一鈍化護層，設置於該基底的該第二表面上方，且填入該基底的該開口內，以覆蓋該重佈線層；以及一導電結構，穿過該鈍化護層而電性連接至該重佈線層。
  8. 如申請專利範圍第1項所述之晶片封裝體，其中該介電層包括一低介電常數材料。
  9. 如申請專利範圍第1項所述之晶片封裝體，其中該通槽延伸入該基底內至一深度。
  10. 如申請專利範圍第9項所述之晶片封裝體，其中該深度在1微米至2微米的範圍。
  11. 一種晶片封裝體的製造方法，包括：提供一基底，該基底具有一第一表面及與其相對的一第二表面，且具有一晶片區及沿該晶片區的邊緣延伸的一切割道區；於該基底的該第一表面上形成一介電層；以及於對應於該切割道區的該介電層內形成一通槽，其中該通槽沿該切割道區的延伸方向延伸。
  12. 如申請專利範圍第11項所述之晶片封裝體的製造方法，更包括於該介電層內形成一密封環，其中該密封環的一邊緣對準於該切割道區與該晶片區之間的一分界線，且該密封環沿該切割道區的延伸方向延伸。
  13. 如申請專利範圍第12項所述之晶片封裝體的製造方法，其中該通槽與該密封環之間的距離在5微米至10微米的範圍。
  14. 如申請專利範圍第11項所述之晶片封裝體的製造方法，其 中該通槽具有一寬度在5微米至15微米的範圍。
  15. 如申請專利範圍第11項所述之晶片封裝體的製造方法，其中藉由雷射開槽形成該通槽。
  16. 如申請專利範圍第11項所述之晶片封裝體的製造方法，更包括於對應於該晶片區的該介電層內形成一導電墊。
  17. 如申請專利範圍第16項所述之晶片封裝體的製造方法，更包括於該通槽內完全填滿一底膠材料層。
  18. 如申請專利範圍第17項所述之晶片封裝體的製造方法，更包括：於該基底的該第一表面上方形成一間隔層；以及於該間隔層上方形成一蓋板，使該間隔層形成於該介電層與該蓋板之間。
  19. 如申請專利範圍第16項所述之晶片封裝體的製造方法，更包括：於該基底內形成一開口，以露出該導電墊；於該基底的該第二表面上形成一重佈線層，且延伸至該基底的該開口內而電性連接該導電墊；於該基底的該第二表面上方形成一鈍化護層，且填入該基底的該開口，以覆蓋該重佈線層；以及於該鈍化護層內形成一導電結構，以電性連接至該重佈線層。
  20. 如申請專利範圍第11項所述之晶片封裝體的製造方法，其中該介電層包括一低介電常數材料。
  21. 如申請專利範圍第11項所述之晶片封裝體的製造方法，其 中該通槽延伸入該基底內至一深度。
  22. 如申請專利範圍第21項所述之晶片封裝體的製造方法，其中該深度在1微米至2微米的範圍。
TW106109106A 2016-03-21 2017-03-20 晶片封裝體及其製造方法 TW201735382A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US201662311287P 2016-03-21 2016-03-21

Publications (1)

Publication Number Publication Date
TW201735382A true TW201735382A (zh) 2017-10-01

Family

ID=59847584

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106109106A TW201735382A (zh) 2016-03-21 2017-03-20 晶片封裝體及其製造方法

Country Status (3)

Country Link
US (1) US10153237B2 (zh)
CN (1) CN107221540B (zh)
TW (1) TW201735382A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI638410B (zh) * 2017-11-14 2018-10-11 蔡宜興 降低封裝基板翹曲的方法及半成品結構

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10153237B2 (en) * 2016-03-21 2018-12-11 Xintec Inc. Chip package and method for forming the same
US10014234B2 (en) 2016-12-02 2018-07-03 Globalfoundries Inc. Semiconductor device comprising a die seal including long via lines
KR102600001B1 (ko) 2018-10-18 2023-11-08 삼성전자주식회사 스크라이브 레인을 포함하는 반도체 칩
CN111199887B (zh) * 2018-11-16 2021-09-14 典琦科技股份有限公司 芯片封装体的制造方法
TWI670779B (zh) * 2018-11-16 2019-09-01 典琦科技股份有限公司 晶片封裝體的製造方法
CN111463134A (zh) * 2019-01-18 2020-07-28 典琦科技股份有限公司 芯片封装体的制造方法
CN112103302A (zh) * 2019-06-18 2020-12-18 中芯国际集成电路制造(上海)有限公司 封装结构及其封装方法
US11031325B2 (en) * 2019-10-18 2021-06-08 Taiwan Semiconductor Manufacturing Co., Ltd. Low-stress passivation layer
CN116207182B (zh) * 2023-01-29 2024-03-12 北京智创芯源科技有限公司 芯片制备方法及电子器件

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7602065B2 (en) * 2007-11-30 2009-10-13 Taiwan Semiconductor Manufacturing Co., Ltd. Seal ring in semiconductor device
JP5583320B2 (ja) * 2007-12-05 2014-09-03 ピーエスフォー ルクスコ エスエイアールエル 半導体ウエハ及びその製造方法
US7704804B2 (en) * 2007-12-10 2010-04-27 International Business Machines Corporation Method of forming a crack stop laser fuse with fixed passivation layer coverage
JP4596001B2 (ja) * 2007-12-12 2010-12-08 カシオ計算機株式会社 半導体装置の製造方法
US8426947B2 (en) * 2010-08-02 2013-04-23 Headway Technologies, Inc. Laminated semiconductor wafer, laminated chip package and method of manufacturing the same
US8963282B2 (en) * 2011-09-14 2015-02-24 Nanya Technology Corp. Crack stop structure and method for forming the same
JP2013157385A (ja) * 2012-01-27 2013-08-15 Semiconductor Components Industries Llc 半導体装置及びその自動外観検査方法
US8999816B1 (en) * 2014-04-18 2015-04-07 Applied Materials, Inc. Pre-patterned dry laminate mask for wafer dicing processes
US9711463B2 (en) * 2015-01-14 2017-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. Dicing method for power transistors
US10153237B2 (en) * 2016-03-21 2018-12-11 Xintec Inc. Chip package and method for forming the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI638410B (zh) * 2017-11-14 2018-10-11 蔡宜興 降低封裝基板翹曲的方法及半成品結構

Also Published As

Publication number Publication date
CN107221540B (zh) 2020-09-22
CN107221540A (zh) 2017-09-29
US10153237B2 (en) 2018-12-11
US20170271276A1 (en) 2017-09-21

Similar Documents

Publication Publication Date Title
TWI629759B (zh) 晶片封裝體及其製造方法
TWI614852B (zh) 晶片封裝體及其製造方法
TWI597813B (zh) 晶片封裝體及其製造方法
TWI646671B (zh) 晶片封裝體及其製造方法
TW201735382A (zh) 晶片封裝體及其製造方法
US10157811B2 (en) Chip package and method for forming the same
TWI565015B (zh) 晶片封裝體及其製造方法
US9997473B2 (en) Chip package and method for forming the same
TW201543641A (zh) 晶片封裝體及其製造方法
TWI550794B (zh) 晶片封裝體及其製造方法
TWI642149B (zh) 晶片封裝體及其製造方法
TWI717846B (zh) 晶片封裝體及其製造方法
TW201742200A (zh) 晶片封裝體及其製造方法
TWI620284B (zh) 晶片封裝體及其製造方法
TWI741327B (zh) 晶片封裝體及其製造方法
TWI593069B (zh) 晶片封裝體及其製造方法
TW202331956A (zh) 晶片封裝體及其製造方法