TWI550794B - 晶片封裝體及其製造方法 - Google Patents

晶片封裝體及其製造方法 Download PDF

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Publication number
TWI550794B
TWI550794B TW103144009A TW103144009A TWI550794B TW I550794 B TWI550794 B TW I550794B TW 103144009 A TW103144009 A TW 103144009A TW 103144009 A TW103144009 A TW 103144009A TW I550794 B TWI550794 B TW I550794B
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Taiwan
Prior art keywords
opening
substrate
chip package
conductive pad
layer
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TW103144009A
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English (en)
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TW201624648A (zh
Inventor
劉滄宇
李柏漢
簡瑋銘
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精材科技股份有限公司
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Priority to TW103144009A priority Critical patent/TWI550794B/zh
Priority to CN201510809457.1A priority patent/CN105720040B/zh
Priority to US14/958,672 priority patent/US9613919B2/en
Publication of TW201624648A publication Critical patent/TW201624648A/zh
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Publication of TWI550794B publication Critical patent/TWI550794B/zh

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Description

晶片封裝體及其製造方法
本發明係有關於一種晶片封裝技術，特別為有關於一種晶片封裝體及其製造方法。
晶片封裝製程是形成電子產品過程中之重要步驟。晶片封裝體除了將晶片保護於其中，使其免受外界環境污染外，還提供晶片內部電子元件與外界之電性連接通路。
一般的晶片封裝體中，通常將導電層與信號接墊的表面接觸，以形成外部電性連接的導電路徑。
然而，上述信號接墊與導電層之間的導電性不佳，且結構強度不足，進而影響晶片封裝體的品質。
因此，有必要尋求一種新穎的晶片封裝體及其製造方法，其能夠解決或改善上述的問題。
本發明實施例係提供一種晶片封裝體，包括一基底，其具有一第一表面及與其相對的一第二表面。一介電層設置於基底的第一表面上，其中介電層內包括一導電墊結構。一第一開口貫穿基底，並露出導電墊結構的一表面。一第二開口與第一開口連通，且貫穿導電墊結構。一重佈線層順應性設置於第一開口的一側壁及導電墊結構的表面上，並填入第二開 口。
本發明實施例係提供一種晶片封裝體的製造方法，包括提供一基底，其具有一第一表面及與其相對的一第二表面。基底的第一表面上具有一介電層，其中介電層內包括一導電墊結構。形成一第一開口，其貫穿基底且露出導電墊結構的一表面。形成一第二開口，其與第一開口連通，且貫穿導電墊結構。在第一開口的一側壁及導電墊結構的表面上順應性形成一重佈線層，並填入第二開口。
100、180‧‧‧基底
100a、180a‧‧‧第一表面
100b、180b‧‧‧第二表面
110‧‧‧元件區
120‧‧‧晶片區
130‧‧‧介電層
140‧‧‧虛線
160‧‧‧導電墊結構
160a、160b、160c‧‧‧導電墊
200‧‧‧光學元件
220‧‧‧蓋板
240‧‧‧間隔層
260、380‧‧‧空腔
280‧‧‧第一開口
300‧‧‧絕緣層
320‧‧‧第二開口
340‧‧‧重佈線層
360‧‧‧鈍化保護層
400‧‧‧導電結構
第1A至1E圖係繪示出根據本發明一實施例之晶片封裝體的製造方法的剖面示意圖。
第2及3圖係繪示出根據本發明各種實施例之晶片封裝體的剖面示意圖。
以下將詳細說明本發明實施例之製作與使用方式。然應注意的是，本發明提供許多可供應用的發明概念，其可以多種特定型式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式，非用以限制本發明之範圍。此外，在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明，不代表所討論之不同實施例及/或結構之間具有任何關連性。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。
本發明一實施例之晶片封裝體可用以封裝微機電系統晶片。然其應用不限於此，例如在本發明之晶片封裝體的實施例中，其可應用於各種包含主動元件或被動元件(active or passive elements)、數位電路或類比電路(digital or analog circuits)等積體電路的電子元件(electronic components)，例如是有關於光電元件(opto electronic devices)、微機電系統(Micro Electro Mechanical System，MEMS)、生物辨識元件(biometric device)、微流體系統(micro fluidic systems)、或利用熱、光線、電容及壓力等物理量變化來測量的物理感測器(Physical Sensor)。特別是可選擇使用晶圓級封裝(wafer scale package，WSP)製程對影像感測元件、發光二極體(light-emitting diodes，LEDs)、太陽能電池(solar cells)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、指紋辨識器(fingerprint recognition device)、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力感測器(process sensors)或噴墨頭(ink printer heads)等半導體晶片進行封裝。
其中上述晶圓級封裝製程主要係指在晶圓階段完成封裝步驟後，再予以切割成獨立的封裝體，然而，在一特定實施例中，例如將已分離之半導體晶片重新分布在一承載晶圓上，再進行封裝製程，亦可稱之為晶圓級封裝製程。另外，上述晶圓級封裝製程亦適用於藉堆疊(stack)方式安排具有積體電路之多片晶圓，以形成多層積體電路(multi-layer integrated circuit devices)之晶片封裝體。
請參照第1E圖，其繪示出根據本發明一實施例之晶片封裝體的剖面示意圖。為了說明本發明實施例，此處使用背照式(backside illumination，BSI)感測裝置作為範例。然而，本發明實施例不限定於任何特定的應用。在本實施例中，晶片封裝體包括一基底180、一介電層130、一第一開口280、一第二開口320及一重佈線層(redistribution layer，RDL)340。基底180具有一第一表面180a及與其相對的一第二表面180b。在一實施例中，基底180可為一矽基底或其他適合的基底。
介電層130設置於基底180的第一表面180a上，且介電層130內包括一個或一個以上的導電墊結構160。在本實施例中，介電層130可由一層或多層介電材料(例如，二氧化矽、氮化物、氧化物、氮氧化物貨其他適合的介電材料)所構成。在一實施例中，導電墊結構160可包括單一導電墊或一個以上垂直堆疊的導電墊，且可由導電材料(例如，銅、鋁或其合金)所構成。為簡化圖式，此處僅以三個垂直堆疊的導電墊160a、160b及160c作為範例說明，且僅繪示出單一介電層130內的兩個導電墊結構160作為範例說明。導電墊160a、導電墊160b及導電墊160c可透過介電層130互相絕緣，且透過導電插塞(未繪示)互相電性連接。在本實施例中，導電墊160a、導電墊160b及導電墊160c依序沿著自第二表面180b朝第一表面180a的方向垂直堆疊。
第一開口280自基底180的第二表面180b朝第一表面180a延伸而貫穿基底180，並進一步延伸至介電層130內，因而露出導電墊結構160中的導電墊160a的一表面。在一實施例 中，第一開口280的側壁傾斜於基底180的第一表面180a。在其他實施例中，第一開口280的側壁可大致上垂直於基底180的第一表面180a。
第二開口320自導電墊160a的表面(即，第一開口280的底部)延伸而貫穿導電墊結構160中的所有導電墊160a、160b及160c，因而露出導電墊結構160的內部。在一實施例中，第二開口320的側壁大致上垂直於基底180的第一表面180a。在其他實施例中，第二開口320的側壁可傾斜於基底180的第一表面180a。在本實施例中，第二開口320與第一開口280連通，且第二開口320的直徑小於第一開口280的直徑。
一絕緣層300順應性設置於基底180的第二表面180b上，且延伸至第一開口280內，並暴露出導電墊160a的表面。在本實施例中，絕緣層300可包括環氧樹脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂(polyimide)、苯環丁烯(butylcyclobutene，BCB)、聚對二甲苯(parylene)、萘聚合物(polynaphthalenes)、氟碳化物(fluorocarbons)、丙烯酸酯(acrylates))或其他適合的絕緣材料。
圖案化的重佈線層340設置於絕緣層300上，且順應性延伸至第一開口280的側壁及底部上(亦即，重佈線層340延伸至導電墊160a的表面上)，並進一步填滿第二開口320。重佈線層340可經由第一開口280直接電性接觸或間接電性連接露出的導電墊160a，且亦可經由第二開口320直接電性接觸或間接電性連接露出的所有導電墊160a、160b及160c的內部。另 外，當基底180包括半導體材料(例如，矽)時，第一開口280內的重佈線層340也稱為矽通孔電極(through silicon via，TSV)，且重佈線層340可透過絕緣層300與半導體材料電性隔離。在一實施例中，重佈線層340可包括銅、鋁、金、鉑、鎳、錫、前述之組合、導電高分子材料、導電陶瓷材料(例如，氧化銦錫或氧化銦鋅)或其他適合的導電材料。
一鈍化保護層360設置於絕緣層300上，且覆蓋重佈線層340，並填入第一開口280內。在一實施例中，鈍化保護層360與第一開口280內的重佈線層340之間具有一空腔380，位於第一開口280的底部。在其他實施例中，鈍化保護層360可填滿第一開口280。鈍化保護層360具有開口(未繪示)，露出位於第二表面180b上的重佈線層340的一部分。在本實施例中，鈍化保護層360可包括環氧樹脂、綠漆(solder mask)、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)、光阻材料或其他適合的絕緣材料。
一導電結構400設置於鈍化保護層360的開口內，以電性連接露出的重佈線層340。在本實施例中，導電結構400可為凸塊(例如，接合球或導電柱)或其他適合的導電結構，且可包括錫、鉛、銅、金、鎳、前述之組合或其他適合的導電材料。
在本實施例中，晶片封裝體還包括另一基底100，設置於介電層130上，基底100具有一第一表面100a(可視為前 側)及與其相對的一第二表面100b(可視為背側)。在本實施例中，介電層130位於基底100的第一表面100a與基底180的第一表面180a之間，亦即基底100的第一表面100a鄰近於導電墊結構160中的導電墊160c(可視為底層導電墊)，而基底180的第一表面180a鄰近於導電墊結構160中的導電墊160a(可視為頂層導電墊)。在一實施例中，基底100可為一矽基底或其他半導體基底。
在本實施例中，基底100為一裝置基底，且包括一元件區110。元件區110可包括影像感測元件(例如，光電二極體(photodiode)、光電晶體(phototransistor)或其他光感測器)。再者，基底100內可具有控制上述影像感測元件的積體電路(例如，互補型金屬氧化物半導體電晶體(complementary metal oxide semiconductor，CMOS)、電阻或其他的半導體元件)，其與介電層130內的導電墊結構160電性連接。為了簡化圖式，此處僅繪示出平整的元件區110及光學元件200，且僅以虛線140表示元件區110與導電墊結構160之間的電性連接。
一光學元件200(例如，微透鏡陣列、濾光層或其他適合的光學元件)可選擇性設置於基底100的第二表面100b(即，背側)上。一蓋板220設置於基底100的第二表面100b上，以保護光學元件200。在本實施例中，蓋板220可包括玻璃或其他適合的透明材料。再者，基底100與蓋板220之間具有一間隔層(或稱作圍堰(dam))240，其圍繞光學元件200，且於基底100與蓋板220之間形成一空腔260。在一實施例中，間隔層240大致上不吸收水氣。在一實施例中，間隔層240不具有黏性， 因此間隔層240可透過額外的黏著膠，以將蓋板220貼附於基底100上。在另一實施例中，間隔層240可具有黏性，因此間隔層240可不與任何的黏著膠接觸，以確保間隔層240之位置不因黏著膠而移動。同時，由於不需使用黏著膠，可避免黏著膠溢流而污染光學元件200。在本實施例中，間隔層240可包括環氧樹脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)、光阻材料或其他適合的絕緣材料。
請參照第2及3圖，其繪示出根據本發明各種實施例之晶片封裝體的剖面示意圖，其中相同於前述第1E圖的實施例的部件係使用相同的標號並省略其說明。第2及3圖的實施例係使用前照式(frontside illumination，FSI)感測裝置作為範例說明。在第2圖的實施例中，晶片封裝體包括一基底100、一介電層130、一第一開口280、一第二開口320及一重佈線層340。基底100具有一第一表面100a(可視為前側)及與其相對的一第二表面100b(可視為背側)。在本實施例中，基底100為一裝置基底，且包括具有影像感測元件的一元件區110。
介電層130設置於基底100的第一表面100a上，且包括導電墊結構160。導電墊結構160由垂直堆疊的導電墊160a(可視為頂層導電墊)、導電墊160b及導電墊160c(可視為底層導電墊)所構成，且與元件區110電性連接(如虛線140所示)。
一光學元件200(例如，微透鏡陣列、濾光層或其他適合的光學元件)可選擇性設置於介電層130及基底100的第一 表面100a(即，前側)上。一蓋板220設置於介電層130上，以保護光學元件200。在本實施例中，介電層130位於蓋板220與基底100之間。再者，介電層130與蓋板220之間具有一間隔層(或稱作圍堰)240，其圍繞光學元件200，且於介電層130與蓋板220之間形成一空腔260。
第一開口280自基底100的第二表面100b朝第一表面100a延伸而貫穿基底100，並進一步延伸至介電層130內，因而露出導電墊結構160中的底層導電墊160c的一表面。第二開口320自底層導電墊160c的表面(即，第一開口280的底部)朝蓋板220延伸，且同時貫穿導電墊結構160中的所有導電墊160a、160b及160c，因而露出導電墊結構160的內部。在本實施例中，第二開口320與第一開口280連通，且第二開口320的直徑小於第一開口280的直徑。
絕緣層300順應性設置於基底100的第二表面100b上，且延伸至第一開口280內，並暴露出導電墊160c的表面。圖案化的重佈線層340設置於絕緣層300上，且順應性延伸至第一開口280的側壁及底部上(亦即，重佈線層340延伸至導電墊160c的表面)，並進一步填滿第二開口320。重佈線層340可經由第一開口280直接電性接觸或間接電性連接露出的導電墊160c，且亦可經由第二開口320直接電性接觸或間接電性連接露出的所有導電墊160a、160b及160c的內部。在本實施例中，第一開口280內的重佈線層340也稱為矽通孔電極。
鈍化保護層360設置於絕緣層300上，且覆蓋重佈線層340，並填入第一開口280內。在本實施例中，鈍化保護層 360可填滿或不填滿第一開口280。鈍化保護層360具有開口(未繪示)，露出位於第二表面100b上的重佈線層340的一部分。導電結構400設置於鈍化保護層360的開口內，以電性連接露出的重佈線層340。
第3圖中的晶片封裝體之結構類似於第2圖中的晶片封裝體之結構，差異在於第3圖中的第二開口320朝蓋板220延伸而貫穿導電墊結構160及介電層130，並進一步延伸至間隔層240內。
根據本發明的上述實施例，由於基底內具有第二開口，自頂層或底層導電墊的表面(即，第一開口的底部)延伸而貫穿所有導電墊，且露出所有導電墊的內部，因此重佈線層不僅直接電性接觸頂層或底層導電墊的表面，更能夠直接電性接觸所有導電墊的內部，進而增加重佈線層與導電墊結構的接觸面積且提升導電性。
再者，由於重佈線層透過第二開口而貫穿且嵌入所有導電墊的內部，進一步增加了重佈線層與導電墊結構之間的結構強度，因此能夠提升晶片封裝體的可靠度或品質。
以下配合第1A至1E圖說明本發明一實施例之晶片封裝體的製造方法，其中第1A至1E圖係繪示出根據本發明一實施例之晶片封裝體的製造方法的剖面示意圖。為了說明本發明實施例，此處使用背照式(BSI)感測裝置作為範例。然而，本發明實施例不限定於任何特定的應用。
請參照第1A圖，提供一基底100、一基底180及基底100與基底180之間的一介電層130。基底100具有一第一表面 100a(可視為前側)及與其相對的一第二表面100b(可視為背側)，且包括複數晶片區。為簡化圖式，此處僅繪示出基底100的單一晶片區120。在一實施例中，基底100可為一矽基底或其他半導體基底。舉例來說，基底100可為一矽晶圓，以利於進行晶圓級封裝製程。在本實施例中，基底100為一裝置基底，且每一晶片區120內的基底100包括一元件區110。元件區110可包括影像感測元件(例如，光電二極體、光電晶體或其他光感測器)。再者，基底100內可具有控制上述影像感測元件的積體電路(例如，互補型金屬氧化物半導體電晶體(complementary metal oxide semiconductor，CMOS)、電阻或其他的半導體元件)。為了簡化圖式，此處僅繪示出平整的元件區110。
基底180具有一第一表面180a及與其相對的一第二表面180b。在一實施例中，基底180可為一矽基底或其他適合的基底。
介電層130位於基底100的第一表面100a與基底180的第一表面180a之間。在本實施例中，介電層130可由一層或多層介電材料(例如，二氧化矽、氮化物、氧化物、氮氧化物貨其他適合的介電材料)所構成。在本實施例中，每一晶片區120內的介電層130中具有一個或一個以上的導電墊結構160，與基底100內的積體電路及元件區110電性連接。在一實施例中，導電墊結構160可包括單一導電墊或一個以上垂直堆疊的導電墊，且可由導電材料(例如，銅、鋁或其合金)所構成。為簡化圖式，此處僅以三個垂直堆疊的導電墊160a、160b及160c作為範例說明，且僅繪示出基底100的單一晶片區120內的 兩個導電墊結構160作為範例說明，並以虛線140表示元件區110與導電墊結構160之間的電性連接。導電墊160a、導電墊160b及導電墊160c可透過介電層130互相絕緣，且透過導電插塞(未繪示)互相電性連接。在本實施例中，導電墊160a、導電墊160b及導電墊160c依序沿著自基底180朝基底100的方向垂直堆疊。因此，基底100的第一表面100a鄰近於導電墊結構160中的導電墊160c(可視為底層導電墊)，而基底180的第一表面180a鄰近於導電墊結構160中的導電墊160a(可視為頂層導電墊)。
在本實施例中，可選擇性在每一晶片區120內的基底100的第二表面100b(即，背側)上設置一光學元件200(例如，微透鏡陣列、濾光層或其他適合的光學元件)。為了簡化圖式，此處僅繪示出平整的光學元件200。接著，以基底180作為支撐，將一蓋板220貼附於基底100的第二表面100b上，以保護光學元件200。在本實施例中，蓋板220可包括玻璃或其他適合的透明材料。基底100與蓋板220之間具有一間隔層(或稱作圍堰)240，其圍繞光學元件200，且於每一晶片區120內的基底100與蓋板220之間形成一空腔260。在一實施例中，間隔層240大致上不吸收水氣。在一實施例中，間隔層240不具有黏性，因此間隔層240可透過額外的黏著膠，以將蓋板220貼附於基底100上。在另一實施例中，間隔層240可具有黏性，因此間隔層240可不與任何的黏著膠接觸，以確保間隔層240之位置不因黏著膠而移動。同時，由於不需使用黏著膠，可避免黏著膠溢流而污染光學元件200。在本實施例中，間隔層240可包括環氧樹 脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)、光阻材料或其他適合的絕緣材料。
請參照第1B圖，可透過微影製程及蝕刻製程(例如，乾蝕刻製程、濕蝕刻製程、電漿蝕刻製程、反應性離子蝕刻製程或其他適合的製程)，在每一晶片區120內形成複數第一開口280。第一開口280自基底180的第二表面180b朝第一表面180a延伸而貫穿基底180，並進一步延伸至介電層130內，因而露出導電墊結構160中的頂層導電墊160a的一表面。另外，在形成第一開口280之前，可選擇性對基底180的第二表面180b進行薄化製程(例如，蝕刻製程、銑削(milling)製程、機械研磨(mechanical grinding)製程或化學機械研磨(chemical mechanical polishing)製程)，以減少基底180的厚度。
接著，可透過沉積製程(例如，塗佈製程、物理氣相沈積製程、化學氣相沈積製程或其他適合的製程)，在基底180的第二表面180b上順應性形成一絕緣層300，其延伸至第一開口280的側壁及底部上。在本實施例中，絕緣層300可包括環氧樹脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的絕緣材料。
請參照第1C圖，可透過微影製程及蝕刻製程(例如，乾蝕刻製程、濕蝕刻製程、電漿蝕刻製程、反應性離子蝕 刻製程或其他適合的製程)，去除第一開口280的底部上的絕緣層300，以暴露出導電墊160a的表面。接著，可透過雷射鑽孔(laser drilling)製程，在每一晶片區120內形成複數第二開口320。第二開口320自頂層導電墊160a的表面(即，第一開口280的底部)延伸，並同時貫穿導電墊結構160中的所有導電墊160a、160b及160c，因而露出導電墊結構160的內部。在本實施例中，第二開口320與第一開口280連通，且第二開口320的直徑小於第一開口280的直徑。
請參照第1D圖，可透過沉積製程(例如，塗佈製程、物理氣相沉積製程、化學氣相沉積製程、電鍍製程、無電鍍製程或其他適合的製程)、微影製程及蝕刻製程，在絕緣層300上形成圖案化的重佈線層340。
重佈線層340順應性延伸至第一開口280的側壁及底部上(亦即，重佈線層340延伸至導電墊160a露出的表面上)，並進一步填滿第二開口320。重佈線層340可經由第一開口280直接電性接觸或間接電性連接露出的導電墊160a，且亦可經由第二開口320直接電性接觸或間接電性連接露出的所有導電墊160a、160b及160c的內部。另外，當基底180包括半導體材料(例如，矽)時，第一開口280內的重佈線層340也稱為矽通孔電極，且重佈線層340可透過絕緣層300與半導體材料電性隔離。在一實施例中，重佈線層340可包括銅、鋁、金、鉑、鎳、錫、前述之組合、導電高分子材料、導電陶瓷材料(例如，氧化銦錫或氧化銦鋅)或其他適合的導電材料。
在本實施例中，重佈線層透過第二開口而嵌入所 有導電墊的內部，進一步增加了重佈線層與導電墊結構之間的接合強度，且避免重佈線層與導電墊之間發生膜層剝離的問題，因此能夠提升晶片封裝體的可靠度。
請參照第1E圖，可透過沉積製程，在絕緣層300上形成一鈍化保護層360，其覆蓋重佈線層340，並填入第一開口280內。在一實施例中，鈍化保護層360與第一開口280內的重佈線層340之間具有一空腔380，可避免鈍化保護層360的應力過大而影響重佈線層340。在其他實施例中，鈍化保護層360可填滿第一開口280。在本實施例中，鈍化保護層360可包括環氧樹脂、綠漆、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的絕緣材料。在另一實施例中，鈍化保護層360可包括光阻材料，且可透過曝光及顯影製程，形成露出重佈線層340的開口。
接著，可透過微影製程及蝕刻製程，在每一晶片區120中的鈍化保護層360內形成開口(未繪示)，露出位於第二表面180b上的重佈線層340的一部分。接著，在鈍化保護層360的開口內形成導電結構400，以電性連接露出的重佈線層340。舉例來說，可透過電鍍製程、網版印刷製程或其他適合的製程，在鈍化保護層360的開口內形成焊料(solder)，且進行迴焊(reflow)製程，以形成導電結構400。在本實施例中，導電結構400可為凸塊(例如，接合球或導電柱)或其他適合的導電結構，且可包括錫、鉛、銅、金、鎳、前述之組合或其他適合的導電 材料。
接著，沿著相鄰晶片區120之間的切割道(未繪示)，對蓋板220、基底100、介電層130及基底180進行切割製程，以形成複數獨立的晶片封裝體。
可以理解的是，上述晶片封裝體的製造方法並不限定於背照式感測裝置，其亦可應用於前照式感測裝置(如第2及3圖所示)或其他感測裝置。舉例來說，上述形成第二開口的製造方法可應用於具有生物特徵感測元件(例如，指紋辨識元件)或環境特徵感測元件(例如，溫度感測元件、溼度感測元件、壓力感測元件)的晶片封裝體。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可更動與組合上述各種實施例。
100、180‧‧‧基底
100a、180a‧‧‧第一表面
100b、180b‧‧‧第二表面
110‧‧‧元件區
120‧‧‧晶片區
130‧‧‧介電層
140‧‧‧虛線
160‧‧‧導電墊結構
160a、160b、160c‧‧‧導電墊
200‧‧‧光學元件
220‧‧‧蓋板
240‧‧‧間隔層
260、380‧‧‧空腔
280‧‧‧第一開口
300‧‧‧絕緣層
320‧‧‧第二開口
340‧‧‧重佈線層
360‧‧‧鈍化保護層
400‧‧‧導電結構

Claims (22)

  1. 一種晶片封裝體，包括：一基底，具有一第一表面及與其相對的一第二表面；一介電層，設置於該基底的該第一表面上，其中該介電層內包括一導電墊結構；一第一開口，貫穿該基底，並露出該導電墊結構的一表面；一第二開口，與該第一開口連通，且貫穿該導電墊結構；以及一重佈線層，順應性設置於該第一開口的一側壁及該導電墊結構的該表面上，並填入該第二開口。
  2. 如申請專利範圍第1項所述之晶片封裝體，其中該第二開口的直徑小於該第一開口的直徑。
  3. 如申請專利範圍第1項所述之晶片封裝體，其中該重佈線層填滿該第二開口。
  4. 如申請專利範圍第1項所述之晶片封裝體，其中該導電墊結構包括垂直堆疊的複數導電墊，且其中該第一開口露出該等導電墊其中一者的一表面，且該第二開口自該等導電墊其中一者的該表面延伸而貫穿該等導電墊。
  5. 如申請專利範圍第1項所述之晶片封裝體，更包括一鈍化保護層，設置於該第一開口內的該重佈線層上。
  6. 如申請專利範圍第5項所述之晶片封裝體，其中該鈍化保護層與該重佈線層之間具有一空腔。
  7. 如申請專利範圍第1項所述之晶片封裝體，更包括：一蓋板，其中該介電層位於該蓋板與該基底之間；以及 一間隔層，設置於該蓋板與該介電層之間。
  8. 如申請專利範圍第7項所述之晶片封裝體，其中該第二開口更延伸至該間隔層內。
  9. 如申請專利範圍第1項所述之晶片封裝體，更包括一另一基底，其具有一元件區，與該導電墊結構電性連接，其中該介電層位於該另一基底與該基底之間。
  10. 如申請專利範圍第1項所述之晶片封裝體，其中該基底內具有一元件區，與該導電墊結構電性連接。
  11. 一種晶片封裝體的製造方法，包括：提供一基底，其具有一第一表面及與其相對的一第二表面，且該基底的該第一表面上具有一介電層，其中該介電層內包括一導電墊結構；形成一第一開口，其貫穿該基底且露出該導電墊結構的一表面；形成一第二開口，其與該第一開口連通，且貫穿該導電墊結構；以及在該第一開口的一側壁及該導電墊結構的該表面上順應性形成一重佈線層，並填入該第二開口。
  12. 如申請專利範圍第11項所述之晶片封裝體的製造方法，其中該第二開口的直徑小於該第一開口的直徑。
  13. 如申請專利範圍第11項所述之晶片封裝體的製造方法，其中該重佈線層填滿該第二開口。
  14. 如申請專利範圍第11項所述之晶片封裝體的製造方法，其中該導電墊結構包括垂直堆疊的複數導電墊，且其中該第 一開口露出該等導電墊其中一者的一表面，且該第二開口自該等導電墊其中一者的該表面延伸而貫穿該等導電墊。
  15. 如申請專利範圍第11項所述之晶片封裝體的製造方法，更包括在該第一開口內的該重佈線層上形成一鈍化保護層。
  16. 如申請專利範圍第15項所述之晶片封裝體的製造方法，其中一空腔形成於該鈍化保護層與該第一開口內的該重佈線層之間。
  17. 如申請專利範圍第11項所述之晶片封裝體的製造方法，更包括提供一蓋板及一間隔層，其中該介電層位於該蓋板與該基底之間，且該間隔層位於該蓋板與該介電層之間。
  18. 如申請專利範圍第17項所述之晶片封裝體的製造方法，其中該第二開口更延伸至該間隔層內。
  19. 如申請專利範圍第11項所述之晶片封裝體的製造方法，更包括提供一另一基底，其具有一元件區，與該導電墊結構電性連接，其中該介電層位於該另一基底與該基底之間。
  20. 如申請專利範圍第11項所述之晶片封裝體的製造方法，其中該基底內具有一元件區，與該導電墊結構電性連接。
  21. 如申請專利範圍第11項所述之晶片封裝體的製造方法，其中該基底為一晶圓。
  22. 如申請專利範圍第21項所述之晶片封裝體的製造方法，更包括在形成該重佈線層之後，切割該晶圓，以形成複數晶片封裝體。
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US10892290B2 (en) * 2018-03-27 2021-01-12 Omnivision Technologies, Inc. Interconnect layer contact and method for improved packaged integrated circuit reliability
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US11605576B2 (en) * 2019-06-25 2023-03-14 Semiconductor Components Industries, Llc Via for semiconductor devices and related methods
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110193241A1 (en) * 2010-02-09 2011-08-11 Yu-Lin Yen Chip package and method for forming the same
TW201234557A (en) * 2011-02-10 2012-08-16 Xintec Inc Chip package and fabrication method thereof

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101465948B1 (ko) * 2007-12-27 2014-12-10 삼성전자주식회사 웨이퍼 레벨 스택 패키지 및 웨이퍼 레벨 스택 패키지 제조방법
US8698316B2 (en) * 2010-03-11 2014-04-15 Yu-Lin Yen Chip package
US8742564B2 (en) * 2011-01-17 2014-06-03 Bai-Yao Lou Chip package and method for forming the same
CN102891133B (zh) * 2011-07-22 2016-04-20 精材科技股份有限公司 晶片封装体及其形成方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110193241A1 (en) * 2010-02-09 2011-08-11 Yu-Lin Yen Chip package and method for forming the same
TW201234557A (en) * 2011-02-10 2012-08-16 Xintec Inc Chip package and fabrication method thereof

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