TWI565015B - 晶片封裝體及其製造方法 - Google Patents

晶片封裝體及其製造方法 Download PDF

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Publication number
TWI565015B
TWI565015B TW103141128A TW103141128A TWI565015B TW I565015 B TWI565015 B TW I565015B TW 103141128 A TW103141128 A TW 103141128A TW 103141128 A TW103141128 A TW 103141128A TW I565015 B TWI565015 B TW I565015B
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Taiwan
Prior art keywords
substrate
chip package
layer
conductive pads
conductive
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TW103141128A
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English (en)
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TW201521172A (zh
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劉建宏
溫英男
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精材科技股份有限公司
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Publication of TW201521172A publication Critical patent/TW201521172A/zh
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Description

晶片封裝體及其製造方法
本發明係有關於一種晶片封裝體及其製造方法，特別為有關於以晶圓級封裝製程所形成之晶片封裝體。
晶片封裝製程是形成電子產品過程中之重要步驟。晶片封裝體除了將晶片保護於其中，使免受外界環境污染外，還提供晶片內部電子元件與外界之電性連接通路。
製作晶片封裝體的過程包括將晶圓基底切割為複數晶片之後，將晶片放置於尺寸大於晶片的導線架(lead frame)上，接著透過金焊線將晶片上的導電墊電性連接至導線架的接合墊，以形成晶片的外部電性連接的路徑。
然而，由於使用金焊線及導線架作為外部電性連接的路徑，成本較高，且使得晶片封裝體的整體尺寸增加，因此難以進一步縮小晶片封裝體的尺寸。
因此，有必要尋求一種新穎的晶片封裝體及其製造方法，其能夠解決或改善上述的問題。
本發明實施例係提供一種晶片封裝體，包括一第一基底，其中複數第一導電墊設置於第一基底的一第一側上。一第二基底貼附於相對於第一基底之第一側的一第二側上，其中第二基底具有一微電子元件，且具有對應第一導電墊的複數 第二導電墊設置於第二基底的一第一側上，且位於第一基底與第二基底之間。一重佈線層設置於相對於第二基底之第一側的一第二側上，且穿過第二基底、第二導電墊及第一基底而延伸至第一導電墊內，以與第一導電墊及第二導電墊電性連接。
本發明實施例係提供一種晶片封裝體的製造方法，包括提供一第一基底，其中複數第一導電墊設置於第一基底的一第一側上。將一第二基底貼附於相對於第一基底之第一側的一第二側上，其中第二基底具有一微電子元件，且具有對應第一導電墊的複數第二導電墊設置於第二基底的一第一側上，且位於第一基底與第二基底之間。在相對於第二基底之第一側的一第二側上形成一重佈線層，其中重佈線層穿過第二基底、第二導電墊及第一基底而延伸至第一導電墊內，以與第一導電墊及第二導電墊電性連接。
100、600‧‧‧第一基底
100a、300a、600a‧‧‧第一側
100b、300b、600b‧‧‧第二側
120、320、620‧‧‧介電層
140、340、640‧‧‧導電墊
180、380、420、465、680‧‧‧開口
200‧‧‧第三基底
220‧‧‧第一層
250、650‧‧‧光學部件
260‧‧‧第二層/圍堰
265‧‧‧空腔
280‧‧‧蓋板
300‧‧‧第二基底
360‧‧‧黏著層
310‧‧‧電子元件區
400、460‧‧‧絕緣層
440‧‧‧重佈線層
480‧‧‧導電結構
500、700‧‧‧晶片封裝體
SC‧‧‧切割道
第1A至1G圖係繪示出根據本發明一實施例之晶片封裝體的製造方法的剖面示意圖。
第2A至2G圖係繪示出根據本發明另一實施例之晶片封裝體的製造方法的剖面示意圖。
以下將詳細說明本發明實施例之製作與使用方式。然應注意的是，本發明提供許多可供應用的發明概念，其可以多種特定型式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式，非用以限制本發明之範圍。此 外，在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明，不代表所討論之不同實施例及/或結構之間具有任何關連性。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。
本發明一實施例之晶片封裝體可用以封裝微機電 系統晶片。然其應用不限於此，例如在本發明之晶片封裝體的實施例中，其可應用於各種包含主動元件或被動元件(active or passive elements)、數位電路或類比電路(digital or analog circuits)等積體電路的電子元件(electronic components)，例如是有關於光電元件(opto electronic devices)、微機電系統(Micro Electro Mechanical System；MEMS)、微流體系統(micro fluidic systems)、或利用熱、光線及壓力等物理量變化來測量的物理感測器(Physical Sensor)。特別是可選擇使用晶圓級封裝(wafer scale package；WSP)製程對影像感測裝置、發光二極體(light-emitting diodes；LEDs)、太陽能電池(solar cells)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力感測器(process sensors)或噴墨頭(ink printer heads)等半導體晶片進行封裝。
其中上述晶圓級封裝製程主要係指在晶圓階段完 成封裝步驟後，再予以切割成獨立的封裝體，然而，在一特定實施例中，例如將已分離之半導體晶片重新分布在一承載晶圓上，再進行封裝製程，亦可稱之為晶圓級封裝製程。另外，上 述晶圓級封裝製程亦適用於藉堆疊(stack)方式安排具有積體電路之多片晶圓，以形成多層積體電路(multi-layer integrated circuit devices)之晶片封裝體。
請參照第1G圖，其繪示出根據本發明一實施例之 晶片封裝體500的剖面示意圖。在本實施例中，晶片封裝體500包括一第一基底100、一第二基底300及一重佈線層440。第一基底100具有一第一側100a及與其相對的一第二側100b。在本實施例中，第一基底100可由空白晶圓(raw wafer)所構成，且不具有任何主動、被動元件或微電子元件。
第二基底300貼附於第一基底100的第二側100b 上，且具有一微電子元件(未繪示)位於一電子元件區310內。在一實施例中，微電子元件可為數位訊號處理(digital signal processor，DSP)元件或其他適合的微電子元件。
第二基底300具有一第一側300a及與其相對的一 第二側300b，且具有一介電層320及位於介電層320內的複數第二導電墊340，設置於第二基底300的第一側300a上，且位於第一基底100與第二基底300之間。在本實施例中，第二基底300具有複數開口380(繪示於第1E及1F圖)，對應於每一第二導電墊340。在一實施例中，第二基底300為一半導體晶圓(例如，矽晶圓)，以利於進行晶圓級封裝製程。在另一實施例中，第二基底300為一半導體晶片。在一實施例中，第二導電墊340可為單層導電層或具有多層之導電層結構，且透過內連線結構(未繪示)而與電子元件區310內的微電子元件電性連接。
一黏著層360設置於第一基底100與第二基底300 的介電層320之間，以將第二基底300貼附於第一基底100。在一實施例中，黏著層360可包括環氧樹脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的絕緣材料。
一絕緣層400設置於第二基底300的第二側300b 上，且填入第二基底300的開口380(繪示於第1E及1F圖)內。在一實施例中，絕緣層400可包括環氧樹脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的絕緣材料。
一第三基底200貼附於第一基底100的第一側100a 上，且具有一光學部件250設置於其上。在一實施例中，第三基底200包括一背照式(back side illumination，BSI)互補型金屬氧化物半導體影像感測(complementary metal oxide semiconductor image sensor，CIS)裝置(未繪示)。在一實施例中，第三基底200為一半導體晶圓(例如，矽晶圓)，以利於進行晶圓級封裝製程。在另一實施例中，第三基底200為一半導體晶片。在一實施例中，光學部件250可為用於影像感測裝置的微透鏡陣列或其他適合的光學部件。
第三基底200具有一介電層120及位於介電層120 內的複數第一導電墊140，第一導電墊140對應於第二導電墊340且設置於第一基底100與第三基底200之間(即，位於第一基底100的第一側100a上)。在一實施例中，第一導電墊140可為 單層導電層或具有多層之導電層結構，且透過內連線結構(未繪示)而與影像感測裝置(未繪示)電性連接。
在本實施例中，第一基底100具有複數開口180(繪 示於第1C及1D圖)，對應地暴露出每一第一導電墊140。設置於第一基底100與第二基底300之間的黏著層360填入於第一基底100的開口180內。
一間隔層對應於第一導電墊140而設置於第三基 底200的介電層120上(即，位於第一基底100的第一側100a上)，且包括第一層(或圍堰(dam))260及第二層220。在一實施例中，第一層260及第二層220可分別包括環氧樹脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂(polyimide)、苯環丁烯(butylcyclobutene，BCB)、聚對二甲苯(parylene)、萘聚合物(polynaphthalenes)、氟碳化物(fluorocarbons)、丙烯酸酯(acrylates))或其他適合的絕緣材料。
一蓋板280設置於圍堰260上。位於第三基底200與 蓋板280之間的圍堰260在其間形成一空腔265，使得光學部件250位於空腔265內的第三基底200上，且透過蓋板280保護光學部件250。在一實施例中，蓋板280可包括玻璃或其他適合的材料。
在一實施例中，複數開口420位於第二基底300的 開口380(繪示於第1E及1F圖)內，且穿過對應的第二導電墊340、第一基底100的開口180(繪示於第1C及1D圖)及對應的第一導電墊140而延伸至間隔層的第二層220內。重佈線層440設 置於第二基底300的第二側300b上，且延伸進入開口420內，而穿過第二導電墊340及第一導電墊140，並延伸至間隔層的第二層220內，以與第一導電墊140及第二導電墊340電性連接。開口420內的重佈線層440也稱為矽通孔電極(through silicon via，TSV)。在一實施例中，重佈線層440可包括銅、鋁、金、鉑或其他適合的導電材料。
在另一實施例中，開口420可更延伸至間隔層的第 一層260內，使得重佈線層440也更延伸至第一層260內(未繪示)。又另一實施例中，開口420可穿過第一導電墊140，而未延伸至間隔層內，使得重佈線層440也未延伸至間隔層內(未繪示)。又另一實施例中，開口420可延伸至第一導電墊140內，而未穿過第一導電墊140，使得重佈線層440也未穿過第一導電墊140(未繪示)。
在本實施例中，重佈線層440以環型接觸 (ring-contact)的方式電性連接第一導電墊140及第二導電墊340。在本實施例中，重佈線層440透過絕緣層400與第二基底300電性隔離，且透過黏著層360與第一基底100電性隔離。
在本實施例中，晶片封裝體500更包括一絕緣層 460(例如，鈍化護層)及一導電結構480(例如，焊球、凸塊或導電柱)，設置於第二基底300的第二側300b上。絕緣層460覆蓋重佈線層440，且具有複數開口465，以暴露出重佈線層440的一部份。在一實施例中，絕緣層460可包括環氧樹脂、綠漆(solder mask)、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺 樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的絕緣材料。
在一實施例中，絕緣層460經由開口420穿過第二 基底300、第二導電墊340、第一基底100及第一導電墊140，而延伸至間隔層的第二層220內。在另一實施例中，絕緣層460更延伸至間隔層的第一層260內(未繪示)。又另一實施例中，絕緣層460未延伸至間隔層內(未繪示)。又另一實施例中，絕緣層460未穿過第一導電墊140(未繪示)。
導電結構480填入於絕緣層460的開口465內，以與 重佈線層440電性連接。在一實施例中，導電結構480可包括錫、鉛、銅、金、鎳、或前述之組合。
請參照第2G圖，其繪示出根據本發明另一實施例之晶片封裝體700的剖面示意圖，其中相同於第1G圖中的部件係使用相同的標號並省略其說明。在本實施例中，晶片封裝體700包括一第一基底600、一第二基底300及一重佈線層440。不同於第1G圖的晶片封裝體500中的第一基底100由空白晶圓所構成，且不具有任何主動或被動元件，在本實施例中，第一基底600具有一介電層620及位於介電層620內的複數第一導電墊640，設置於第一基底600的第一側600a上，且具有一光學部件650設置於介電層620上。在一實施例中，第一基底600包括一前照式(front side illumination，FSI)互補型金屬氧化物半導體影像感測(CIS)裝置(未繪示)。在一實施例中，第一基底600為一半導體晶圓(例如，矽晶圓)，以利於進行晶圓級封裝製程。在另一實施例中，第一基底600為一半導體晶片。在一實施例 中，光學部件650可為用於影像感測裝置的微透鏡陣列或其他適合的光學部件。在一實施例中，第一導電墊640可為單層導電層或具有多層之導電層結構，且透過內連線結構(未繪示)而與影像感測裝置(未繪示)電性連接。
在本實施例中，第一基底600具有複數開口680(繪 示於第2C及2D圖)，對應地暴露出每一第一導電墊640。設置於第一基底600與第二基底300之間的黏著層360填入於第一基底600的開口680內。
不同於第1G圖的晶片封裝體500中的間隔層包括 第一層260及第二層220，在本實施例中，間隔層由一圍堰260所構成，其對應於第一導電墊640而設置於第一基底600的介電層620上(即，位於第一基底600的第一側600a上)。一蓋板280設置於圍堰260上。位於第一基底600與蓋板280之間的圍堰260在其間形成一空腔265，使得光學部件650位於空腔265內的第一基底600上，且透過蓋板280保護光學部件650。
在本實施例中，晶片封裝體700中的重佈線層440 經由開口420穿過第二基底300、第二導電墊340、第一基底600及第一導電墊640而延伸至圍堰260內。在另一實施例中，重佈線層440可穿過第一導電墊640，而未延伸至圍堰260內(未繪示)。又另一實施例中，重佈線層440可延伸至第一導電墊640內，而未穿過第一導電墊640(未繪示)。
根據本發明的上述實施例，將互補式金屬氧化物 半導體影像感測(CIS)裝置及數位訊號處理(DSP)元件垂直堆疊，且開口420穿過第二基底300、對應的第二導電墊340及第 一基底100/600而延伸至對應的第一導電墊140/640內，因此可透過延伸至開口420內的重佈線層440電性連接互補式金屬氧化物半導體影像感測裝置與數位訊號處理元件，且以矽通孔電極(即，重佈線層440)作為晶片封裝體的外部電性連接的路徑，而不需使用焊線及導線架，能夠節省成本，並使得結合互補式金屬氧化物半導體影像感測裝置及數位訊號處理元件之晶片封裝體的尺寸能夠進一步縮小。
以下配合第1A至1G圖說明本發明一實施例之晶片 封裝體的製造方法，其中第1A至1G圖係繪示出根據本發明一實施例之晶片封裝體500的製造方法的剖面示意圖。
請參照第1A圖，提供一第一基底100，其具有一第 一側100a及與其相對的一第二側100b。在本實施例中，第一基底100可由空白晶圓所構成，且不具有任何主動、被動元件或微電子元件。
一第三基底200貼附於第一基底100的第一側100a 上，且具有一光學部件250設置於其上。在一實施例中，第三基底200包括一背照式(BSI)互補型金屬氧化物半導體影像感測(CIS)裝置(未繪示)。在一實施例中，第三基底200為一半導體晶圓(例如，矽晶圓)，以利於進行晶圓級封裝製程。在一實施例中，光學部件250可為用於影像感測裝置的微透鏡陣列或其他適合的光學部件。
第三基底200具有一介電層120及位於介電層120 內的複數第一導電墊140，設置於第一基底100與第三基底200之間(即，位於第一基底100的第一側100a上)。在一實施例中， 第一導電墊140可為單層導電層或具有多層之導電層結構，且透過內連線結構(未繪示)而與影像感測裝置(未繪示)電性連接。
一間隔層對應於第一導電墊140而設置於第三基 底200的介電層120上。在本實施例中，間隔層可包括位於介電層120上的一第二層220及位於第二層220上的一第一層(或圍堰)260，如第1B圖所示。在一實施例中，第二層220可包括環氧樹脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯(BCB)、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的絕緣材料。
可透過沉積製程(例如，塗佈製程、物理氣相沈積 製程、化學氣相沈積製程或其他適合的製程)，在第三基底200上形成第一層260，使第一層260對應於第一導電墊140。在一實施例中，第一層260可包括環氧樹脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯(BCB)、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的絕緣材料。
接著，在圍堰260上提供一蓋板280，以在第三基底200與蓋板280之間形成一空腔265，使得光學部件250位於空腔265內的第三基底200上，且透過蓋板280保護光學部件250。在一實施例中，蓋板280可包括玻璃或其他適合的材料。
請參照第1C圖，以蓋板280作為承載基板，對第一基底100的第二側100b的表面進行薄化製程(例如，蝕刻製程、 銑削(milling)製程、磨削(grinding)製程或研磨(polishing)製程)，以減少第一基底100的厚度。
接著，透過微影製程及蝕刻製程(例如，乾蝕刻製 程、濕蝕刻製程、電漿蝕刻製程、反應性離子蝕刻製程或其他適合的製程)，在第一基底100內形成複數開口180，對應地暴露出每一第一導電墊140。
請參照第1D圖，可透過沉積製程(例如，塗佈製 程、物理氣相沈積製程、化學氣相沈積製程或其他適合的製程)，在第一基底100的第二側100b上形成一黏著層360，且填入於第一基底100的開口180內。在一實施例中，黏著層360可包括環氧樹脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的絕緣材料。
接著，透過黏著層360，將一第二基底300貼附於 第一基底100的第二側100b上。第二基底300具有一微電子元件(未繪示)位於一電子元件區310內。在一實施例中，微電子元件可為數位訊號處理(DSP)元件或其他適合的微電子元件。第二基底300具有一第一側300a及與其相對的一第二側300b，且具有一介電層320及位於介電層320內的複數第二導電墊340。第二導電墊340對應於第一導電墊140，且設置於第二基底300的第一側300a上以及位於第一基底100與第二基底300之間。
請參照第1E圖，以蓋板280作為承載基板，對第二 基底300的第二側300b的表面進行薄化製程(例如，蝕刻製程、 銑削製程、磨削製程或研磨製程)，以減少第二基底300的厚度。
接著，透過微影製程及蝕刻製程(例如，乾蝕刻製 程、濕蝕刻製程、電漿蝕刻製程、反應性離子蝕刻製程或其他適合的製程)，在第二基底300內形成複數開口380，對應於每一第二導電墊340。在一實施例中，第二基底300為一半導體晶圓(例如，矽晶圓)，以利於進行晶圓級封裝製程。在一實施例中，第二導電墊340可為單層導電層或具有多層之導電層結構，且透過內連線結構(未繪示)而與電子元件區310內的微電子元件電性連接。
請參照第1F圖，可透過沉積製程(例如，塗佈製程、 物理氣相沈積製程、化學氣相沈積製程或其他適合的製程)，在第二基底300的第二側300b上形成一絕緣層400，且填入於第二基底300的開口380內。在一實施例中，絕緣層400可包括環氧樹脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的絕緣材料。
接著，可透過雷射鑽孔製程、蝕刻製程(例如，乾 蝕刻製程、濕蝕刻製程、電漿蝕刻製程、反應性離子蝕刻製程)或其他適合的製程，在每一開口380(繪示於第1E及1F圖)內的絕緣層400內形成一開口420。
接著，可透過沉積製程(例如，塗佈製程、物理氣 相沉積製程、化學氣相沉積製程、電鍍製程、無電鍍製程或其他適合的製程)、微影製程及蝕刻製程，在第二基底300的第二 側300b上形成圖案化的重佈線層440，且延伸進入每一開口420內。在一實施例中，重佈線層440可包括銅、鋁、金、鉑或其他適合的導電材料。
在一實施例中，開口420穿過對應的第二導電墊 340、第一基底100的開口180(繪示於第1C及1D圖)及對應的第一導電墊140而延伸至間隔層的第二層220內，因而重佈線層440也穿過對應的第二導電墊340及第一導電墊140，並延伸至間隔層的第二層220內，以與第一導電墊140及第二導電墊340電性連接。
在另一實施例中，開口420可更延伸至間隔層的第 一層260內，使得重佈線層440也更延伸至間隔層的第一層260內(未繪示)。又另一實施例中，開口420可穿過第一導電墊140，而未延伸至間隔層內，使得重佈線層440也未延伸至間隔層內(未繪示)。又另一實施例中，開口420可延伸至第一導電墊140內，而未穿過第一導電墊140，使得重佈線層440也未穿過第一導電墊140(未繪示)。
在本實施例中，重佈線層440以環型接觸(ring-contact)的方式電性連接第一導電墊140及第二導電墊340。在本實施例中，重佈線層440透過絕緣層400與第二基底300電性隔離，且透過黏著層360與第一基底100電性隔離。
請參照第1G圖，可透過沉積製程，在第二基底300的第二側300b上形成絕緣層460(例如，鈍化護層)，以覆蓋重佈線層440。在一實施例中，絕緣層460填入開口420而穿過第二基底300、對應的第二導電墊340、第一基底100及對應的第一 導電墊140，並延伸至間隔層的第二層220內。在另一實施例中，絕緣層460更延伸至間隔層的第一層260內(未繪示)。又另一實施例中，絕緣層460未延伸至間隔層內(未繪示)。又另一實施例中，絕緣層460未穿過第一導電墊140(未繪示)。在一實施例中，絕緣層460可包括環氧樹脂、綠漆、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的絕緣材料。
接著，可透過微影製程及蝕刻製程，在絕緣層460 內形成開口465，以暴露出圖案化的重佈線層440的一部分。接著，在絕緣層460的開口465內填入導電結構480(例如，焊球、凸塊或導電柱)，以與圖案化的重佈線層440電性連接。舉例來說，可透過電鍍製程、網版印刷製程或其他適合的製程，在絕緣層460的開口465內形成焊料(solder)，且進行迴焊(reflow)製程，以形成導電結構480。在一實施例中，導電結構480可包括錫、鉛、銅、金、鎳、或前述之組合。接著，沿著切割道SC，切割第二基底300、第一基底100及蓋板280，以形成複數獨立的晶片封裝體500。
以下配合第2A至2G圖說明本發明另一實施例之晶 片封裝體的製造方法。第2A至2G圖係繪示出根據本發明另一實施例之晶片封裝體700的製造方法的剖面示意圖，其中相同於第1A至1G圖中的部件係使用相同的標號並省略其說明。
請參照第2A圖，提供一第一基底600，其具有一第一側600a及與其相對的一第二側600b。在本實施例中，第一基 底600具有一介電層620及位於介電層620內的複數第一導電墊640，設置於第一基底600的第一側600a上，且具有一光學部件650設置於介電層620上。在一實施例中，第一基底600包括一前照式(FSI)互補型金屬氧化物半導體影像感測(CIS)裝置(未繪示)。在一實施例中，第一基底600為一半導體晶圓(例如，矽晶圓)，以利於進行晶圓級封裝製程。在一實施例中，光學部件650可為用於影像感測裝置的微透鏡陣列或其他適合的光學部件。在一實施例中，第一導電墊640可為單層導電層或具有多層之導電層結構，且透過內連線結構(未繪示)而與影像感測裝置(未繪示)電性連接。
請參照第2B圖，可透過與第1B圖相同或相似之步 驟，在第一基底600的介電層620上(即，第一基底600的第一側600a上)形成一圍堰260，其對應於第一導電墊640。接著，在圍堰260上提供一蓋板280，以在第一基底600與蓋板280之間形成一空腔265，使得光學部件650位於空腔265內的第一基底600上，且透過蓋板280保護光學部件650。
請參照第2C至2E圖，可透過與第1C至1E圖相同或 相似之步驟，薄化第一基底600且於其中形成複數開口680，對應地暴露出每一第一導電墊640，如第2C圖所示。接著，在第一基底600的第二側600b上形成一黏著層360，且填入於第一基底600的開口680內，並透過黏著層360，將一第二基底300貼附於第一基底600的第二側600b上，如第2D圖所示。在薄化第二基底300之後，在第二基底300內形成複數開口380，對應於第二基底300的每一第二導電墊340，如第2E圖所示。
第二基底300具有一微電子元件(未繪示)位於一電 子元件區310內。在一實施例中，微電子元件可為數位訊號處理(DSP)元件或其他適合的微電子元件。
請參照第2F至2G圖，可透過與第1F至1G圖相同或 相似之步驟，依序在第二基底300的第二側300b上形成一絕緣層400、複數開口420以及圖案化且填入開口420內的重佈線層440，如第2F圖所示。接著，依序形成具有複數開口465的一絕緣層460以及填入開口465內的導電結構480，並沿著切割道SC，切割第二基底300、第一基底600及蓋板280，以形成複數獨立的晶片封裝體700，如第2G圖所示。
在本實施例中，重佈線層440經由開口420穿過第 二基底300、第二導電墊340、第一基底600及第一導電墊640而延伸至圍堰260內。在另一實施例中，重佈線層440可穿過第一導電墊640，而未延伸至圍堰260內(未繪示)。又另一實施例中，重佈線層440可延伸至第一導電墊640內，而未穿過第一導電墊640(未繪示)。
根據本發明的上述實施例，由於將互補式金屬氧 化物半導體影像感測裝置及數位訊號處理元件垂直堆疊，且透過雷射鑽孔製程，形成開口420，以穿過第二基底300、第二導電墊340及第一基底100/600而延伸至第一導電墊140/640內。因此，可透過延伸至開口420內的重佈線層440電性連接互補式金屬氧化物半導體影像感測裝置與數位訊號處理元件，而不需使用焊線，使得結合互補式金屬氧化物半導體影像感測裝置及數位訊號處理元件之晶片封裝體的尺寸能夠進一步縮小，且降低 成本。另外，採用晶圓級製程來製作晶片封裝體，可大量生產晶片封裝體，進而降低成本並節省製程時間。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可更動與組合上述各種實施例。
100‧‧‧第一基底
100a、300a‧‧‧第一側
100b、300b‧‧‧第二側
120、320‧‧‧介電層
140、340‧‧‧導電墊
200‧‧‧第三基底
220‧‧‧第一層
250‧‧‧光學部件
260‧‧‧第二層/圍堰
265‧‧‧空腔
280‧‧‧蓋板
300‧‧‧第二基底
360‧‧‧黏著層
310‧‧‧電子元件區
400、40‧‧‧絕緣層
420、465‧‧‧開口
440‧‧‧重佈線層
480‧‧‧導電結構
500‧‧‧晶片封裝體
SC‧‧‧切割道

Claims (21)

  1. 一種晶片封裝體，包括：一第一基底，其中複數第一導電墊設置於該第一基底的一第一側上；一第二基底，貼附於相對於該第一基底之該第一側的一第二側上，其中該第二基底具有一微電子元件，且具有對應於該等第一導電墊的複數第二導電墊設置於該第二基底的一第一側上，且位於該第一基底與該第二基底之間，且其中該第二基底具有一開口對應於該等第二導電墊的其中一者；一開口，具有小於該第二基底的該開口的寬度，且經由該第二基底的該開口而穿過該第二基底、該等第二導電墊及該第一基底；以及一重佈線層，設置於相對於該第二基底之該第一側的一第二側上，且延伸至該開口內，並穿過該第二基底、該等第二導電墊及該第一基底而延伸至該等第一導電墊內，以與該等第一導電墊及該等第二導電墊電性連接。
  2. 如申請專利範圍第1項所述之晶片封裝體，其中該重佈線層更延伸穿過該等第一導電墊。
  3. 如申請專利範圍第1項所述之晶片封裝體，其中該第一基底為一空白晶圓。
  4. 如申請專利範圍第3項所述之晶片封裝體，更包括一影像感測裝置，設置於該第一基底的該第一側上，其中該微電子元件為一數位訊號處理元件。
  5. 如申請專利範圍第1項所述之晶片封裝體，其中該第一基底包括一影像感測裝置，且該微電子元件為一數位訊號處理元件。
  6. 如申請專利範圍第1項所述之晶片封裝體，更包括：一黏著層，將該第二基底貼附於該第一基底；以及一絕緣層，設置於該第二基底的該第二側上。
  7. 如申請專利範圍第6項所述之晶片封裝體，其中該重佈線層穿過該黏著層及該絕緣層。
  8. 如申請專利範圍第1項所述之晶片封裝體，更包括一間隔層，設置於該第一基底的該第一側上，其中該重佈線層更延伸進入該間隔層內。
  9. 如申請專利範圍第1項所述之晶片封裝體，更包括一絕緣層，設置於該第二基底的該第二側上，以覆蓋該重佈線層，其中該絕緣層穿過該第二基底、該等第二導電墊及該第一基底而延伸至該等第一導電墊內。
  10. 如申請專利範圍第9項所述之晶片封裝體，其中該絕緣層更延伸穿過該等第一導電墊。
  11. 一種晶片封裝體的製造方法，包括：提供一第一基底，其中複數第一導電墊設置於該第一基底的一第一側上；將一第二基底貼附於相對於該第一基底之該第一側的一第二側上，其中該第二基底具有一微電子元件，且具有對應於該等第一導電墊的複數第二導電墊設置於該第二基底的一第一側上，且位於該第一基底與該第二基底之間；以及 在相對於該第二基底之該第一側的一第二側上形成一重佈線層，其中該重佈線層穿過該第二基底、該等第二導電墊及該第一基底而延伸至該等第一導電墊內，以與該等第一導電墊及該等第二導電墊電性連接。
  12. 如申請專利範圍第11項所述之晶片封裝體的製造方法，其中該重佈線層更延伸穿過該等第一導電墊。
  13. 如申請專利範圍第11項所述之晶片封裝體的製造方法，其中該第一基底為一空白晶圓。
  14. 如申請專利範圍第13項所述之晶片封裝體的製造方法，更包括在該第一基底的該第一側上設置一影像感測裝置，其中該微電子元件為一數位訊號處理元件。
  15. 如申請專利範圍第11項所述之晶片封裝體的製造方法，其中該第一基底包括一影像感測裝置，且該微電子元件為一數位訊號處理元件。
  16. 如申請專利範圍第11項所述之晶片封裝體的製造方法，其中透過一黏著層，將該第二基底貼附於該第一基底。
  17. 如申請專利範圍第16項所述之晶片封裝體的製造方法，更包括：在形成該重佈線層之前，在該第二基底的該第二側上形成一絕緣層；以及形成穿過該絕緣層及該黏著層的一開口，其中該重佈線層延伸進入該開口，以穿過該黏著層。
  18. 如申請專利範圍第17項所述之晶片封裝體的製造方法，其中透過雷射鑽孔製程，形成該開口。
  19. 如申請專利範圍第11項所述之晶片封裝體的製造方法，更包括在該第一基底的該第一側上形成一間隔層，其中該重佈線層更延伸進入該間隔層內。
  20. 如申請專利範圍第11項所述之晶片封裝體的製造方法，更包括在該第二基底的該第二側上形成一絕緣層，以覆蓋該重佈線層，其中該絕緣層穿過該第二基底、該等第二導電墊及該第一基底而延伸至該等第一導電墊內。
  21. 如申請專利範圍第20項所述之晶片封裝體的製造方法，其中該絕緣層更延伸穿過該等第一導電墊。
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