TWI579995B - 晶片封裝體及其製造方法 - Google Patents

晶片封裝體及其製造方法 Download PDF

Info

Publication number
TWI579995B
TWI579995B TW104107139A TW104107139A TWI579995B TW I579995 B TWI579995 B TW I579995B TW 104107139 A TW104107139 A TW 104107139A TW 104107139 A TW104107139 A TW 104107139A TW I579995 B TWI579995 B TW I579995B
Authority
TW
Taiwan
Prior art keywords
chip package
conductive
doped region
region
pad structure
Prior art date
Application number
TW104107139A
Other languages
English (en)
Other versions
TW201523824A (zh
Inventor
Chien Hung Liu
Cheng Te Chou
Original Assignee
Xintex Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xintex Inc filed Critical Xintex Inc
Publication of TW201523824A publication Critical patent/TW201523824A/zh
Application granted granted Critical
Publication of TWI579995B publication Critical patent/TWI579995B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0239—Material of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05024—Disposition the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/05686—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2224/05688—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29005—Structure
    • H01L2224/29007—Layer connector smaller than the underlying bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29011—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32052—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01021—Scandium [Sc]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Description

晶片封裝體及其製造方法
本發明係有關於一種晶片封裝體，特別有關於一種晶圓級晶片封裝體及其製造方法。
目前業界針對晶片的封裝已發展出一種晶圓級封裝技術，於晶圓級封裝完成之後，再進行切割步驟，以分離形成晶片封裝體。其中晶片封裝體內的重佈線路圖案係以和金屬接墊直接接觸為主，因此，在重佈線路圖案的製程上，必須配合金屬接墊的設計。
因此，業界亟需一種新穎的晶片封裝體及其製作方法，以克服上述問題。
本發明之實施例係提供一種晶片封裝體，包括：一半導體基板，具有相反之第一表面與第二表面，以及至少一接墊區與至少一元件區；複數個導電墊結構，位於該半導體基板之第一表面，且位於該半導體基板之該接墊區上；複數個相互隔離之重摻雜區，設於該些導電墊結構下方，且與該些導電墊結構電性連接；以及，複數個導電凸塊，設於該些重摻雜區下方，且經由該些重摻雜區與該些導電墊結構形成電性連接。
本發明之實施例更提供一種晶片封裝體的製造方法，包括：提供一半導體晶圓，具有相反之第一表面與第二表 面，該半導體晶圓包括至少一接墊區與至少一元件區，以及複數個導電墊結構，位於該第一表面之該接墊區上；形成複數個相互隔離之重摻雜區於該些導電墊結構下方，其中該些重摻雜區和該些導電墊結構形成電性連接；以及，形成複數個導電凸塊於該些重摻雜區之下方，其中該些導電凸塊經由該些重摻雜區與該些導電墊結構形成電性連接。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
300‧‧‧半導體晶圓
300B‧‧‧重摻雜區
301‧‧‧絕緣層
100A‧‧‧元件區
100B‧‧‧周邊接墊區
302‧‧‧半導體元件
304‧‧‧導電墊結構
305‧‧‧絕緣壁
500‧‧‧封裝層
310‧‧‧間隔層
316‧‧‧空腔
320‧‧‧絕緣層
330‧‧‧重佈線路圖案
340‧‧‧保護層
350‧‧‧導電凸塊
600‧‧‧承載晶圓
600B‧‧‧重摻雜區
630‧‧‧絕緣層
610‧‧‧絕緣壁
500‧‧‧封裝層
640‧‧‧保護層
650‧‧‧導電凸塊
第1-2圖係顯示依據本發明之一實施例中，形成半導體晶片之製造方法的剖面示意圖。
第3A-3F圖係顯示依據本發明之另一實施例中，形成承載基板之製造方法的剖面示意圖。
第4-5圖係顯示依據本發明之另一實施例中，形成晶片封裝體之製造方法的剖面示意圖。
第6A-6B圖係顯示依據本發明之另一實施例中，形成晶片封裝體之製造方法的剖面示意圖。
第7A-7D圖係顯示依據本發明之另一實施例中，形成晶片封裝體之製造方法的剖面示意圖。
第8A-8D圖係顯示依據本發明之另一實施例中，形成晶片封裝體之製造方法的剖面示意圖。
以下以實施例並配合圖式詳細說明本發明，在圖式或說明書描述中，相似或相同之部分係使用相同之圖號。且在圖式中，實施例之形狀或是厚度可擴大，以簡化或是方便標示。再者，圖式中各元件之部分將以描述說明之，值得注意的是，圖中未繪示或描述之元件，為所屬技術領域中具有通常知識者所知的形式。另外，特定之實施例僅為揭示本發明使用之特定方式，其並非用以限定本發明。
本發明係以一製作CMOS影像感測晶片封裝體為例，然而微機電晶片封裝體(MEMS chip package)或其他半導體晶片亦可適用。亦即，可以了解的是，在本發明之晶片封裝體的實施例中，其可應用於各種包含主動元件或被動元件(active or passive elements)、數位電路或類比電路(digital or analog circuits)等積體電路的電子元件(electronic components)，例如是有關於光電元件(opto electronic devices)、微機電系統(Micro Electro Mechanical System；MEMS)、微流體系統(micro fluidic systems)、或利用熱、光線及壓力等物理量變化來測量的物理感測器(Physical Sensor)，或是CMOS影像感測器等。特別是可選擇使用晶圓級封裝(wafer scale package；WSP)製程對影像感測元件、發光二極體(light-emitting diodes；LEDs)、太陽能電池(solar cells)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力感測器(process sensors)或噴墨頭(ink printer heads)等晶片進行封裝。
其中上述晶圓級封裝製程主要係指在晶圓階段完 成封裝步驟後，再予以切割成獨立的封裝體，然而，在一特定實施例中，例如將已分離之半導體晶片重新分布在一承載晶圓上，再進行封裝製程，亦可稱之為晶圓級封裝製程。另外，上述晶圓級封裝製程亦適用於藉堆疊(stack)方式安排具有積體電路之多片晶圓，以形成多層積體電路(multi-layer integrated circuit devices)之晶片封裝體。
本發明的特徵之一係藉由重摻雜區達成導電墊結構與導電凸塊之間的電性連接，而不以重佈線路圖案與導電墊結構的直接接觸為必要。在一實施例中，上述重摻雜區係直接設置於導電墊結構下方的半導體基底。在另一實施例中，上述重摻雜區亦可設置在一額外的承載基板中。
請參閱第1至2圖，其係顯示依據本發明之一實施例，於半導體晶圓上製作晶片封裝體之製造方法的剖面示意圖。在本實施例中重摻雜區係設置於導電墊結構下方的半導體基底。如第1圖及第2圖所示，首先提供一半導體晶圓300，一般為矽基板，其包括一絕緣層301，可藉由熱氧化或化學氣相沈積法等半導體製程形成，或者在一實施例中可採用一絕緣層上覆矽基板(SOI)，或者藉由晶圓接合製程(wafer bonding)結合兩片晶圓而成，其中一片晶圓具有絕緣層。其次，半導體晶圓定義有多個元件區100A，圍繞元件區100A者為周邊接墊區100B。接續，於半導體晶圓300中形成連接至絕緣層301之絕緣壁305以隔離複數個區域以作為重摻雜區300B。以及於元件區100A製作半導體元件302，例如影像感測器元件或是微機電結構，而覆蓋上述半導體晶圓300及半導體元件302者為層間介電 層303(IMD)，一般可選擇低介電係數(low k)的絕緣材料，例如多孔性氧化層。接著於周邊接墊區100B的層間介電層303中製作複數個導電墊結構304。上述絕緣壁和絕緣層可以為絕緣材料例如一般的氧化矽，或是由絕緣空間構成，例如是氣隙層或真空隔離層。上述導電墊結構304較佳可以由銅(copper；Cu)、鋁(aluminum；Al)或其它合適的金屬材料所製成。其中值得注意的是，上述半導體晶圓於周邊接墊區100B之位置包括多個重摻雜區300B，其電性連接導電墊結構304並由絕緣壁305所隔離，重摻雜區300B可透過例如擴散或離子植入步驟，摻雜高濃度的離子如摻雜劑量為1E14~6E15atoms/cm2的磷或砷等形成，以構成一導電路徑。在一實施例中，一個重摻雜區係對應一個導電墊結構，然而，在多個導電墊結構作為共同輸出的情形下，可由一個重摻雜區對應多個導電墊結構。
此外，半導體晶圓300在晶圓廠產出時一般係覆蓋有一晶片保護層306(passivation layer)，同時為將晶片內的元件電性連接至外部電路，傳統上晶圓廠會事先定義晶片保護層306以形成複數個暴露出導電墊結構304的開口306h。
接著，如第3A圖所示，提供封裝層500以與半導體晶圓接合，其中為方便說明起見，上述半導體晶圓300係僅揭示導電墊結構304、絕緣壁305和絕緣層301。封裝層500例如為玻璃等透明基板、另一空白矽晶圓、或是另一含有積體電路元件的晶圓。在一實施例中，可藉由間隔層310分開封裝層500與半導體基板，同時形成由間隔層310所圍繞的空腔316。間隔層310可以為密封膠，或是感光絕緣材料，例如環氧樹脂(epoxy)、 阻銲材料(solder mask)等。此外間隔層310可先形成於半導體晶圓300上，之後再藉由黏著層與相對之封裝層500接合，反之，亦可將間隔層310先形成於封裝層500上，之後再藉由黏著層與相對之半導體晶圓300接合。
請參閱第3B圖，可以封裝層500為承載基板，自半導體晶圓背面300a進行蝕刻，例如藉由非等向性蝕刻製程去除部份矽基板和絕緣層301，於半導體晶圓300中形成暴露出重摻雜區300B之連通開口300h。值得注意的是，此些開口300h係分別對應各周邊接墊區100B中由絕緣壁305隔離之重摻雜區300B。
然後如第3C圖所示，於開口300h內形成露出重摻雜區300B之絕緣層320，例如可先藉由熱氧化法或電漿化學氣相沈積法，形成氧化矽層於開口300h內，其並可延伸至半導體晶圓300的背面300a，接著，除去開口300h之底部上的絕緣層，例如藉由微影製程定義開口300h之底部以暴露出重摻雜區300B。
接著，如第3D圖所示，於開口300h內形成導電圖案330。在此實施例中，導電圖案330係作為重佈線路圖案，因此其除了形成於開口300h之側壁上，還進一步延伸至半導體晶圓下表面300a和重摻雜區300B上。重佈線路圖案330之形成方式可包括物理氣相沉積、化學氣相沉積、電鍍、或無電鍍等。重佈線路圖案330之材質可為金屬材質，例如銅、鋁、金、或前述之組合。重佈線路圖案330之材質還可包括導電氧化物，例如氧化銦錫(ITO)、氧化銦鋅(IZO)、或前述之組合。在一實 施例中，係於整個半導體晶圓300上順應性形成一導電層，接著將導電層圖案化為例如第3D圖所示之重佈線路圖案分佈。
接續，請參閱第3E圖，其顯示保護層340的形成方式。在本發明實施例中，保護層340例如為阻焊膜(solder mask)，可經由塗佈防銲材料的方式於半導體晶圓背面300a處形成保護層340。然後，對保護層340進行圖案化製程，以形成暴露部分重佈線路圖案330的複數個終端接觸開口。然後，於終端接觸開口處形成銲球下金屬層(Under Bump Metallurgy,UBM)和導電凸塊350。舉例而言，由導電材料構成之銲球下金屬層(UBM)可以是金屬或金屬合金，例如鎳層、銀層、鋁層、銅層或其合金；或者是摻雜多晶矽、單晶矽、或導電玻璃層等材料。此外，耐火金屬材料例如鈦、鉬、鉻、或是鈦鎢層，亦可單獨或和其他金屬層結合。而在一特定實施例中，鎳/金層可以局部或全面性的形成於金屬層表面。其中導電凸塊350可藉由重佈線路圖案330電性連接重摻雜區300B，而非導電墊結構304。在本發明實施例中，導電凸塊350係用以傳遞元件302中的輸入/輸出(I/O)信號、接地(ground)信號或電源(power)信號。接著，沿著周邊接墊區的切割線SC將半導體晶圓分割，即可形成複數個晶片封裝體。
其中，在週邊接墊區上之重摻雜區300B，係由絕緣壁305隔離，因此重佈線路圖案330可直接和重摻雜區300B電性接觸，而不以和導電墊結構304直接接觸為必要。此外由於週邊接墊區上之重摻雜區300B其區域範圍可較導電墊結構為寬，因此開口300h可有較高的對準容許誤差。
另如第3F圖所示，開口300h的深度可以超過絕緣層301，因此開口內的重佈線路圖案330可以深入重摻雜區300B中，或甚至抵達導電墊結構，以增加接觸面積。亦即絕緣層301可位於該些開口300h的底部或其下方。
接下來，請參閱第4至5圖，其係顯示依據本發明之另一實施例，於半導體晶圓上製作晶片封裝體之製造方法的剖面示意圖。在本實施例中，重摻雜區係設置於一承載基板中。如第4圖及第5圖所示，首先提供一半導體晶圓，一般為矽晶圓300，半導體晶圓包括一上表面300a及一下表面300b。其次，半導體晶圓定義有複數個對應晶片的切割區和複數個基板，每個基板包括至少一元件區100A，圍繞元件區100A者為周邊接墊區100B。接續，於上表面300a處之元件區100A製作半導體元件302，例如影像感測器元件或是微機電結構，而覆蓋上述半導體晶圓300及半導體元件302者為層間介電層303(IMD)，一般可選擇低介電係數(low k)的絕緣材料，例如多孔性氧化層。接著於周邊接墊區100B的層間介電層303中製作複數個導電墊結構304。上述導電墊結構304較佳可以由銅(copper；Cu)、鋁(aluminum；Al)或其它合適的金屬材料所製成。
此外，半導體晶圓300在晶圓廠產出時一般係覆蓋有一晶片保護層306(passivation layer)，同時為將晶片內的元件電性連接至外部電路，傳統上晶圓廠會事先定義晶片保護層306以形成複數個暴露出導電墊結構304的開口306h。
接著，如第6A圖所示，提供一半導體晶圓做為一承載基板，如空白或含有電路結構之矽晶圓600，包括一上表 面600a及一下表面600b。其次，自上表面600a處去除部分矽晶圓600以形成複數個開口600h。然後如第6B圖所示，填入絕緣層610於開口600h中，例如是高分子材料，如聚醯亞胺樹脂(polyimide)。或者，藉由半導體製程形成絕緣材料如氧化矽層等，例如透過熱氧化或是電漿化學氣相沈積法全面性形成氧化矽層，然後去除矽晶圓600的上表面600a及/或下表面600b上的氧化矽層。其中值得注意的是，上述矽晶圓600係為重摻雜基板，可透過例如擴散或離子植入步驟，摻雜高濃度的離子如摻雜劑量為1E14~6E15atoms/cm2的磷或砷等形成，以構成一導電路徑。在一實施例中，一個重摻雜區係對應一個導電墊結構，然而，在多個導電墊結構作為共同輸出的情形下，可由一個重摻雜區對應多個導電墊結構。
請參閱第7A圖，接著，將上述具有半導體元件的矽基板300接合至承載基板600上，舉例而言，可將矽基板300翻轉後由上表面300a接合至承載基板600的上表面600a上，使得半導體元件302遠離承載基板600，而導電墊結構304則面向承載基板600的上表面600a接合。其中為方便說明起見，上述矽基板300係僅揭示導電墊結構304、半導体元件302、和層間介電層303。
之後，請參閱第7B圖，藉由例如是蝕刻(etching)、銑削(milling)、磨削(grinding)或研磨(polishing)的方式，從矽基板300的下表面300b處如虛線所示，薄化至一適當的厚度，以半導體元件為影像感測器為例，上述薄化後的矽基板300係被薄化至一可允許足夠的光通過的厚度，使得影像感測器元件 302可感應此入射的光，進而產生訊號，此時矽基板300的下表面300b係作為入光面。
如第7C圖所示，在完成薄化步驟後，提供封裝層500以與半導體晶圓300的下表面300b接合。封裝層500例如為玻璃等透明基板、另一空白矽晶圓、或是另一含有積體電路元件的晶圓。在一實施例中，可藉由間隔層310分開封裝層500與半導體基板，同時形成由間隔層310所圍繞的空腔316。間隔層310可以為密封膠，或是感光絕緣材料，例如環氧樹脂(epoxy)、阻銲材料(solder mask)等。此外間隔層310可先形成於矽基板的下表面300b上，之後再藉由黏著層與相對之封裝層500接合，反之，亦可將間隔層310先形成於封裝層500上，之後再藉由黏著層與相對之矽基板下表面300b接合。
請參閱第7D圖，在一選擇性(optional)步驟中，可以封裝層500為承載基板，對另一承載基板之下表面600b實施一薄化步驟，例如以化學機械研磨製程研磨承載基背面600b，以便於後續暴露出絕緣層610表面，此時，絕緣層610係構成一絕緣壁，可分別隔離承載基板600中對應周邊接墊區100B內的重摻雜區600B。
然後形成保護層640，在本發明實施例中，保護層640例如為阻焊膜(solder mask)，可經由塗佈防銲材料的方式於承載基板之下表面600b處形成保護層640。然後，對保護層640進行圖案化製程，以形成暴露部分承載基板下表面600b的複數個接觸開口。然後，於接觸開口處形成銲球下金屬層(Under Bump Metallurgy,UBM)和導電凸塊650。舉例而言，由導電材 料構成之銲球下金屬層(UBM)可以是金屬或金屬合金，例如鎳層、銀層、鋁層、銅層或其合金；或者是摻雜多晶矽、單晶矽、或導電玻璃層等材料。此外，耐火金屬材料例如鈦、鉬、鉻、或是鈦鎢層，亦可單獨或和其他金屬層結合。而在一特定實施例中，亦可透過重佈線路圖案的形成，重新分布導電凸塊650的位置。
在本發明實施例中，導電凸塊650係用以傳遞元件302中的輸入/輸出(I/O)信號、接地(ground)信號或電源(power)信號。接著，沿著周邊接墊區的切割線SC將上述半導體晶圓分割，即可形成複數個晶片封裝體。
其中，承載基板600於對應週邊接墊區之重摻雜區600B，係由絕緣壁610隔離，因此導電凸塊650可直接或透過重佈線路圖案和重摻雜區600B電性接觸，而不以和導電墊結構304直接接觸為必要。此外由於承載基板600於對應週邊接墊區之重摻雜區600B其區域範圍可較導電墊結構為寬，因此接觸開口可有較高的對準容許誤差。
第8A至8D圖係顯示依據本發明之另一實施例中，形成晶片封裝體之製造方法的剖面示意圖。其中與前述實施例之主要差異在於承載基板600為一絕緣層上覆矽基板(SOI)，其包括一絕緣層630。接續，於承載基板600中形成連接至絕緣層630之絕緣壁610以隔離承載基板中對應該些周邊接墊區100B內之重摻雜區600B。上述絕緣壁和絕緣層一般可為氧化矽材料。其中重摻雜區600B可藉由離子植入步驟完成，其可於絕緣壁610製程之前或之後實施。然後如第8B圖所示，自半導體晶 圓300的背面處300b除去部分半導體晶圓的厚度。接著如第8C-8D圖所示，覆蓋封裝層500後，薄化承載基板600，並依序完成保護層640和導電凸塊650的製作。然而在另一實施例中，於薄化承載基板600的過程中，絕緣層630亦可保留，不必去除。在其他實施例中，上述絕緣層630，係可藉由熱氧化或化學氣相沈積法等半導體製程形成，或者在一實施例中可藉由晶圓接合製程(wafer bonding)結合兩片晶圓而成，其中一片晶圓具有絕緣層。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
300‧‧‧半導體晶圓
300B‧‧‧重摻雜區
301‧‧‧絕緣層
305‧‧‧絕緣壁
304‧‧‧導電墊結構
500‧‧‧封裝層
310‧‧‧間隔層
316‧‧‧空腔
320‧‧‧絕緣層
330‧‧‧重佈線路圖案
340‧‧‧保護層
350‧‧‧導電凸塊

Claims (25)

  1. 一種晶片封裝體，包括：一半導體基板，具有相反之第一表面與第二表面；一導電墊結構，設置於該半導體基板之第一表面；一摻雜區，設於該導電墊結構下方，且與該導電墊結構電性連接，其中該摻雜區係設置於該半導體基板中；以及一導電元件，設於該摻雜區下方，且經由該摻雜區與該導電墊結構形成電性連接，其中該摻雜區之摻雜濃度可使該導電墊結構與該摻雜區下方之該導電元件形成電性連接；一開口，由該半導體基板之第二表面深入該半導體基板中以暴露出該摻雜區；其中該導電元件包括一導電圖案，位於該開口內並電性接觸該摻雜區。
  2. 如申請專利範圍第1項所述之晶片封裝體，其中該導電元件包括：導電凸塊、導電圖案、或前述之組合。
  3. 如申請專利範圍第1項所述之晶片封裝體，其中該導電圖案係深入該摻雜區。
  4. 如申請專利範圍第3項所述之晶片封裝體，其中該開口內之導電圖案與該半導體基板之間係由一絕緣層所隔離。
  5. 如申請專利範圍第1項所述之晶片封裝體，其中該半導體基板更包括：至少一接墊區與至少一元件區，且該導電墊結構設於該接墊區。
  6. 如申請專利範圍第5項所述之晶片封裝體，更包括：一封裝層，接合至該半導體基板；以及一間隔層，設置於該半導體基板與該封裝層之間，且圍繞 該元件區形成一空腔。
  7. 如申請專利範圍第1項所述之晶片封裝體，更包括：複數個摻雜區，該些摻雜區之間係由一絕緣壁隔離。
  8. 如申請專利範圍第7項所述之晶片封裝體，其中該些摻雜區下方更包括一絕緣層，且該絕緣壁係延伸至該絕緣層。
  9. 如申請專利範圍第1項所述之晶片封裝體，其中該摻雜區寬於該導電墊結構。
  10. 如申請專利範圍第1項所述之晶片封裝體，更包括一承載基板，且該承載基板接合至該半導體基板之第一表面。
  11. 如申請專利範圍第10項所述之晶片封裝體，其中該承載基板為一絕緣層上覆矽基板。
  12. 一種晶片封裝體的製造方法，包括：提供一半導體晶圓，具有相反之第一表面與第二表面，該半導體晶圓包括一導電墊結構位於該第一表面；形成一摻雜區於該導電墊結構下方，其中該摻雜區和該導電墊結構形成電性連接，其中該摻雜區係設置於該半導體晶圓中；以及形成一導電元件於該摻雜區下方，其中該導電元件經由該摻雜區與該導電墊結構形成電性連接，其中該摻雜區之摻雜濃度可使該導電墊結構與該摻雜區下方之該導電元件形成電性連接；形成一開口，由該半導體晶圓之第二表面深入該半導體基板中以暴露出該摻雜區；及其中該導電元件的形成包括一形成導電圖案於該開口內並 電性接觸該摻雜區。
  13. 如申請專利範圍第12項所述之晶片封裝體的製造方法，其中該導電元件包括：導電凸塊、導電圖案、或前述之組合。
  14. 如申請專利範圍第12項所述之晶片封裝體的製造方法，其中該導電圖案係深入該摻雜區。
  15. 如申請專利範圍第12項所述之晶片封裝體的製造方法，更包括：於該開口內形成一絕緣層以隔離該導電圖案與該半導體晶圓。
  16. 如申請專利範圍第12項所述之晶片封裝體的製造方法，其中該半導體晶圓更包括：至少一接墊區與至少一元件區，且該導電墊結構設於該接墊區。
  17. 如申請專利範圍第16項所述之晶片封裝體的製造方法，更包括：接合一封裝層至該半導體晶圓，且於該半導體晶圓與該封裝層之間形成由一間隔層所圍繞之空腔。
  18. 如申請專利範圍第12項所述之晶片封裝體的製造方法，更包括：形成複數個摻雜區以及形成一絕緣壁於該些摻雜區之間，以隔離該些摻雜區。
  19. 如申請專利範圍第18項所述之晶片封裝體的製造方法，更包括：於該些摻雜區下方形成一絕緣層，且該絕緣壁係延伸至該絕緣層。
  20. 如申請專利範圍第12項所述之晶片封裝體的製造方法，其中該摻雜區寬於該導電墊結構。
  21. 如申請專利範圍第12項所述之晶片封裝體的製造方法，更 包括：將一承載基板接合至該半導體晶圓之第一表面。
  22. 如申請專利範圍第21項所述之晶片封裝體的製造方法，其中該承載基板為一絕緣層上覆矽基板。
  23. 如申請專利範圍第21項所述之晶片封裝體的製造方法，更包括於該些摻雜區之間形成一絕緣壁而予以隔離。
  24. 如申請專利範圍第23項所述之晶片封裝體的製造方法，更包括將一封裝層接合至該半導體晶圓，且該形成絕緣壁之步驟係於該接合步驟後實施。
  25. 如申請專利範圍第12項所述之晶片封裝體的製造方法，更包括：切割該半導體晶圓以形成複數個晶片封裝體。
TW104107139A 2009-08-19 2010-05-20 晶片封裝體及其製造方法 TWI579995B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US23515309P 2009-08-19 2009-08-19
US23514609P 2009-08-19 2009-08-19

Publications (2)

Publication Number Publication Date
TW201523824A TW201523824A (zh) 2015-06-16
TWI579995B true TWI579995B (zh) 2017-04-21

Family

ID=43604663

Family Applications (2)

Application Number Title Priority Date Filing Date
TW104107139A TWI579995B (zh) 2009-08-19 2010-05-20 晶片封裝體及其製造方法
TW099116113A TWI502705B (zh) 2009-08-19 2010-05-20 晶片封裝體及其製造方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
TW099116113A TWI502705B (zh) 2009-08-19 2010-05-20 晶片封裝體及其製造方法

Country Status (3)

Country Link
US (3) US8497534B2 (zh)
CN (1) CN101996953B (zh)
TW (2) TWI579995B (zh)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI579995B (zh) * 2009-08-19 2017-04-21 Xintex Inc 晶片封裝體及其製造方法
TWI473223B (zh) 2009-08-19 2015-02-11 Xintec Inc 晶片封裝體及其製造方法
WO2011103813A1 (en) * 2010-02-26 2011-09-01 Xintec Inc. Chip package and fabrication method thereof
TWI485818B (zh) * 2011-06-16 2015-05-21 Xintec Inc 晶片封裝體及其形成方法
FR2985088B1 (fr) * 2011-12-23 2015-04-17 Commissariat Energie Atomique Via tsv dote d'une structure de liberation de contraintes et son procede de fabrication
US9548283B2 (en) * 2012-07-05 2017-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package redistribution layer structure and method of forming same
US9520380B2 (en) * 2012-09-01 2016-12-13 Alpha And Omega Semiconductor Incorporated Wafer process for molded chip scale package (MCSP) with thick backside metallization
US9379072B2 (en) * 2013-11-27 2016-06-28 Xintec Inc. Chip package and method for forming the same
TWI560829B (en) * 2014-03-07 2016-12-01 Xintec Inc Chip package and method thereof
CN105110286B (zh) * 2015-06-04 2017-10-03 美新半导体（无锡）有限公司 一种圆片级芯片尺寸封装的微电子机械系统及其制造方法
US9741620B2 (en) * 2015-06-24 2017-08-22 Invensas Corporation Structures and methods for reliable packages
US9564345B1 (en) * 2015-08-18 2017-02-07 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
KR102595276B1 (ko) * 2016-01-14 2023-10-31 삼성전자주식회사 반도체 패키지
JP2017204510A (ja) * 2016-05-09 2017-11-16 キヤノン株式会社 光電変換装置の製造方法
KR102525166B1 (ko) * 2017-11-14 2023-04-24 삼성전자주식회사 이미지 센서
US10340249B1 (en) * 2018-06-25 2019-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10707215B2 (en) * 2018-08-22 2020-07-07 Micron Technology, Inc. Methods of forming semiconductor devices, and related semiconductor devices, memory devices, and electronic systems
JP6871317B2 (ja) 2019-07-26 2021-05-12 藤森工業株式会社 帯電防止表面保護フィルム
US11031462B1 (en) * 2019-12-23 2021-06-08 Nanya Technology Corporation Semiconductor structure with improved guard ring structure
US11309212B2 (en) * 2020-07-30 2022-04-19 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and methods of forming the same
JP7301178B2 (ja) * 2020-09-24 2023-06-30 藤森工業株式会社 帯電防止表面保護フィルム

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050051883A1 (en) * 2003-06-19 2005-03-10 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5920108A (en) * 1995-06-05 1999-07-06 Harris Corporation Late process method and apparatus for trench isolation
US6300148B1 (en) * 1998-10-05 2001-10-09 Advanced Micro Devices Semiconductor structure with a backside protective layer and backside probes and a method for constructing the structure
US6710454B1 (en) * 2000-02-16 2004-03-23 Micron Technology, Inc. Adhesive layer for an electronic apparatus having multiple semiconductor devices
US6887753B2 (en) * 2001-02-28 2005-05-03 Micron Technology, Inc. Methods of forming semiconductor circuitry, and semiconductor circuit constructions
US7115973B1 (en) * 2001-03-08 2006-10-03 National Semiconductor Corporation Dual-sided semiconductor device with a resistive element that requires little silicon surface area
US6686627B2 (en) * 2001-12-26 2004-02-03 Sirenza Microdevices, Inc. Multiple conductive plug structure for lateral RF MOS devices
EP1351288B1 (en) * 2002-04-05 2015-10-28 STMicroelectronics Srl Process for manufacturing an insulated interconnection through a body of semiconductor material and corresponding semiconductor device
US7371462B2 (en) * 2002-04-26 2008-05-13 Kaneka Corporation Hardenable composition, hardening product, process for producing the same and light emitting diode sealed with the hardening product
US6902872B2 (en) * 2002-07-29 2005-06-07 Hewlett-Packard Development Company, L.P. Method of forming a through-substrate interconnect
US6800930B2 (en) * 2002-07-31 2004-10-05 Micron Technology, Inc. Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies
SG111972A1 (en) * 2002-10-17 2005-06-29 Agency Science Tech & Res Wafer-level package for micro-electro-mechanical systems
US6987052B2 (en) * 2003-10-30 2006-01-17 Agere Systems Inc. Method for making enhanced substrate contact for a semiconductor device
US7498647B2 (en) * 2004-06-10 2009-03-03 Micron Technology, Inc. Packaged microelectronic imagers and methods of packaging microelectronic imagers
TWI244152B (en) * 2004-10-22 2005-11-21 Advanced Semiconductor Eng Bumping process and structure thereof
TWI278069B (en) * 2005-08-23 2007-04-01 Nanya Technology Corp Method of fabricating a trench capacitor having increased capacitance
US7491618B2 (en) * 2006-01-26 2009-02-17 International Business Machines Corporation Methods and semiconductor structures for latch-up suppression using a conductive region
KR100794658B1 (ko) * 2006-07-07 2008-01-14 삼성전자주식회사 반도체 칩 제조 방법, 이에 의해 형성된 반도체 칩 및 이를포함하는 칩 스택 패키지
US7816231B2 (en) * 2006-08-29 2010-10-19 International Business Machines Corporation Device structures including backside contacts, and methods for forming same
US20080157342A1 (en) 2007-01-03 2008-07-03 Advanced Chip Engineering Technology Inc. Package with a marking structure and method of the same
CN101236938A (zh) * 2007-02-01 2008-08-06 精材科技股份有限公司 芯片封装模块的散热方法及构造
DE102007034306B3 (de) * 2007-07-24 2009-04-02 Austriamicrosystems Ag Halbleitersubstrat mit Durchkontaktierung und Verfahren zur Herstellung eines Halbleitersubstrates mit Durchkontaktierung
CN101355043B (zh) * 2007-07-26 2010-07-21 精材科技股份有限公司 电子元件封装体及其制作方法
EP2540776B1 (en) * 2007-09-25 2017-08-09 Hitachi Chemical Co., Ltd. Thermosetting light-reflecting resin composition, optical semiconductor element mounting board produced therewith, method for manufacture thereof, and optical semiconductor device
US8178976B2 (en) * 2008-05-12 2012-05-15 Texas Instruments Incorporated IC device having low resistance TSV comprising ground connection
US8987014B2 (en) * 2008-05-21 2015-03-24 Stats Chippac, Ltd. Semiconductor wafer and method of forming sacrificial bump pad for wafer probing during wafer sort test
US8823179B2 (en) 2008-05-21 2014-09-02 Chia-Lun Tsai Electronic device package and method for fabricating the same
TWI508194B (zh) 2009-01-06 2015-11-11 Xintec Inc 電子元件封裝體及其製作方法
JP5618994B2 (ja) * 2009-05-12 2014-11-05 電気化学工業株式会社 粘着剤、粘着シート及び電子部品の製造方法
US8067308B2 (en) * 2009-06-08 2011-11-29 Stats Chippac, Ltd. Semiconductor device and method of forming an interconnect structure with TSV using encapsulant for structural support
TWI579995B (zh) 2009-08-19 2017-04-21 Xintex Inc 晶片封裝體及其製造方法
TWI473223B (zh) * 2009-08-19 2015-02-11 Xintec Inc 晶片封裝體及其製造方法
US8674518B2 (en) * 2011-01-03 2014-03-18 Shu-Ming Chang Chip package and method for forming the same
US8664540B2 (en) * 2011-05-27 2014-03-04 Taiwan Semiconductor Manufacturing Company, Ltd. Interposer testing using dummy connections

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050051883A1 (en) * 2003-06-19 2005-03-10 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument

Also Published As

Publication number Publication date
TWI502705B (zh) 2015-10-01
CN101996953A (zh) 2011-03-30
US8497534B2 (en) 2013-07-30
CN101996953B (zh) 2016-03-02
US20120280389A1 (en) 2012-11-08
US8922026B2 (en) 2014-12-30
TW201142999A (en) 2011-12-01
US20110042804A1 (en) 2011-02-24
US20110042807A1 (en) 2011-02-24
TW201523824A (zh) 2015-06-16
US8748949B2 (en) 2014-06-10

Similar Documents

Publication Publication Date Title
TWI579995B (zh) 晶片封裝體及其製造方法
TWI473223B (zh) 晶片封裝體及其製造方法
TWI629759B (zh) 晶片封裝體及其製造方法
TWI597813B (zh) 晶片封裝體及其製造方法
US8399963B2 (en) Chip package and fabrication method thereof
TWI515838B (zh) 電子元件封裝體及其製造方法
TWI569400B (zh) 晶片封裝體及其形成方法
CN107221540B (zh) 晶片封装体及其制造方法
TW201508882A (zh) 電子元件封裝體及其製造方法
TW201719480A (zh) 指紋感測器裝置與方法
US8810012B2 (en) Chip package, method for forming the same, and package wafer
TW201545297A (zh) 晶片封裝體
TWI500132B (zh) 半導體裝置之製法、基材穿孔製程及其結構
TW201306188A (zh) 晶片封裝體及其製造方法
TWI390688B (zh) Semiconductor device and method for manufacturing semiconductor device
TW201715662A (zh) 晶片封裝體及其製造方法
TWI593069B (zh) 晶片封裝體及其製造方法
TW201222748A (en) Chip package and fabrication method thereof
TWI470708B (zh) 電子元件封裝體及其製作方法
US20230238344A1 (en) Electronic device and method for manufacturing same
TWI539568B (zh) 電子元件封裝體及其製造方法