TWI390688B - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Semiconductor device and method for manufacturing semiconductor device Download PDF

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Publication number
TWI390688B
TWI390688B TW098105312A TW98105312A TWI390688B TW I390688 B TWI390688 B TW I390688B TW 098105312 A TW098105312 A TW 098105312A TW 98105312 A TW98105312 A TW 98105312A TW I390688 B TWI390688 B TW I390688B
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Taiwan
Prior art keywords
hole
semiconductor substrate
insulating film
concave portion
semiconductor device
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TW098105312A
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English (en)
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TW201001645A (en
Inventor
Michihiro Kawashita
Yasuhiro Yoshimura
Naotaka Tanaka
Takahiro Naito
Takashi Akazawa
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Renesas Electronics Corp
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Publication of TW201001645A publication Critical patent/TW201001645A/zh
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Publication of TWI390688B publication Critical patent/TWI390688B/zh

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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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Description

半導體裝置及半導體裝置之製造方法
本發明係關於一種半導體裝置及其製造技術，尤其是關於一種具有三次元層積之複數個半導體晶片的半導體裝置。
近年來，SiP(System in Package：系統級封裝)之開發呈現進展，已有多種安裝構造被提出，而SiP係將複數個半導體晶片(亦有單純稱為「晶片」的情形)作高密度安裝以短時間實現高功能之系統者。尤其，將複數個晶片作層積而可實現大幅度之小型化的層積型封裝之開發係呈現旺盛進展。通常，在晶片間之電性連接上係使用引線接合。此係引線接合鋪設自由度高，在複數個半導體晶片的連接上有效之故。
然而，在引線接合連接方面，由於必須將從一方之晶片所引出之布線暫時推落於搭載基板，作再布線於另一方之晶片，因此晶片間之布線長度變長。藉由此方式，晶片間之電感係增加而使高速傳送變得困難。針對此引線接合連接方面的問題，已有Si(矽)電極貫通技術被提出，其係形成貫通於晶片內部之電極而將晶片間作直接連接。
在日本特開2000-260934號公報(專利文獻1)中，係揭示如下技術：將電極形成於晶片之上下，在將晶片作層積後予以加熱，藉由填入電極之熔融接合而將晶片作三次元式層積，而該電極係藉由電解或無電解電鍍法而將銲錫或低融點金屬填入形成於晶片內之貫通孔部分。
又，在日本特開2007-053149號公報(專利文獻2)中，係揭示如下技術：將形成於上階晶片之柱形凸塊藉由壓接而作變形佈植於形成於下階晶片之中空的貫通電極，將柱形凸塊與貫通電極作幾何學式接合固定，而將晶片作層積。
[專利文獻1]日本特開2000-260934號公報
[專利文獻2]日本特開2007-053149號公報
考慮晶片層積而將貫通電極形成於構成晶片之半導體基板的情形，為了確保導通路，在貫通半導體基板之孔的內面及半導體基板背面側之該孔的周邊設置電極材料。再者，在本申請案中，將設於孔之側面的電極材料作為內部電極，並將設於該孔周邊之電極材料作為背面布線墊。
使用記載於日本特開2007-053149號公報(專利文獻2)之技術而形成貫通電極的情形，由於在比半導體基板之背面更外側，亦即半導體基板之背面上形成背面布線墊，因此在半導體基板背面出現背面布線墊所產生的凸部。本發明者們發現：由於此凸部，在晶片吸附時會產生空氣之外洩，而引起吸附力的下降。因此，認為半導體裝置之製造良率下降。
對此，本發明者們進行了以下的研討。圖1係本發明者們所研討之晶片1C背面的模式性平面圖。再者，為了使構成容易理解，在圖中一部分附有影線。
在構成晶片1C之半導體基板1設有複數個貫通電極4，其平面形狀係以圓形狀顯示。在該貫通電極4周邊的半導體基板1之背面上設有背面布線墊4d，與貫通電極4電性連接。又，為了電性連接背面布線墊4d間，在半導體基板1之背面上設有背面布線4e。再者，背面布線墊4d及背面布線4e係由相同電極材料所構成，從步驟效率化的觀點，在同時形成。
如此，在半導體基板1之背面上設有背面布線墊4d及背面布線4e的情形，如前述會在半導體基板1之背面出現凸部，在晶片1C吸附時產生空氣之外洩，而引起吸附力的下降。
因此，認為在晶片1C之背面未設有背面布線墊4d或背面布線4e的區域形成擬真背面布線墊4f，或在晶片1C背面的周邊區域形成框狀之擬真背面布線4g，將擬真背面布線墊配置於晶片背面全面，藉此消除凸部，可防止空氣之外洩。
然而，在設置背面布線墊4d、背面布線4e、擬真背面布線墊4f及擬真背面布線4g之方法方面，譬如使用Au(金)般之電極材料的情形，由於在晶片1C背面全面配置Au，因而有貫通電極4之製造成本上升的問題。此外，如框狀般細又長之圖案亦有容易剝離的問題。
本發明之目的為提供一種可改善半導體裝置之製造良率的技術。
本發明之其他目的為提供一種可降低半導體裝置之製造成本的技術。
本發明之前述及其他目的與新穎特徵從本說明書之記述及附圖當可理解。
簡單說明在本申請案中所揭示的發明之中具有代表性者之概要如下。
在比背面布線墊及背面布線之圖案更廣之區域，將凹部設於半導體基板之背面側，將背面布線墊及背面布線設於該凹部之內部。
 [發明之效果]
簡單說明在本申請案中所揭示的發明之中由具有代表性者所獲得之效果如下。
可改善半導體裝置之製造良率。
又，可降低半導體裝置之製造成本。
作為在晶片背面之周邊區域形成框等，不配置擬真背面布線墊及擬真背面布線於晶片背面全面，而防止晶片吸附力下降的方法，可考慮以下之技術。
首先，在元件形成面(主面(第1面))已形成有半導體元件的半導體晶圓(晶圓狀態之半導體基板)方面，於與該主面為相反側之背面(第2面)，形成凹部形成用之抗蝕劑遮罩(第1抗蝕劑遮罩)。使用此抗蝕劑遮罩藉由作蝕刻，而形成深於以後續之步驟所形成的擬真背面布線墊之厚度以上的凹部。
其後，在與主面布線墊(第1導電膜)呈對應的凹部內部之位置，形成孔開口用之抗蝕劑遮罩(第2抗蝕劑遮罩)，而主面布線墊(第1導電膜)係與主面之半導體元件呈電性連接。使用此抗蝕劑遮罩藉由作乾式蝕刻，而形成到達半導體晶圓之表面上的層間絕緣膜之孔(第1孔)，其後，變更處理氣體，至少在從半導體晶圓之矽與層間絕緣膜之境界、與主面布線墊之間，於層間絕緣膜形成較深之孔(第1孔)。
在蝕刻後，進行洗淨，藉由CVD法而在孔內面及半導體晶圓之背面形成絕緣膜。為了保護上述絕緣膜而形成Al(鋁)膜。藉由光微影技術而形成在孔底面之一部分具有開口的抗蝕劑遮罩(第3抗蝕劑遮罩)，以蝕刻將孔底面之Al膜與絕緣膜及位於孔底面之層間絕緣膜加工，而形成到達半導體晶圓之表面的電極之接觸孔(第2孔)。
在包含凹部、孔及接觸孔之內面與底面的半導體晶圓之背面，形成金屬晶種層，在已形成之金屬晶種層，藉由光微影技術而形成電鍍用抗蝕劑遮罩(第4抗蝕劑遮罩)，藉由電鍍法而形成電鍍層，而電鍍用抗蝕劑遮罩(第4抗蝕劑遮罩)係形成背面布線及背面布線墊者。在除去電鍍用抗蝕劑遮罩(第4抗蝕劑遮罩)後，在背面布線及背面布線墊設置保護用之抗蝕劑遮罩(第5抗蝕劑遮罩)的包覆，將金屬晶種層作蝕刻，而形成背面布線及背面布線墊(第2導電膜)。此時，由於凹部比背面布線墊之厚度為深，因此背面布線墊表面係位於半導體基板背面更內側。亦即，背面布線及背面布線墊係收納於凹部之內部。
圖2係應用本發明之半導體晶片背面的模式性平面圖。再者，為了使構成容易理解，在圖中一部分係附有影線。
如圖2所示般，在比背面布線墊4d及背面布線4e之圖案更廣之區域，設置凹部100，在該凹部100之內部設置背面布線墊4d及背面布線4e，以防止在比半導體基板1(晶片1C)背面更外側形成背面布線墊表面，避免在晶片背面造成凸部。
貫通電極形成之際，如應用本發明，則可避免在晶片背面形成凸部，可防止晶片吸附力的下降。又，相較於在晶片背面形成背面布線墊之框或擬真圖案的技術，可以低成本防止晶片吸附力下降。
以下，根據圖式將本發明之實施型態作詳細說明。再者，在用於說明實施型態之全部圖中，係對具有同一功能的構件賦予同一符號，有省略其重複之說明的情形。又，在說明以下之實施型態的圖式中，為了使構成容易理解，即使為平面圖，亦有附有影線的情形。
(第1實施型態)
在本實施型態方面，係針對如下情形作說明：譬如，在構成微電腦晶片般之半導體裝置的半導體晶片中，在將貫通電極設置於搭載著高積體電路(半導體元件)的半導體晶片之際，應用本發明。再者，半導體晶片係在半導體元件已形成於半導體基板後，從晶圓狀態之半導體基板(半導體晶圓)所裁切而成者。又，在半導體晶片形成貫通電極之際係成為晶圓狀態。
圖3係本實施型態之半導體裝置的要部之模式性平面圖，圖4係圖3之X1-X1線上的半導體裝置之模式性剖面圖。
如圖4所示般，半導體基板1具有主面1x、及位於其相反側之背面1y。在此半導體基板1之主面1x係形成有半導體元件(未圖示)，以覆蓋該半導體元件之方式，而在半導體基板1之主面1x上形成有層間絕緣膜2。在該層間絕緣膜2之最表面係形成有主面布線墊4a，經由層間絕緣膜2而設於半導體基板1之主面1x上。在該主面布線墊4a上係形成有柱形凸塊(凸塊電極)3。
又，在半導體基板1之背面1y側係形成有凹部100。以從該凹部100之底面貫通半導體基板1的內部之方式，而形成有到達層間絕緣膜2之表面與主面布線墊4a之間的孔5；以從該孔5之底面貫通層間絕緣膜2的內部之方式，比孔5孔徑為小的接觸孔6係形成至主面布線墊4a。
又，在包含孔5、凹部100之底面及側面的半導體基板1之背面1y上，係形成有絕緣膜7。經由該絕緣膜7沿著凹部100及孔5、且沿著接觸孔6而構成金屬晶種層4b與Au膜(構成內部電極4c及背面布線墊4d)的層積膜(導電膜)，基於此因，主面布線墊4a、金屬晶種層4b、內部電極4c及背面布線墊4d係呈電性連接。再者，在本實施型態所使用之Au膜係藉由電鍍法所形成之電鍍層，如非Au膜，而為Au/Ni層積膜等亦可。
因此，本實施型態之半導體裝置的貫通電極4，係具有從孔5與接觸孔6貫通半導體基板1的孔，而孔5係從凹部100的底面到達層間絕緣膜2之孔，且該孔之底面係位於比層間絕緣膜2與半導體基板1之境界更接近主面布線墊4a的位置，而接觸孔6係從孔5之底面到達主面布線墊4a的孔，且比孔5之孔徑為小。再者，貫通電極4具有絕緣膜7、與背面布線墊4d、金屬晶種層4b及內部電極4c，而絕緣膜7係形成於孔5之底面及其側面與凹部100之底面上，而背面布線墊4d係在孔5之底面及其側面上與凹部100之底面上方面，經由絕緣膜7而形成，與主面布線墊4a呈電性接觸而形成於接觸孔6之底面上。
貫通電極4係周圍藉由絕緣膜7及層間絕緣膜而覆蓋，對半導體基板1處於電性絕緣之狀態。又，背面布線墊4d係形成於凹部100內部，背面布線墊之主面101係位於比半導體基板之背面1y更內側。再者，如圖3所示般，作平面觀察時，如凹部100比背面布線墊4d為大，則其平面形狀並不限於圖示之形狀(矩形狀)。
如此般，在比背面布線墊4d之圖案更廣之區域，設置凹部100，在該凹部100之內部設置背面布線墊4d，藉由此方式，則可避免背面布線墊4d之主面101形成於比半導體基板1之背面1y更外側。亦即，可避免在半導體基板1之背面1y造成凸部。又，由於可確保半導體基板1之背面ly的平坦性，因此在作為晶片1C予以處理之際，可防止吸附力的下降。藉由此方式，在半導體裝置的製造上，可改善製造良率，進而可降低製造成本。
接著，參考圖5~圖29，針對圖4所示半導體裝置之製造方法(尤其，貫通電極4之製造方法)作說明。
如圖5所示般，譬如準備包含單結晶矽之10~50 μm程度之厚度的半導體基板1。接著，在半導體基板1之主面(元件形成面)，使用周知之技術，譬如在形成MIS(Metal Insulator Semiconductor：金屬絕緣體半導體)電晶體等半導體元件(未圖示)後，在半導體基板1之主面1x上形成譬如包含氧化矽膜或氮化矽膜的層間絕緣膜2。接著，在半導體基板1之主面1x上以經由層間絕緣膜2之方式，於層間絕緣膜2之表面側形成主面布線墊4a。此主面布線墊4a與已形成於半導體基板1之主面的半導體元件，係藉由層間絕緣膜2而呈電性分離，可使用光微影法、濺鍍法等而譬如從A1膜形成。
在欲形成貫通電極之半導體基板1方面，譬如進行薄型化至10~50 μm程度，則所形成之貫通電極變淺，加工難易度降低，但會引起良率下降，而其係藉由伴隨薄型化之基板強度的下降及基板之撓曲者。
因此，如圖6所示般，在層間絕緣膜2上塗佈黏著層8，將譬如包含石英或玻璃、矽之支持基板9貼合。藉由貼合支持基板9，則可抑制薄型化後之半導體晶圓強度下降及之半導體晶圓之撓曲。又，黏著層8係具有保護積體電路的功能。
接著，如圖7所示般，施行背研處理，將半導體基板1之厚度削薄。就切削之方法而言，有研削、研磨等。由於切削後之平坦性會影響形成於基板1之背面1y的背面布線墊形成精度，因此係以實施乾式拋光或蝕刻、或是CMP(Chemical Mechanical Polish：化學機械研磨)為佳。
接著，如圖8所示般，將光抗蝕劑塗佈於半導體基板1之背面1y上，藉由光微影法，而形成凹部加工用之抗蝕劑遮罩102。作為抗蝕劑塗佈方法，係譬如使用旋轉器塗佈。再者，遮罩形成位置係藉由紅外分光法，確認半導體基板1之主面1x的元件圖案而決定。
接著，如圖9所示般，藉由乾式蝕刻裝置，使用抗蝕劑遮罩102，在半導體基板1之背面1y藉由蝕刻，而形成凹部100。具體而言，係以ICP-RIE(Inductively coupled plasma-Reactive ion etching：感應耦合電漿-反應性離子蝕刻)進行各方異性之蝕刻，而形成凹部100。再者，作為處理氣體係使用SF6 與C4 F8 。凹部100之深度係設為比以後續之步驟所形成的背面布線墊4d之厚度(譬如2 μm程度)更深或同等。
接著，如圖10所示般，藉由有機溶劑或氧灰化而將凹部加工用之抗蝕劑遮罩102除去。
接著，如圖11所示般，將光抗蝕劑塗佈於半導體基板1之背面1y上，藉由光微影法，而形成孔開口用之抗蝕劑遮罩10。作為抗蝕劑塗佈方法，係譬如使用旋轉器塗佈。再者，遮罩形成位置係譬如使用與凹部100同時形成之對準記號而決定。
接著，如圖12所示般，以ICP-RIE進行各方異性之蝕刻，而形成孔5。再者，作為處理氣體係使用SF6 與C4 F8 。通常，在矽之乾式蝕刻方面，由於將氧化矽膜作為遮罩而將矽作蝕刻，因此，在藉由SF6 與C4 F8 之蝕刻方面，在以氧化矽膜作為主成分的層間絕緣膜2，蝕刻係停止。此時之孔5的深度係藉由半導體基板1之厚度而決定。
其後，如圖13所示般，將處理氣體從SF6 與C4 F8 換成與C3 F8 、Ar、CHF4 之混合氣體，展開層間絕緣膜2之加工。此時，並不進行新遮罩的形成。其結果為，將抗蝕劑遮罩10與半導體基板1(矽部)作為遮罩，而展開孔底部之層間絕緣膜2的薄層化。其後，為了將抗蝕劑遮罩10等除去，而藉由有機溶劑或氧灰化作洗淨。藉由此方式，孔5之底面係形成至比層間絕緣膜2與半導體基板1之境界更接近主面布線墊4a的位置。
此時，如將層間絕緣膜2持續加工而形成到達主面布線墊4a的孔5亦可，但接觸主面布線墊4a之層間絕緣膜2係消失，主面布線墊4a之強度下降。因此，如後述般，從自層間絕緣膜2之表面下部到達主面布線墊4a為止的範圍起，係形成比形成於矽部之孔5更小徑的接觸孔6。
接著，如圖14所示般，在包含孔5及凹部100之各自的底面及側面的半導體基板1之背面1y全面上，譬如以CVD(Chemical vapor deposition：化學氣相沉積)法形成絕緣膜7。絕緣膜7係以沿著孔5內壁及半導體基板1之背面1y將該等的面覆蓋之方式形成。作為絕緣膜7係可形成氧化矽、氮化矽、聚醯亞胺樹脂。
接著，如圖15所示般，譬如以濺鍍法，以覆蓋亦包含孔5內壁及凹部100的絕緣膜7之方式，形成絕緣膜保護用之Al(鋁)膜11。形成方法如為蒸鍍法亦可。
接著，如圖16所示般，將光抗蝕劑(抗蝕劑遮罩12)塗佈於亦包含孔5內壁及凹部100的區域。譬如，作為抗蝕劑之塗佈方法，有藉由旋轉器之塗佈與藉由噴霧器之塗佈。以旋轉器作塗佈之情形，為了填入孔5，係以使用可塗佈至5~30 μm厚度的抗蝕劑為佳。再者，如在抗蝕劑之中殘存著氣泡，則在光微影之步驟曝光係變得困難，而發生圖案不良。基於此因，係以藉由真空脫泡將氣泡除去為佳。以噴霧器作塗佈之情形，係與旋轉器塗佈不同，可沿著孔5塗佈抗蝕劑。
接著，如圖17所示般，進行已塗佈於孔5內壁之抗蝕劑的圖案化，在孔5之底面形成接觸孔開口用之抗蝕劑遮罩12。以保護孔5之內壁的抗蝕劑遮罩12不被圖案化之方式，將開口徑形成得較小。再者，在抗蝕劑遮罩12之開口部係出現絕緣膜保護用之Al膜11。
接著，如圖18所示般，藉由以磷酸為主成分之蝕刻液，將開口部之Al膜11除去，使開口部之絕緣膜7露出。再者，作為A1之蝕刻液，如使用稀氟酸亦可。
接著，如圖19所示般，使用抗蝕劑遮罩12將開口部之絕緣膜7與層間絕緣膜2之殘餘全部作加工。藉由此方式，而形成主面布線墊4a露出於開口部之接觸孔6。在加工方面，係使用以CHF3 或C4 F8 氣體為主成分成之混合氣體。以如此方式，而在凹部100之底面形成到達主面布線墊4a之孔5及接觸孔6。
接著，如圖20所示般，藉由有機溶劑或氧灰化而將抗蝕劑遮罩102除去。其後，如圖21所示般，藉由Al之蝕刻溶液而將絕緣膜保護用之Al膜11除去。此時，由於薄之主面布線墊4a露出於開口部，因此主面布線墊4a不溶於蝕刻液係重要之事。
接著，如圖22所示般，在包含孔5之內部的半導體基板1之背面1y(絕緣膜7)上，譬如以濺鍍法形成金屬晶種層13。作為形成之金屬晶種層13，可考慮譬如包含Ti(鈦)膜與Au(金)膜的層積。在Ti膜方面，為了確保絕緣膜7與Au膜的密合性，而形成為0.02 μm~0.3 μm程度之厚度，在Au膜方面，作為電鍍之晶種，如具有0.3 μm~2 μm程度之厚度即可。作為金屬晶種層除Ti膜與Au膜的層積膜外，亦可考慮譬如Cr膜與Au膜的層積膜。
接著，如圖23所示般，藉由光微影技術而形成抗蝕劑遮罩14。此抗蝕劑遮罩係在後續之形成電鍍膜之步驟使用。
接著，如圖24所示般，譬如，藉由電性電鍍法而形成成為內部電極4c及背面布線墊4d的Au膜15(電鍍層)。在形成之電鍍膜厚方面，考慮電性電阻，係以1 μm以上為佳，但以用Au膜15之膜厚使貫通電極4的內徑成為特定之徑之方式予以調節。作為Au膜15之形成方法，係可考慮無電解電鍍法、濺鍍法等。再者，作為電鍍膜雖亦可考慮Au膜與Cu膜的層積，但如從晶片層積及晶圓層積之觀點，最表面係以設為Au膜為佳。
接著，如圖25所示般，藉由有機溶劑或氧灰化而將電鍍用之抗蝕劑遮罩14除去。其後，如圖26所示般，藉由光微影步驟將抗蝕劑作圖案化，而形成覆蓋孔5及背面布線墊4d的保護用之抗蝕劑遮罩16。
接著，如圖27所示般，將呈露出之金屬晶種層13(Au膜與Ti膜)，分別藉由Au之蝕刻溶液與Ti之蝕刻溶液予以除去。再者，作為Ti之蝕刻溶液係譬如可考慮氟酸，但如為其他蝕刻溶液亦可。
以如此方式，而形成構成金屬晶種層4b及背面布線墊4d的導電膜，而金屬晶種層4b及背面布線墊4d係在凹部100之底面上方面，經由絕緣膜7，在接觸孔6之底面上方面，與主面布線墊4a呈電性連接。
接著，如圖28所示般，將保護用之抗蝕劑遮罩16除去，而結束半導體基板1之加工。其後，如圖29所示般，從半導體基板1進行支持基板9之剝下。譬如，如為熱可塑性之黏著層8，則藉由加熱而進行剝下。然後，將晶圓狀態之半導體基板1藉由刀具切割而單片化為晶片1C。單片化為晶片一事，雖在半導體基板1黏附於支持基板9之狀態下亦可進行，但如已將各支持基板9單片化，則無法進行支持基板9的再利用。雖然操作變得較困難，但藉由將支持基板9剝離而進行切割，則支持基板9的再利用係變為可能。
接著，如圖4所示般，譬如藉由柱形凸塊法，而將凸塊3形成於位於半導體基板1之主面1x側的主面布線墊4a。作為凸塊之形成方法，有錫膏凸塊法、電鍍法、蒸鍍法等。
如此般，在形成貫通電極4之際，如應用本發明，則可避免在晶片1C(半導體基板1)之背面1y形成凸部，可防止晶片吸附力的下降。又，相較於在晶片1C之背面1y形成背面布線墊4d之框狀的擬真背面布線或擬真背面布線墊的情形，以低成本可防止晶片吸附力下降。如此般，在本實施型態之半導體裝置方面，可改善製造良率，可降低製造成本。
(第2實施型態)
在本實施型態方面，係針對如下情形作說明：譬如，在構成微電腦晶片般之半導體裝置的半導體晶片中，在將鄰接之複數個貫通電極設置於搭載著高積體電路(半導體元件)的半導體晶片之際，應用本發明。具體而言，在前述第1實施型態中，係針對在1個凹部內部具有1個貫通電極之情形作說明，但在本實施型態中，係針對在1個凹部內部具有複數個貫通電極之情形作說明。再者，與前述第1本實施型態，係僅在1個凹部內部具有複數個貫通電極之點為不同，因此，有省略與前述第1本實施型態同樣之說明的情形。
圖30係本實施型態之半導體裝置的要部之模式性平面圖，圖31係圖30之X2-X2線上的半導體裝置之模式性剖面圖。在1個凹部100內部係譬如設有1~3個貫通電極4。將複數個貫通電極4設置於半導體基板1的情形，譬如亦可在1個凹部100內部係設置1個貫通電極4。然而，當考慮鄰接之貫通電極4的窄間距化之對應的情形，則會有礙於確保鄰接之凹部100的間距。因此，在本實施型態中，藉由將複數個貫通電極4設置於1個凹部100內部，則對應於貫通電極4的窄間距化。
再者，本實施型態之貫通電極係使用在前述第1實施型態參考圖5~圖29所說明之製造方法作同樣形成，因此省略其說明。
(第3實施型態)
在本實施型態方面，係針對如下情形作說明：譬如，在構成微電腦晶片般之半導體裝置的半導體晶片中，在將貫通電極與布線鋪設用之背面布線設置於搭載著高積體電路(半導體元件)的半導體晶片之際，應用本發明。再者，與前述第1實施型態，係僅在凹部內部除貫通電極外並具有布線鋪設用的背面布線之點為不同，因此，有省略與前述第1實施型態同樣之說明的情形。
圖32係本實施型態之半導體裝置的要部之模式性平面圖，圖33係圖32之X3-X3線上的半導體裝置之模式性剖面圖。
如圖33所示般，在半導體基板1之主面1x係形成有半導體元件(未圖示)，以覆蓋該半導體元件之方式而形成有層間絕緣膜2。又，在半導體基板1之背面1y係設有凹部100，在該凹部100內部係設有由金屬晶種層4b與內部電極4c所構成的背面布線4e。此背面布線4e係形成於凹部100內部，背面布線4e之主面101係位於比半導體基板1之背面1y之更內側。再者，如圖32所示般，作平面觀察時，如凹部100比背面布線4e為大，則其平面形狀並不限於圖示之形狀。
如此般，在比背面布線4e之圖案更廣之區域，設置凹部100，在該凹部100之內部設置背面布線4e，則可防止背面布線4e之主面101形成於比半導體基板1之背面1y更外側，可避免在半導體基板1之背面1y造成凸部。又，由於可確保半導體基板1之背面1y的平坦性，因此在作為晶片1C予以處理之際，可防止吸附力的下降。藉由此方式，在半導體裝置的製造上，可改善製造良率，進而可降低製造成本。
接著，參考圖34~圖50，針對圖33所示半導體裝置之製造方法(尤其，背面布線4e之製造方法)作說明。再者，將與前述第1實施型態同一步驟(圖5~圖7)的說明予以省略，而針對其以後之步驟作說明。
如圖34所示般，將光抗蝕劑塗佈於半導體基板1之背面1y上，藉由光微影法，而形成凹部加工用之抗蝕劑遮罩102。然後，如圖35所示般，以ICP-RIE進行各方異性之蝕刻，而形成凹部100。凹部100之深度係設為比在以後所形成之背面布線4e之厚度更深或同等。其後，藉由有機溶劑或氧灰化而將凹部加工用之抗蝕劑遮罩102從半導體基板1除去(圖36)。
接著，如圖37所示般，將光抗蝕劑塗佈於半導體基板1，藉由光微影法，以覆蓋凹部之方式而形成抗蝕劑遮罩10。藉由此方式，即使進行在前述第1實施型態所說明之圖9的加工，藉由抗蝕劑遮罩10而覆蓋之區域並未被加工。然後，在孔5之形成結束後，將殘存之抗蝕劑遮罩10藉由有機溶劑或氧灰化予以洗淨(圖38、圖12)。其後，如圖39所示般，在包含凹部100的半導體基板1之背面1y全面，譬如以CVD(Chemical vapor deposition：化學氣相沉積)法形成絕緣膜7。絕緣膜7係以在孔5內部沿著孔內壁及背面將該等的面覆蓋之方式形成(圖14)。
接著，如圖40所示般，譬如以濺鍍法，以亦包含凹部100而覆蓋絕緣膜7之方式，形成Al膜11。此時，在孔5內面及底面亦形成絕緣膜保護用之Al膜11(圖15)。形成方法如為蒸鍍法亦可。然後，如圖41所示般，以覆蓋凹部100之方式形成抗蝕劑遮罩12。藉由此方式，即使進行在前述第1實施型態所說明之圖18及圖19所示加工，藉由抗蝕劑遮罩12而覆蓋之區域並未被加工。其後，藉由有機溶劑或氧灰化而將絕緣膜開口用之抗蝕劑遮罩12從半導體基板1除去(圖42)。
接著，將絕緣膜保護用之Al膜11藉由Al之蝕刻溶液予以除去(圖43)。接著，為了將金屬晶種層13譬如以濺鍍法形成於包含孔5內部之半導體基板1(圖22)，如圖44所示般，在絕緣膜7上形成金屬晶種層13。然後，如圖45所示般，藉由光微影技術而將電鍍用之抗蝕劑遮罩14形成於金屬晶種層13上。
接著，如圖46所示般，譬如藉由電性電鍍法而將成為背面布線4e之Au膜15，形成於從抗蝕劑遮罩14之開口部露出的金屬晶種層13上。此Au膜15係構成內部電極4c及背面布線墊4d(圖24)。然後，藉由有機溶劑或氧灰化而將電鍍用之抗蝕劑遮罩14從半導體基板1除去(圖47)。其後，如圖48所示般，藉由藉由光微影步驟將抗蝕劑作圖案化，而將保護用之抗蝕劑遮罩16形成於金屬晶種層13上。此時，係以覆蓋孔5及背面布線墊4d之方式形成保護用之抗蝕劑遮罩16(圖26)。
接著，如圖49所示般，將呈露出之金屬晶種層13(Au膜與Ti膜)，分別藉由Au之蝕刻溶液與Ti之蝕刻溶液予以除去。然後，藉由將保護用之抗蝕劑遮罩16除去，而結束半導體基板1之加工(圖50)。藉由此方式，係在與前述第1實施型態所示背面布線墊4d同時，於凹部100之底面上形成由金屬晶種層13/Au膜15之層積膜所構成的背面布線4e。
接著，從半導體基板1進行支持基板9之剝下。譬如，如為熱可塑性之黏著層8，則藉由加熱而進行剝下(圖51)。其後，將晶圓狀態之半導體基板1藉由刀具切割而單片化為晶片1C(圖33)。
如此般，在形成背面布線4e之際，如應用本發明，則可避免在晶片1C(半導體基板1)之背面1y形成凸部，可防止晶片吸附力的下降。如此般，在本實施型態之半導體裝置方面，可改善製造良率，可降低製造成本。
(第4實施型態)
在本實施型態方面，係針對將在前述第1實施型態所示半導體晶片層積而構成之半導體裝置作說明。圖52係本實施型態之半導體裝置的模式性剖面圖，圖53係將圖52之半導體裝置作分解顯示之模式性平面圖。
在圖52中，係為了將2片晶片作層積，而將進行再布線之中介層晶片22插入上述2片晶片間，搭載於布線基板23，而該2片晶片係搭載著以在前述第1實施型態所示半導體晶片所構成之譬如微電腦晶片20與SDRAM晶片21的高積體電路。
各晶片間係將形成於上階晶片之柱形凸塊3藉由壓接而作變形佈植於形成於下階晶片之中空的貫通電極4，作幾何學式接合固定而呈電性連接。在布線基板23之下側係形成有銲錫凸塊24，使用於與外部之連接用。藉由此方式，微電腦晶片20之貫通電極4與中介層晶片22之柱形凸塊3係呈幾何學式接合固定，而層積於微電腦晶片20之背面ly上。又，中介層晶片22之貫通電極4與SDRAM晶片21之柱形凸塊3係呈幾何學式接合固定，而層積於中介層晶片22之背面1y上。
在將各晶片(微電腦晶片20、SDRAM晶片21、中介層晶片22)與布線基板23作層積後，以封閉用黏著材25將各晶片與布線基板23之間填滿，在提高機械強度、提高半導體裝置之組裝時之操作性的同時，並從外部環境將半導體元件予以保護。
如圖53所示般，在各晶片之背面1y係形成有背面布線26，經由貫通電極4，布線彼此呈三次元式連結而構成三次元布線。因而，背面布線26係可作為同電位線使用，譬如，可考慮作為接地線、電源線、信號線的利用。藉由作如此之使用，由於可降低作為半導體裝置全體之布線電感，因此可使動作高速化。
以上，雖根據實施型態將藉由本發明者所研發之發明作了具體說明，但本發明並不限定於前述實施型態，而可在不超出其要旨之範圍內作各種變更，此點毋庸置疑。
譬如，在前述實施型態中，係針對如下情形作說明：將柱形凸塊與貫通電極作幾何學式接合固定而將晶片作層積。然而，除柱形凸塊之外，亦可應用於使用銲錫凸塊或電鍍凸塊與貫通電極作幾何學式接合固定之情形。
(產業上之可利用性)
本發明係廣泛利用於半導體裝置(尤其，具有呈三次元式層積之複數個半導體晶片的半導體裝置)之製造業。
1．．．半導體基板
1x．．．主面(第1面)
1y．．．背面(第2面)
1C．．．晶片
2．．．層間絕緣膜
3．．．柱形凸塊(凸塊電極)
4．．．貫通電極
4a．．．主面布線墊(第1導電膜)
4b．．．金屬晶種層(第2導電膜)
4c．．．內部電極(第2導電膜)
4d．．．背面布線墊(第2導電膜)
4e．．．背面布線(第2導電膜)
4f．．．擬真背面布線墊
4g．．．擬真背面布線
5．．．孔(第1孔)
6．．．接觸孔(第2孔)
7．．．絕緣膜
8．．．黏著層
9．．．支持基板
10．．．抗蝕劑遮罩(第2抗蝕劑遮罩)
11．．．Al膜
12．．．抗蝕劑遮罩(第3抗蝕劑遮罩)
13．．．金屬晶種層(第2導電膜)
14．．．抗蝕劑遮罩(第4抗蝕劑遮罩)
15．．．Au膜(第2導電膜)
16．．．抗蝕劑遮罩(第5抗蝕劑遮罩)
20．．．微電腦晶片
21．．．SDRAM晶片
22．．．中介層晶片
23．．．布線基板
24．．．銲錫凸塊
25．．．封閉用黏著材
26．．．背面布線
100．．．凹部
101．．．主面
102．．．抗蝕劑遮罩(第1抗蝕劑遮罩)
圖1係本發明者們所研討之半導體晶片背面的模式性平面圖。
圖2係應用本發明之半導體晶片背面的模式性平面圖。
圖3係本發明之一實施型態之半導體裝置的要部之模式性平面圖。
圖4係圖3之X1-X1線上的半導體裝置之模式性剖面圖。
圖5係本發明之一實施型態之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖6係延續圖5之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖7係延續圖6之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖8係延續圖7之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖9係延續圖8之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖10係延續圖9之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖11係延續圖10之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖12係延續圖11之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖13係延續圖12之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖14係延續圖13之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖15係延續圖14之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖16係延續圖15之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖17係延續圖16之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖18係延續圖17之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖19係延續圖18之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖20係延續圖19之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖21係延續圖20之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖22係延續圖21之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖23係延續圖22之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖24係延續圖23之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖25係延續圖24之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖26係延續圖25之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖27係延續圖26之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖28係延續圖27之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖29係延續圖28之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖30係本發明之其他實施型態之半導體裝置的要部之模式性平面圖。
圖31係圖30之X2-X2線上的半導體裝置之模式性剖面圖。
圖32係本發明之其他實施型態之半導體裝置的要部之模式性平面圖。
圖33係圖32之X3-X3線上的半導體裝置之模式性剖面圖。
圖34係本發明之其他實施型態之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖35係延續圖34之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖36係延續圖35之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖37係延續圖36之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖38係延續圖37之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖39係延續圖38之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖40係延續圖39之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖41係延續圖40之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖42係延續圖41之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖43係延續圖42之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖44係延續圖43之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖45係延續圖44之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖46係延續圖45之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖47係延續圖46之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖48係延續圖47之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖49係延續圖48之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖50係延續圖49之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖51係延續圖50之製造步驟中之半導體裝置的要部之模式性剖面圖。
圖52係本發明之其他實施型態之半導體裝置的要部之模式性剖面圖。
圖53係將圖52之半導體裝置作分解顯示之模式性平面圖。
1．．．半導體基板
1C．．．晶片
4．．．貫通電極
4d．．．背面布線墊
4e．．．背面布線
100．．．凹部

Claims (11)

  1. 一種半導體裝置，其包括：半導體基板，其係具有第1面、及位於與其相反側的第2面；層間絕緣膜，其係形成於前述半導體基板之第1面上；第1導電膜，其係經由前述層間絕緣膜而形成於前述半導體基板之第1面上；凹部，其係形成於前述半導體基板之第2面；孔，其係形成於前述凹部之底面，到達前述第1導電膜；絕緣膜，其係形成於前述凹部之底面上；及第2導電膜，其係在前述凹部之底面上經由前述絕緣膜而形成，與前述第1導電膜電性連接，形成於前述孔之底面上。
  2. 如請求項1之半導體裝置，其中前述第2導電膜收納於前述凹部之內部。
  3. 如請求項1之半導體裝置，其中前述孔、前述絕緣膜及前述第2導電膜構成貫通電極；前述貫通電極具有：前述第1孔，其係構成前述孔，從前述凹部之底面到達前述層間絕緣膜，且前述第1孔之底面位於比前述層間絕緣膜與前述半導體基板之境界更接近前述第1導電膜的位置；前述第2孔，其係構成前述孔，從前述第1孔之底面到達前述第1導電膜，且比前述第1孔之孔徑小；前述絕緣膜，其係形成於前述第1孔之底面及其側面上與前述凹部之底面上；及前述第2導電膜，其係在前述第1孔之底面及其側面上與前述凹部之底面上經由前述絕緣膜而形成，與前述第1導電膜電性連接，形成於前述第2孔之底面上。
  4. 如請求項3之半導體裝置，其中前述半導體基板之前述貫通電極與其他半導體基板之凸塊電極係呈用幾何學式嵌塞，而在前述半導體基板之第2面上層積有前述其他半導體基板。
  5. 如請求項4之半導體裝置，其中前述凹部底面上之前述第2導電膜構成與前述貫通電極電性連接之布線；以前述貫通電極、前述凸塊電極及前述布線構成三次元布線。
  6. 如請求項5之半導體裝置，其中前述三次元布線構成同電位線。
  7. 一種半導體裝置之製造方法，其包含以下步驟：(a)準備半導體基板，其係具有第1面、及位於與其相反側的第2面；(b)在前述半導體基板之第1面上形成層間絕緣膜；(c)在前述半導體基板之第1面上，經由前述層間絕緣膜而形成第1導電膜；(d)在前述半導體基板之第2面形成凹部；(e)在前述凹部之底面上形成絕緣膜；(f)在前述凹部之底面，形成到達前述第1導電膜之孔；及(g)在前述凹部之底面上經由前述絕緣膜，而在前述孔之底面上形成與前述第1導電膜電性連接之第2導電膜。
  8. 如請求項7之半導體裝置之製造方法，其中在前述(d)步驟中，形成前述第2導電膜之厚度以上深的前述凹部。
  9. 如請求項7之半導體裝置之製造方法，其中在前述(g)步驟中，在前述凹部之底面上同時形成由前述第2導電膜所構成之布線及布線墊。
  10. 如請求項7之半導體裝置之製造方法，其中在前述(g)步驟中，藉由層積金屬晶種層與電鍍層而形成前述第2導電膜；在前述(f)步驟之後，在前述凹部之底面上經由前述絕緣膜，在前述孔之底面上形成與前述第1導電膜電性連接之前述金屬晶種層，在前述金屬晶種層上形成前述電鍍層。
  11. 一種半導體裝置之製造方法，其包含以下步驟：(a)在準備具有主面、及位於與其相反側之背面的半導體基板後，在前述半導體基板之主面形成半導體元件，在前述半導體基板之主面上形成層間絕緣膜；(b)在前述半導體基板之主面上，經由前述層間絕緣膜而形成主面布線墊；(c)在前述半導體基板之背面形成第1抗蝕劑遮罩，使用前述第1抗蝕劑遮罩於前述半導體基板藉由蝕刻形成凹部後，將前述第1抗蝕劑遮罩除去；(d)在與前述主面布線墊之位置相對之前述凹部底面的一部分形成具有開口部之第2抗蝕劑遮罩，使用前述第2抗蝕劑遮罩於前述半導體基板藉由蝕刻形成第1孔後，將前述第2抗蝕劑遮罩除去；(e)在包含前述第1孔內部的前述半導體基板背面上形成絕緣膜；(f)在前述絕緣膜上形成鋁膜；(g)在前述(f)步驟之後，在前述第1孔底面的一部分形成具有開口部之第3抗蝕劑遮罩，使用前述第3抗蝕劑遮罩將前述鋁膜、前述絕緣膜、前述半導體基板及前述層間絕緣膜分別藉由蝕刻除去，而形成到達前述主面布線墊之第2孔後，將前述第3抗蝕劑遮罩除去；(h)在前述第2孔、前述第1孔、前述凹部之各底面及側面、以及前述半導體基板之背面上形成金屬晶種層；(i)在前述凹部的一部分、前述第1孔及前述第2孔形成具有開口部之第4抗蝕劑遮罩，藉由使用前述第4抗蝕劑遮罩之電鍍法在前述金屬晶種層上形成電鍍層後，將前述第4抗蝕劑遮罩除去；及(j)形成覆蓋前述電鍍層之第5抗蝕劑遮罩，藉由將未以前述第5抗蝕劑遮罩覆蓋的前述金屬晶種層除去，而在前述凹部之底面上形成由前述金屬晶種層及前述電鍍層所構成的背面布線墊後，將前述第5抗蝕劑遮罩除去。
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