CN101609828A - 半导体器件以及半导体器件的制造方法 - Google Patents

半导体器件以及半导体器件的制造方法 Download PDF

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Publication number
CN101609828A
CN101609828A CNA2009101426602A CN200910142660A CN101609828A CN 101609828 A CN101609828 A CN 101609828A CN A2009101426602 A CNA2009101426602 A CN A2009101426602A CN 200910142660 A CN200910142660 A CN 200910142660A CN 101609828 A CN101609828 A CN 101609828A
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mentioned
semiconductor substrate
hole
recess
semiconductor device
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CN101609828B (zh
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川下道宏
吉村保广
田中直敬
内藤孝洋
赤泽隆
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Desella Advanced Technology Company
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Renesas Technology Corp
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Abstract

本发明提供一种半导体器件以及半导体器件的制造方法。如果在芯片背面形成贯通电极以及背面布线，则通过作为贯通电极的一部分的背面布线焊盘以及背面布线，在芯片背面形成凸部。以此为原因，在吸附芯片时引起空气的泄漏而引起芯片吸附力降低。在形成背面布线焊盘(4d)以及背面布线(4e)的区域中，预先形成凹部(100)。在该凹部(100)内部设置背面布线焊盘(4d)以及背面布线(4e)。由此，通过由于背面布线焊盘(4d)以及背面布线(4e)厚度而产生的凸部，确保芯片(1C)背面的平坦性，而不会在处理芯片(1C)时造成吸附力降低。

Description

半导体器件以及半导体器件的制造方法
技术领域
本发明涉及半导体器件及其制造技术，特别涉及具有三维地层叠的多个半导体芯片的半导体器件。
背景技术
近年来，高密度地安装多个半导体芯片(还简称为“芯片”)而短时间地实现高功能的系统的SIP(System in Package，系统级封装)的开发得到了发展，并提出了多种安装结构。特别使多个芯片层叠，而可以大幅实现小型化的层叠型封装的开发得到了发展。通常，在芯片间的电连接中，使用引线键合。其原因为，引线键合的卷绕自由度高，且对于多个半导体芯片的连接是有效的。
但是，在引线键合连接中，需要使从一个芯片引出的布线临时落于搭载衬底上，并对另一个芯片再次布线，所以芯片间的布线长度变长。由此，芯片间的电感增加而难以实现高速传送。针对该引线键合连接中的课题，提出了形成在芯片内部贯通的电极，而直接连接芯片间的Si(硅)贯通电极技术。
在日本特开2000-260934号公报(专利文献1)中，公开了如下技术：在芯片的上下形成对形成在芯片内的贯通孔部分通过电镀或无电镀法而埋入焊锡或低熔点金属的电极，层叠了芯片之后进行加热，通过埋入电极的熔融接合而三维地层叠芯片。
另外，在日本特开2007-053149号公报(专利文献2)中，公开了如下技术：通过压接向形成于下级芯片中的中空的贯通电极变形注入形成于上级芯片中的柱形凸缘(stud bump)，并对柱形凸缘与贯通电极几何学地进行铆接而层叠芯片。
专利文献1：日本特开2000-260934号公报
专利文献2：日本特开2007-053149号公报
当考虑芯片层叠，而在构成芯片的半导体衬底上形成贯通电极的情况下，为了确保导通路径，在贯通半导体衬底的孔的内面以及半导体衬底背面侧的该孔的周边设置有电极材料。另外，在本申请中，将设置于孔的侧面的电极材料设为内部电极，并且将设置于该孔周边的电极材料设为背面布线焊盘。
在使用日本特开2007-053149号公报(专利文献2)记载的技术形成贯通电极的情况下，由于在半导体衬底的背面的外侧、即半导体衬底的背面上形成有背面布线焊盘，所以可以通过背面布线焊盘在半导体衬底背面形成凸部。本发明者发现了起因于该凸部，而在吸附芯片时发生空气的泄漏，从而引起吸附力降低的现象。因此，半导体器件的制造成品率降低。
对应于此，本发明者进行了以下的研究。图1是本发明者研究的芯片1C的背面的示意俯视图。另外，为了易于理解结构而对图中的一部分附加了阴影线。
在构成芯片1C的半导体衬底1中设置有多个贯通电极4，其平面形状呈现圆形形状。在该贯通电极4的周边的半导体衬底1的背面上设置有背面布线焊盘4d，并与贯通电极4电连接。另外，以电连接背面布线焊盘4d间的形式，在半导体衬底1的背面上设置有背面布线4e。另外，背面布线焊盘4d以及背面布线4e由相同电极材料构成，从工序的效率化的观点出发，而同时形成。
当这样在半导体衬底1的背面上设置有背面布线焊盘4d以及背面布线4e的情况下，如上所述在半导体衬底1的背面形成凸部，而在吸附芯片1C时发生空气的泄漏，从而引起吸附力降低。
因此，考虑如下方法：在芯片1C的背面，在未设置背面布线焊盘4d、背面布线4e的区域，形成虚拟背面布线焊盘4f，在芯片1C的背面中的周边区域，形成框状的虚拟背面布线4g，并在整个芯片背面配置虚拟的背面布线焊盘，从而消除凸部，而可以防止空气的泄漏。
但是，在设置背面布线焊盘4d、背面布线4e、虚拟背面布线焊盘4f以及虚拟背面布线4g的方法中，例如在使用Au(金)那样的电极材料的情况下，由于在整个芯片1C背面配置Au，所以存在贯通电极4的制造成本上升的问题。而且，还存在如框状那样细长的图案易于剥落这样的问题。
发明内容
本发明的目的在于提供一种可以改善半导体器件的制造成品率的技术。
本发明的另一目的在于提供一种可以降低半导体器件的制造成本的技术。
本发明的上述以及其他目的和新特征根据本说明书的记述以及附图将更加明确。
如果简单说明本申请公开的发明中的代表性的发明的概要，则如下所述。
比背面布线焊盘以及背面布线的图案更广域地在半导体衬底的背面侧设置凹部，并在该凹部的内部设置背面布线焊盘以及背面布线。
如果简单说明通过本申请公开的发明中的代表性的发明而得到的效果，则如下所述。
可以改善半导体器件的制造成品率。
另外，可以降低半导体器件的制造成本。
附图说明
图1是本发明者研究的半导体芯片背面的示意俯视图。
图2是应用了本发明的半导体芯片背面的示意俯视图。
图3是本发明的一个实施方式中的半导体器件的要部的示意俯视图。
图4是图3的X1-X1线处的半导体器件的示意剖面图。
图5是本发明的一个实施方式中的制造工序中的半导体器件的要部的示意剖面图。
图6是接着图5的制造工序中的半导体器件的要部的示意剖面图。
图7是接着图6的制造工序中的半导体器件的要部的示意剖面图。
图8是接着图7的制造工序中的半导体器件的要部的示意剖面图。
图9是接着图8的制造工序中的半导体器件的要部的示意剖面图。
图10是接着图9的制造工序中的半导体器件的要部的示意剖面图。
图11是接着图10的制造工序中的半导体器件的要部的示意剖面图。
图12是接着图11的制造工序中的半导体器件的要部的示意剖面图。
图13是接着图12的制造工序中的半导体器件的要部的示意剖面图。
图14是接着图13的制造工序中的半导体器件的要部的示意剖面图。
图15是接着图14的制造工序中的半导体器件的要部的示意剖面图。
图16是接着图15的制造工序中的半导体器件的要部的示意剖面图。
图17是接着图16的制造工序中的半导体器件的要部的示意剖面图。
图18是接着图17的制造工序中的半导体器件的要部的示意剖面图。
图19是接着图18的制造工序中的半导体器件的要部的示意剖面图。
图20是接着图19的制造工序中的半导体器件的要部的示意剖面图。
图21是接着图20的制造工序中的半导体器件的要部的示意剖面图。
图22是接着图21的制造工序中的半导体器件的要部的示意剖面图。
图23是接着图22的制造工序中的半导体器件的要部的示意剖面图。
图24是接着图23的制造工序中的半导体器件的要部的示意剖面图。
图25是接着图24的制造工序中的半导体器件的要部的示意剖面图。
图26是接着图25的制造工序中的半导体器件的要部的示意剖面图。
图27是接着图26的制造工序中的半导体器件的要部的示意剖面图。
图28是接着图27的制造工序中的半导体器件的要部的示意剖面图。
图29是接着图28的制造工序中的半导体器件的要部的示意剖面图。
图30是本发明的其他实施方式中的半导体器件的要部的示意俯视图。
图31是图30的X2-X2线处的半导体器件的示意剖面图。
图32是本发明的其他实施方式中的半导体器件的要部的示意俯视图。
图33是图32的X3-X3线处的半导体器件的示意剖面图。
图34是本发明的其他实施方式中的制造工序中的半导体器件的要部的示意剖面图。
图35是接着图34的制造工序中的半导体器件的要部的示意剖面图。
图36是接着图35的制造工序中的半导体器件的要部的示意剖面图。
图37是接着图36的制造工序中的半导体器件的要部的示意剖面图。
图38是接着图37的制造工序中的半导体器件的要部的示意剖面图。
图39是接着图38的制造工序中的半导体器件的要部的示意剖面图。
图40是接着图39的制造工序中的半导体器件的要部的示意剖面图。
图41是接着图40的制造工序中的半导体器件的要部的示意剖面图。
图42是接着图41的制造工序中的半导体器件的要部的示意剖面图。
图43是接着图42的制造工序中的半导体器件的要部的示意剖面图。
图44是接着图43的制造工序中的半导体器件的要部的示意剖面图。
图45是接着图44的制造工序中的半导体器件的要部的示意剖面图。
图46是接着图45的制造工序中的半导体器件的要部的示意剖面图。
图47是接着图46的制造工序中的半导体器件的要部的示意剖面图。
图48是接着图47的制造工序中的半导体器件的要部的示意剖面图。
图49是接着图48的制造工序中的半导体器件的要部的示意剖面图。
图50是接着图49的制造工序中的半导体器件的要部的示意剖面图。
图51是接着图50的制造工序中的半导体器件的要部的示意剖面图。
图52是本发明的其他实施方式中的半导体器件的要部的示意剖面图。
图53是将图52中的半导体器件分解而示出的示意俯视图。
标号说明
1半导体衬底
1x主面(第一面)
1y背面(第二面)
1C芯片
2层间绝缘膜
3柱形凸缘(凸缘电极)
4贯通电极
4a主面布线焊盘(第一导电膜)
4b金属种子层(第二导电膜)
4c内部电极(第二导电膜)
4d背面布线焊盘(第二导电膜)
4e背面布线(第二导电膜)
4f虚拟背面布线焊盘
4g虚拟背面布线
5孔(第一孔)
6接触孔(第二孔)
7绝缘膜
8粘接层
9支撑衬底
10抗蚀剂掩模(第二抗蚀剂掩模)
11Al膜
12抗蚀剂掩模(第三抗蚀剂掩模)
13金属种子层(第二导电膜)
14抗蚀剂掩模(第四抗蚀剂掩模)
15Au膜(第二导电膜)
16抗蚀剂掩模(第五抗蚀剂掩模)
20微型机芯片
21SDRAM芯片
22内插芯片
23布线衬底
24焊锡凸缘
25密封用粘接材料
26背面布线
100凹部
101主面
102抗蚀剂掩模(第一抗蚀剂掩模)
具体实施方式
作为在芯片背面的周边区域形成框等，不在整个芯片背面配置虚拟背面布线焊盘以及虚拟背面布线，而防止芯片吸附力降低的方法，考虑以下技术。
首先，在作为元件形成面的主面(第一面)中形成有半导体元件的半导体晶片(晶片状态的半导体衬底)中，在与该主面相反一侧的背面(第二面)，形成凹部形成用的抗蚀剂掩模(第一抗蚀剂掩模)。使用该抗蚀剂掩模通过干蚀刻，形成深度为在后面的工序中形成的背面布线焊盘的厚度以上的凹部。
之后，在和与主面的半导体元件电连接的主面布线焊盘(第一导电膜)对应的凹部内部的位置，形成孔开口用的抗蚀剂掩模(第二抗蚀剂掩模)。使用该抗蚀剂掩模通过干蚀刻形成达到半导体晶片的表面上的层间绝缘膜的孔(第一孔)，之后变更工艺气体，至少从半导体晶片的硅与层间绝缘膜的边界直到与主面布线焊盘之间在层间绝缘膜中更深地形成孔(第一孔)。
在蚀刻之后进行洗净，通过CVD法在孔内面以及半导体晶片的背面形成绝缘膜。为了保护上述绝缘膜而形成Al(铝)膜。通过光刻技术，在孔底面的一部分中形成具有开口的抗蚀剂掩模(第三抗蚀剂掩模)，通过蚀刻对孔底面的Al膜、绝缘膜、位于孔底面的层间绝缘膜进行加工，而形成达到半导体晶片的表面的电极的接触孔(第二孔)。
在包括凹部、孔以及接触孔的内面与底面的半导体晶片的背面形成金属种子层，在所形成的金属种子层中通过光刻技术形成用于形成背面布线以及背面布线焊盘的镀敷用的抗蚀剂掩模(第四抗蚀剂掩模)，通过镀敷法形成镀敷层。在去除了镀敷用的抗蚀剂掩模之后，在背面布线以及背面布线焊盘中设置保护用的抗蚀剂掩模(第五抗蚀剂掩模)的罩，对金属种子层进行蚀刻，而形成背面布线以及背面布线焊盘(第二导电膜)。此时，凹部由于比背面布线焊盘的厚度深，所以背面布线焊盘表面位于半导体衬底背面的内侧。即，背面布线以及背面布线焊盘收容于凹部的内部中。
图2是应用了本发明的半导体芯片背面的示意俯视图。另外，为了易于理解结构而对图中的一部分附加了阴影线。
如图2所示，比背面布线焊盘4d以及背面布线4e的图案更广域地设置凹部100，并在该凹部100的内部设置背面布线焊盘4d以及背面布线4e，而防止在半导体衬底1(芯片1C)背面的外侧形成背面布线焊盘表面，防止在芯片背面形成凸部。
如果在形成贯通电极时应用本发明，则可以防止在芯片背面形成凸部，而可以防止芯片吸附力降低。另外，与在芯片背面形成背面布线焊盘的框、虚拟图案的技术相比，可以低成本地防止芯片吸附力降低。
以下，根据附图对本发明的实施方式进行详细说明。另外，在用于说明实施方式的全部图中，有时对具有同一功能的部件附加同一标号，而省略其重复的说明。另外，在说明以下的实施方式的图中，为了易于理解结构而在俯视图中也有时附加了阴影线。
(实施方式1)
在本实施方式中，对如下的情况进行说明：在例如微型机芯片那样的构成半导体器件的半导体芯片中，在向搭载有高集成电路(半导体元件)的半导体芯片设置贯通电极时，应用本发明。另外，半导体芯片是在半导体衬底中形成了半导体元件之后，从晶片状态的半导体衬底(半导体晶片)切出而成的。另外，在半导体芯片中形成贯通电极时成为晶片状态。
图3是本实施方式中的半导体器件的要部的示意俯视图，图4是图3的X1-X1线处的半导体器件的示意剖面图。
如图4所示，半导体衬底1具有主面1x以及与其相反一侧的背面1y。在该半导体衬底1的主面1x中形成有半导体元件(未图示)，以覆盖该半导体元件的形式在半导体衬底1的主面1x上形成有层间绝缘膜2。在该层间绝缘膜2的最表面形成有主面布线焊盘4a，在半导体衬底1的主面1x上隔着层间绝缘膜2而设置。在该主面布线焊盘4a上形成有柱形凸缘3(凸缘电极)。
另外，在半导体衬底1的背面1y侧形成有凹部100。以从该凹部100的底面贯通半导体衬底1的内部的形式，形成达到层间绝缘膜2的表面与主面布线焊盘4a之间的孔5，以从该孔5的底面贯通层间绝缘膜2的内部的形式，直到主面布线焊盘4a为止地形成孔径比孔5小的接触孔6。
另外，在包括孔5、凹部100的底面以及侧面的半导体衬底1的背面1y上形成有绝缘膜7。隔着该绝缘膜7沿着凹部100以及孔5，并且沿着接触孔6，构成金属种子层4b与Au膜(构成内部电极4c以及背面布线焊盘4d)的层叠膜(导电膜)，所以主面布线焊盘4a、金属种子层4b、内部电极4c、以及背面布线焊盘4d被电连接。另外，本实施方式中使用的Au膜是通过镀敷法形成的镀敷层，既可以是Au膜，也可以是Au/Ni层叠膜等。
因此，本实施方式中的半导体器件的贯通电极4具有：从凹部100的底面达到层间绝缘膜2、且底面比层间绝缘膜2与半导体衬底1的边界更靠近主面布线焊盘4a的孔5；以及从孔5的底面达到主面布线焊盘4a，且从孔径小于孔5的接触孔6贯通半导体衬底1的孔。而且，贯通电极4具有：形成在孔5的底面及其侧面上和凹部100的底面上的绝缘膜7；在孔5的底面及其侧面上和凹部100的底面上隔着绝缘膜7形成，且与主面布线焊盘4a电连接而形成在接触孔6的底面上的背面布线焊盘4a、金属种子层4b以及内部电极4c。
贯通电极4被绝缘膜7以及层间绝缘膜2覆盖其周围，而处于从半导体衬底1电绝缘的状态。另外，背面布线焊盘4d形成在凹部100内部，背面布线焊盘的主面101位于半导体衬底的背面1y的内侧。而且，只要如图3所示俯视时凹部100大于背面布线焊盘4d，则其平面形状不限于图示的形状(矩形形状)。
这样，通过比背面布线焊盘4d的图案更广域地设置凹部100，并在该凹部100的内部设置背面布线焊盘4d，可以防止在半导体衬底1的背面1y的外侧形成背面布线焊盘4d的主面101。即，可以防止在半导体衬底1的背面1y形成凸部。另外，由于可以确保半导体衬底1的背面1y的平坦性，所以在作为芯片1C进行处理时，可以防止吸附力降低。由此，在半导体器件的制造中，可以改善制造成品率，而且可以降低制造成本。
接下来，参照图5～图29对图4所示的半导体器件的制造方法、特别是贯通电极4的制造方法进行说明。
准备如图5所示，例如由单晶硅构成的10～50μm左右的厚度的半导体衬底1。接下来，在半导体衬底1的主面(元件形成面)中，使用公知技术例如形成MIS(Metal Insulator Semiconductor，金属绝缘体半导体)晶体管等半导体元件(未图示)之后，在半导体衬底1的主面1x上形成例如由氧化硅膜、氮化硅膜构成的层间绝缘膜2。接下来，在半导体衬底1的主面1x上以隔着层间绝缘膜2的形式，在层间绝缘膜2的表面侧形成主面布线焊盘4a。该主面布线焊盘4a与形成在半导体衬底1的主面上的半导体元件通过层间绝缘膜2被电分离，可以使用光刻法、溅射法等例如由Al膜形成。
在形成贯通电极的半导体衬底1中，在例如薄型化为10～50μm左右时，形成的贯通电极变浅而加工难易度降低，但由于伴随薄型化的衬底强度降低以及衬底的弯曲而引起成品率降低。
因此，如图6所示在层间绝缘膜2上涂敷粘接层8，而粘贴例如由石英、玻璃、硅构成的支撑衬底9。通过粘贴支撑衬底9，可以抑制薄型化后的半导体晶片强度降低以及半导体晶片的弯曲。另外，粘接层8还具有保护集成电路的作用。
接下来，如图7所示，实施背面研磨处理，将半导体衬底1的厚度削薄。作为切削的方法，有研削、研磨等。切削后的平坦性由于对形成在衬底的背面1y中的背面布线焊盘形成精度造成影响，所以优选实施干抛光、蚀刻、或者CMP(Chemical Mechanical Polish，化学机械抛光)。
接下来，如图8所示，在半导体衬底1的背面1y上涂敷抗蚀剂掩模，通过光刻法，形成凹部加工用的抗蚀剂掩模102。作为抗蚀剂涂敷方法，例如使用旋转涂敷。另外，通过红外分光法确认半导体衬底1的主面1x的器件图案而决定掩模形成位置。
接下来，如图9所示，利用干蚀刻装置使用抗蚀剂掩模102在半导体衬底1的背面1y中通过蚀刻形成凹部100。具体而言，通过ICP-RIE(Inductively coupled plasma-Reactive ion etching，感应耦合等离子体活性离子蚀刻)进行各向异性的蚀刻，而形成凹部100。另外，将SF6和C4F8用作工艺气体。凹部100的深度设为比通过以后的工序形成的背面布线焊盘4d的厚度(例如2μm左右)深、或者等同。
接下来，如图10所示，通过有机溶剂、氧灰化(ashing)去除凹部加工用的抗蚀剂掩模102。
接下来，如图11所示，在半导体衬底1的背面1y上涂敷光致抗蚀剂，通过光刻法，形成孔开口用的抗蚀剂掩模10。作为抗蚀剂涂敷方法，例如使用旋转涂敷。另外，例如使用与凹部100同时形成的对位标记来决定掩模形成位置。
接下来，如图12所示，通过ICP-RIE进行各向异性的蚀刻，而形成孔5。另外，将SF6和C4F8用作工艺气体。通常在硅的干蚀刻中，由于以氧化硅膜为掩模而对硅进行蚀刻，所以在利用SF6和C4F8的蚀刻中，在以氧化硅膜为主成分的层间绝缘膜2中蚀刻被阻止。此时的孔5的深度由半导体衬底1的厚度决定。
之后，如图13所示将工艺气体从SF6和C4F8改变为C3F8、Ar、CHF4的混合气体，而进行层间绝缘膜2的加工。此时，不形成新的掩模。其结果，以抗蚀剂掩模10和半导体衬底1(硅部)为掩模而进行孔底部的层间绝缘膜2的薄层化。之后，为了去除抗蚀剂掩模10等，通过有机溶剂、氧灰化进行洗净。由此，直到比层间绝缘膜2与半导体衬底1的边界更靠近主面布线焊盘4a的位置为止形成孔5的底面。
此时，虽然也可以继续加工层间绝缘膜2而形成达到主面布线焊盘4a的孔5，但与主面布线焊盘4a相接的层间绝缘膜2消失，而主面布线焊盘4a的强度降低。因此，如后所述，从从层间掩模2的表面下部直到达到主面布线焊盘4a的范围，形成比形成在硅部中的孔5较小径的接触孔6。
接下来，如图14所示，在包括孔5以及凹部100各自的底面以及侧面的半导体衬底1的背面1y整个面上，例如通过CVD(Chemicalvapor deposition，化学气相沉积)法形成绝缘膜7。以沿着孔5内壁以及半导体衬底1的背面1y覆盖它们的面的形式，形成绝缘膜7。作为绝缘膜7，可以形成氧化硅、氮化硅、聚酰亚胺树脂。
接下来，如图15所示，例如通过溅射法以覆盖还包括孔5内壁以及凹部100的绝缘膜7的形式，形成绝缘膜保护用的Al(铝)膜11。形成方法也可以是蒸镀法。
接下来，如图16所示，对还包括孔5内壁以及凹部100的区域涂敷光致抗蚀剂(抗蚀剂掩模12)。例如作为抗蚀剂的涂敷方法，有利用旋转器的涂敷和利用喷雾器的涂敷。在使用旋转器涂敷的情况下，优选使用为了埋入孔5而可以涂敷为5～30μm厚度的抗蚀剂。而且在抗蚀剂中残存气泡时，在光刻的工序中曝光变得困难而发生图案不良。因此，优选通过真空脱泡去除气泡。在使用喷雾器涂敷的情况下，与旋转器涂敷不同，而可以沿着孔5涂敷抗蚀剂。
接下来，如图17所示，进行对孔5内壁涂敷的抗蚀剂的图案化，在孔5的底面形成接触孔开口用的抗蚀剂掩模12。较小地形成开口径，以使保护孔5的内壁的抗蚀剂掩模12不被图案化。另外，在抗蚀剂掩模12的开口部中，出现绝缘膜保护用的Al膜11。
接下来，如图18所示，利用以磷酸为主成分的蚀刻液，去除开口部的Al膜11，而使开口部的绝缘膜7露出。另外，也可以将稀氢氟酸等用作Al的蚀刻液。
接下来，如图19所示，使用抗蚀剂掩模12将开口部的绝缘膜7和层间绝缘膜2的剩余全部加工。由此，形成在开口部使主面布线焊盘4a露出的接触孔6。在加工中使用以CHF3和C4F8气体为主成分的混合气体。这样，在凹部100的底面形成达到主面布线焊盘4a的孔5以及接触孔6。
接下来，如图20所示，通过有机溶剂、氧灰化来去除抗蚀剂掩模12。之后，如图21所示，利用Al的蚀刻溶液去除绝缘膜保护用的Al膜11。此时，由于在开口部中露出薄的主面布线焊盘4a，所以不使主面布线焊盘4a溶于蚀刻液是重要的。
接下来，如图22所示，在包括孔5的内部的半导体衬底1的背面1y(绝缘膜7)上例如通过溅射法形成金属种子层13。作为要形成的金属种子层13，例如考虑由Ti(钛)膜和Au(金)膜构成的叠层。为了确保绝缘膜7与Au膜的密接性而使Ti膜形成为0.02μm～0.3μm左右的厚度，Au膜作为镀敷的种子而是0.3μm～2μm左右的厚度即可。作为金属种子层，除了Ti膜与Au膜的层叠膜以外，例如还考虑Cr膜与Au膜的层叠膜。
接下来，如图23所示，通过光刻技术形成抗蚀剂掩模14。在后面的形成镀敷膜的工序中使用该抗蚀剂掩模。
接下来，如图24所示，例如通过电镀法形成成为内部电极4c以及背面布线焊盘4d的Au膜15(镀敷层)。在考虑电气电阻时，要形成的镀敷膜厚优选为1μm以上，但通过Au膜15的膜厚进行调节以使贯通电极4的内径成为规定的径。作为Au膜15的形成方法，考虑无电镀法、溅射法等。另外，作为镀敷膜还考虑Au膜与Cu膜的层叠，但从芯片层叠以及晶片层叠的观点出发，最表面优选设为Au膜。
接下来，如图25所示，通过有机溶剂、氧灰化去除镀敷用的抗蚀剂掩模14。之后，如图26所示，通过光刻工序对抗蚀剂进行图案化，而形成覆盖孔5以及背面布线焊盘4d的保护用的抗蚀剂掩模16。
接下来，如图27所示，利用Au的蚀刻溶液和Ti的蚀刻溶液分别去除作为露出的金属种子层13的Au膜和Ti膜。另外，作为Ti膜的蚀刻溶液，例如考虑氢氟酸，但也可以是其他蚀刻溶液。
这样，在凹部100的底面上隔着绝缘膜7，形成在接触孔6的底面上构成与主面布线焊盘4a电连接的金属种子层4b以及背面布线焊盘4d的导电膜。
接下来，如图28所示，去除保护用的抗蚀剂掩模16，而半导体衬底1的加工完成。之后，如图29所示，从半导体衬底1剥离支撑衬底9。例如，如果是热可塑性的粘接层8，则通过加热而进行剥离。接下来，将晶片状态的半导体衬底1通过刀具切割而个片化为芯片1C。也可以在支撑衬底9上粘贴了半导体衬底1的状态下进行向芯片的个片化，但在支撑衬底9被个片化时，无法再次利用支撑衬底9。虽然处理变得困难，但通过剥离支撑衬底9来进行切割，可以再次利用支撑衬底9。
接下来，如图4所示，在处于半导体衬底1的主面1x侧的主面布线焊盘4a，例如通过柱形凸缘法形成凸缘3。作为凸缘的形成方法，有焊膏凸缘法、镀敷法、蒸镀法等。
如果这样在形成贯通电极4时应用本发明，则可以防止在芯片1C(半导体衬底1)的背面1y形成凸部，而可以防止芯片吸附力降低。另外，与在芯片1C的背面1y形成背面布线焊盘4d的框状的虚拟背面布线、虚拟背面布线焊盘的情况相比，可以低成本地防止芯片吸附力降低。这样在本实施方式的半导体器件中，可以改善制造成品率，可以降低制造成本。
(实施方式2)
在本实施方式中，对如下情况进行说明：在例如微型机芯片那样的构成半导体器件的半导体芯片中，在向搭载有高集成电路(半导体元件)的半导体芯片设置邻接的多个贯通电极时，应用本发明。具体而言，在上述实施方式1中对在一个凹部内部具有一个贯通电极的情况进行了说明，但在本实施方式中对在一个凹部内部具有多个贯通电极的情况进行说明。另外，与上述实施方式1相比，仅在一个凹部内部具有多个贯通电极的点不同，所以有时省略与上述实施方式1相同的说明。
图30是本实施方式中的半导体器件的要部的示意俯视图。图31是图30的X2-X2线处的半导体器件的示意剖面图。在一个凹部100内部，例如设置有一～三个贯通电极4。在半导体衬底1中设置有多个贯通电极4的情况下，例如还可以在一个凹部100内部设置一个贯通电极4。但是，在考虑了邻接的贯通电极4的窄间距化的对应的情况下，有时妨碍确保所邻接的凹部100的间距。因此，在本实施方式中，通过在一个凹部100内部设置多个贯通电极4，而对应于贯通电极4的窄间距化。
另外，由于可以使用在上述实施方式1中参照图5～图29说明的制造方法同样地形成本实施方式中的贯通电极，所以省略其说明。
(实施方式3)
在本实施方式中，对如下情况进行说明：在例如微型机芯片那样的构成半导体器件的半导体芯片中，在向搭载有高集成电路(半导体元件)的半导体芯片设置贯通电极以及布线引出用的背面布线时，应用本发明。另外，与上述实施方式1相比，仅是在凹部内部除了贯通电极以外还具有布线引出用的背面布线这一点不同，所以有时省略与上述实施方式1相同的说明。
图32是本实施方式中的半导体器件的要部的示意俯视图，图33是图32的X3-X3线处的半导体器件的示意剖面图。
如图33所示，在半导体衬底1的主面1x中形成有半导体元件(未图示)，并以覆盖该半导体元件的形式形成有层间绝缘膜2。另外，在半导体衬底1的背面1y中设置有凹部100，在该凹部100内部设置有由金属种子层4b和内部电极4c构成的背面布线4e。该背面布线4e形成在凹部100内部，背面布线4e的主面101位于半导体衬底1的背面1y的内侧。另外，只要如图32所示俯视时凹部100大于背面布线4e，则其平面形状不限于图示的形状。
这样，比背面布线4e的图案更广域地设置凹部100，并在该凹部100的内部设置背面布线4e，而可以防止在半导体衬底1的背面1y的外侧形成背面布线4e的主面101，防止在半导体衬底1的背面1y中形成凸部。另外，由于可以确保半导体衬底1的背面1y的平坦性，所以在作为芯片1C进行处理时，可以防止吸附力降低。由此，在半导体器件的制造中，可以改善制造成品率，而且可以降低制造成本。
接下来，参照图34～图50对图33所示的半导体器件的制造方法、特别是背面布线4e的制造方法进行说明。另外，省略作为与上述实施方式1相同的工序的图5～图7的说明，而对其后的工序进行说明。
如图34所示，在半导体衬底1的背面1y上涂敷光致抗蚀剂，通过光刻法，形成凹部加工用的抗蚀剂掩模102。接下来，如图35所示通过ICP-RIE进行各向异性的蚀刻，而形成凹部100。凹部100的深度比以后形成的背面布线4e的厚度深或等同。之后，通过有机溶剂、氧灰化从半导体衬底1中去除凹部加工用的抗蚀剂掩模102(图36)。
接下来，如图37所示，对半导体衬底1涂敷光致抗蚀剂，通过光刻法，以覆盖凹部的形式形成抗蚀剂掩模10。由此，即使进行了上述实施方式1中说明的图9的加工，也不会加工由抗蚀剂掩模10覆盖的区域。接下来，在孔5的形成完成之后，通过有机溶剂、氧灰化洗净所剩余的抗蚀剂掩模10(图38、图12)。之后，如图39所示，在包括凹部100的半导体衬底1的背面1y整个面，例如通过CVD(Chemical vapor deposition)法形成绝缘膜7。以在孔5内部沿着孔内壁以及背面覆盖它们的面的形式，形成绝缘膜7(图14)。
接下来，如图40所示，例如通过溅射法以还包括凹部100地覆盖绝缘膜7的形式形成Al膜11。此时，在孔5内面以及底面中也进行绝缘膜保护用的Al膜11(图15)。形成方法也可以是蒸镀法。接下来，如图41所示，以覆盖凹部100的形式形成抗蚀剂掩模12。由此，即使进行了上述实施方式1中说明的图18以及图19所示的加工，也不会加工由抗蚀剂掩模12覆盖的区域。之后，通过有机溶剂、氧灰化从半导体衬底1中去除绝缘间开口用的抗蚀剂掩模12(图42)。
接下来，利用Al的蚀刻溶液去除绝缘膜保护用的Al膜11(图43)。接下来，为了在包括孔5的内部的半导体衬底1中例如通过溅射法形成金属种子层13(图22)，而如图44所示，在绝缘膜7上形成金属种子层13。接下来，如图45所示，通过光刻技术在金属种子层13上形成镀敷用的抗蚀剂掩模14。
接下来，如图46所示，例如通过电镀法在从抗蚀剂掩模14的开口部露出的金属种子层13上形成成为背面布线4e的Au膜15。该Au膜15构成内部电极4c以及背面布线焊盘4d(图24)。接下来，通过有机溶剂、氧灰化从半导体衬底1中去除镀敷用的抗蚀剂掩模14(图47)。之后，如图48所示，通过光刻工序对抗蚀剂进行图案化，而在金属种子层13上形成保护用的抗蚀剂掩模16。此时，以覆盖孔5以及背面布线焊盘4d的形式，形成保护用的抗蚀剂掩模16(图26)。
接下来，如图49所示，分别利用Au的蚀刻溶液和Ti的蚀刻溶液去除作为露出的金属种子层13的Au膜和Ti膜。接下来，通过去除保护用的抗蚀剂掩模16，半导体衬底1的加工完成(图50)。由此，与上述实施方式1中示出的背面布线焊盘4d同时，在凹部10的底面上形成由金属种子层13/Au膜15的层叠膜构成的背面布线4e。
接下来，从半导体衬底1剥离支撑衬底9。例如，如果是热可塑性的粘接层8，则通过加热而进行剥离(图51)。之后，将晶片状态的半导体衬底1通过刀具切割而个片化为芯片1C(图33)。
如果这样在形成背面布线4e时应用本发明，则可以防止在芯片1C(半导体衬底1)的背面1y中形成凸部，而可以防止芯片吸附力降低。这样在本实施方式的半导体器件中，可以改善制造成品率，可以降低制造成本。
(实施方式4)
在本实施方式中，对将上述实施方式1中示出的半导体芯片层叠而构成的半导体器件进行说明。图52是本实施方式中的半导体器件的示意剖面图，图53是将图52中的半导体器件分解而示出的示意俯视图。
在图52中，为了层叠由上述实施方式1中示出的半导体芯片构成的例如微型机芯片20和SDRAM芯片21的搭载有高集成电路的两个芯片，将用于进行再布线的内插芯片22插入于上述两个芯片间，而搭载于布线衬底23上。
各芯片间是通过压接向形成于下级芯片的中空的贯通电极4变形注入形成于上级芯片中的柱形凸缘3，并几何学地进行铆接而电连接的。在布线衬底23的下侧，形成有焊锡凸缘24，用于与外部的连接。由此，微型机芯片20的贯通电极4与内插芯片22的柱形凸缘3被几何学地铆接，而层叠在微型机芯片20的背面1y上。另外，内插芯片22的贯通电极4与SDRAM芯片21的柱形凸缘3被几何学地铆接，而层叠在内插芯片22的背面1y上。
在层叠了各芯片(微型机芯片20、SDRAM芯片21、内插芯片22)与布线衬底23之后，用密封用粘接材料25添埋各芯片、布线衬底23之间，提高机械强度而提高半导体器件的组装时的可操作性，并且从外部环境保护半导体元件。
如图53所示，在各芯片的背面1y中形成有背面布线26，布线彼此经由贯通电极4三维地连接而构成三维布线。因此，背面布线26可以用作同电位线，例如可以用作地线、电源线、信号线。通过这样使用，可以降低作为半导体器件整体的布线电感，所以可以使动作高速化。
以上，根据实施方式对由本发明者完成的发明进行了具体说明，但本发明不限于上述实施方式，而可以在不脱离其要旨的范围内进行各种变更。
例如，在上述实施方式中，对几何学地铆接柱形凸缘与贯通电极而层叠芯片的情况进行了说明，但除了柱形凸缘以外，还可以应用于使用焊锡凸缘、镀敷凸缘而与贯通电极铆接的情况。
产业上的可利用性
本发明广泛用于半导体器件、特别是具有三维地层叠的多个半导体芯片的半导体器件的制造业中。

Claims (11)

1.一种半导体器件，其特征在于，具有：
具有第一面以及与其相反一侧的第二面的半导体衬底；
形成在上述半导体衬底的第一面上的层间绝缘膜；
在上述半导体衬底的第一面上隔着上述层间绝缘膜形成的第一导电膜；
形成在上述半导体衬底的第二面中的凹部；
形成在上述凹部的底面，且达到上述第一导电膜的孔；
形成在上述凹部的底面上的绝缘膜；以及
在上述凹部的底面上隔着上述绝缘膜形成，且与上述第一导电膜电连接而形成在上述孔的底面上的第二导电膜。
2.根据权利要求1所述的半导体器件，其特征在于，
上述第二导电膜收容于上述凹部的内部中。
3.根据权利要求1所述的半导体器件，其特征在于，
上述孔、上述绝缘膜以及上述第二导电膜构成贯通电极，
上述贯通电极具有：
构成上述孔，且从上述凹部的底面达到上述层间绝缘膜，且底面比上述层间绝缘膜与上述半导体衬底的边界更靠近上述第一导电膜的第一孔；
构成上述孔，且从上述第一孔的底面达到上述第一导电膜，且孔径小于上述第一孔的第二孔；
形成在上述第一孔的底面及其侧面上和上述凹部的底面上的上述绝缘膜；以及
在上述第一孔的底面及其侧面上和上述凹部的底面上隔着上述绝缘膜形成，且与上述第一导电膜电连接而形成在上述第二孔的底面上的上述第二导电膜。
4.根据权利要求3所述的半导体器件，其特征在于，
上述半导体衬底的上述贯通电极与其他半导体衬底的凸缘电极被几何学地铆接，而上述其他半导体衬底层叠在上述半导体衬底的第二面上。
5.根据权利要求4所述的半导体器件，其特征在于，
上述凹部的底面上的上述第二导电膜构成与上述贯通电极电连接的布线，
由上述贯通电极、上述凸缘电极以及上述布线构成三维布线。
6.根据权利要求5所述的半导体器件，其特征在于，
上述三维布线构成同电位线。
7.一种包括以下步骤的半导体器件的制造方法：
(a)准备具有第一面以及与其相反一侧的第二面的半导体衬底的步骤；
(b)在上述半导体衬底的第一面上形成层间绝缘膜的步骤；
(c)在上述半导体衬底的第一面上隔着上述层间绝缘膜形成第一导电膜的步骤；
(d)在上述半导体衬底的第二面上形成凹部的步骤；
(e)在上述凹部的底面上形成绝缘膜的步骤；
(f)在上述凹部的底面中，形成达到上述第一导电膜的孔的步骤；以及
(g)在上述凹部的底面上隔着上述绝缘膜，形成在上述孔的底面上与上述第一导电膜电连接的第二导电膜的步骤。
8.根据权利要求7所述的半导体器件的制造方法，其特征在于，
在上述(d)步骤中，形成深度为上述第二导电膜的厚度以上的上述凹部。
9.根据权利要求7所述的半导体器件的制造方法，其特征在于，
在上述步骤(g)中，在上述凹部的底面上同时形成由上述第二导电膜构成的布线以及布线焊盘。
10.根据权利要求7所述的半导体器件的制造方法，其特征在于，
在上述步骤(g)中，通过层叠金属种子层与镀敷层而形成上述第二导电膜，
在上述步骤(f)之后，在上述凹部的底面上隔着上述绝缘膜，形成在上述孔的底面上与上述第一导电膜电连接的上述金属种子层，在上述金属种子层上形成上述镀敷层。
11.一种包括以下步骤的半导体器件的制造方法：
(a)在准备了具有主面以及与其相反一侧的背面的半导体衬底之后，在上述半导体衬底的主面形成半导体元件，在上述半导体衬底的主面上形成层间绝缘膜的步骤；
(b)在上述半导体衬底的主面上隔着上述层间绝缘膜形成主面布线焊盘的步骤；
(c)在上述半导体衬底的背面形成第一抗蚀剂掩模，使用上述第一抗蚀剂掩模在上述半导体衬底中通过蚀刻形成了凹部之后，去除上述第一抗蚀剂掩模的步骤；
(d)在与上述主面布线焊盘的位置相对的上述凹部的底面的一部分形成具有开口部的第二抗蚀剂掩模，使用上述第二抗蚀剂掩模在上述半导体衬底中通过蚀刻形成了第一孔之后，去除上述第二抗蚀剂掩模的步骤；
(e)在包括上述第一孔的内部的上述半导体衬底的背面上形成绝缘膜的步骤；
(f)在上述绝缘膜上形成铝膜的步骤；
(g)在上述步骤(f)之后，在上述第一孔的底面的一部分形成具有开口部的第三抗蚀剂掩模，使用上述第三抗蚀剂掩模通过蚀刻分别去除上述铝膜、上述绝缘膜、上述半导体衬底以及上述层间绝缘膜，形成了达到上述主面布线焊盘的第二孔之后，去除上述第三抗蚀剂掩模的步骤；
(h)在上述第二孔、上述第一孔、上述凹部各自的底面以及侧面、以及上述半导体衬底的背面上形成金属种子层的步骤；
(i)在上述凹部的一部分、上述第一孔以及上述第二孔中形成具有开口部的第四抗蚀剂掩模，通过使用了上述第四抗蚀剂掩模的镀敷法在上述金属种子层上形成了镀敷层之后，去除上述第四抗蚀剂掩模的步骤；以及
(j)形成覆盖上述镀敷层的第五抗蚀剂掩模，通过去除未由上述第五抗蚀剂掩模覆盖的上述金属种子层而在上述凹部的底面上形成了由上述金属种子层以及上述镀敷层构成的背面布线焊盘之后，去除上述第五抗蚀剂掩模的步骤。
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