CN101996953B - 芯片封装体及其制造方法 - Google Patents

芯片封装体及其制造方法 Download PDF

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Publication number
CN101996953B
CN101996953B CN201010250512.5A CN201010250512A CN101996953B CN 101996953 B CN101996953 B CN 101996953B CN 201010250512 A CN201010250512 A CN 201010250512A CN 101996953 B CN101996953 B CN 101996953B
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Prior art keywords
heavily doped
those
doped regions
chip packing
conductive
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Expired - Fee Related
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CN201010250512.5A
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CN101996953A (zh
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刘建宏
周正德
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XinTec Inc
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XinTec Inc
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Abstract

本发明公开一种芯片封装体及其制造方法。实施例的芯片封装体包括：一半导体基板，具有相反的第一表面与第二表面，以及至少一接垫区与至少一元件区；多个导电垫结构，位于半导体基板的第一表面，且位于半导体基板的接垫区上；多个相互隔离的重掺杂区，设于导电垫结下方且与该些导电垫结构电连接；以及，多个导电凸块，设于重掺杂区下方，且经由重掺杂区与导电垫结构形成电连接。

Description

芯片封装体及其制造方法
技术领域
本发明涉及一种芯片封装体，特别是涉及一种晶片级芯片封装体及其制造方法。
背景技术
目前业界针对芯片的封装已发展出一种晶片级封装技术，在晶片级封装完成之后，再进行切割步骤，以分离形成芯片封装体。其中芯片封装体内的重布线路图案以和金属接垫直接接触为主，因此，在重布线路图案的制作工艺上，必须配合金属接垫的设计。
因此，业界亟需一种新颖的芯片封装体及其制作方法，以克服上述问题。
发明内容
为克服上述问题，本发明的实施例提供一种芯片封装体，包括：一半导体基板，具有相反的第一表面与第二表面，以及至少一接垫区与至少一元件区；多个导电垫结构，位于该半导体基板的第一表面，且位于该半导体基板的该接垫区上；
多个相互隔离的重掺杂区，设于该些导电垫结构下方，且与该些导电垫结构电连接；以及，多个导电凸块，设于该些重掺杂区下方，且经由该些重掺杂区与该些导电垫结构形成电连接。
本发明的实施例还提供一种芯片封装体的制造方法，包括：提供一半导体晶片，具有相反的第一表面与第二表面，该半导体晶片包括至少一接垫区与至少一元件区，以及多个导电垫结构，位于该第一表面的该接垫区上；形成多个相互隔离的重掺杂区于该些导电垫结构下方，其中该些重掺杂区和该些导电垫结构形成电连接；以及，形成多个导电凸块于该些重掺杂区的下方，其中该些导电凸块经由该些重掺杂区与该些导电垫结构形成电连接。
为让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举出较佳实施例，并配合所附附图，作详细说明如下：
附图说明
图1-图2为显示依据本发明的一实施例中，形成半导体芯片的制造方法的剖面示意图；
图3A-图3F为显示依据本发明的另一实施例中，形成承载基板的制造方法的剖面示意图；
图4-图5为显示依据本发明的另一实施例中，形成芯片封装体的制造方法的剖面示意图；
图6A-图6B为显示依据本发明的另一实施例中，形成芯片封装体的制造方法的剖面示意图；
图7A-图7D为显示依据本发明的另一实施例中，形成芯片封装体的制造方法的剖面示意图；
图8A-图8D为显示依据本发明的另一实施例中，形成芯片封装体的制造方法的剖面示意图。
主要元件符号说明
半导体晶片300；重掺杂区300B；绝缘层301；元件区100A；周边接垫区100B；半导体元件302；导电垫结构304；绝缘壁305；封装层500；间隔层310；空腔316；绝缘层320；重布线路图案330；保护层340；导电凸块350；承载晶片600；重掺杂区600B；绝缘层630；绝缘壁610；封装层500；保护层640；导电凸块650。
具体实施方式
以下以实施例并配合附图详细说明本发明，在附图或说明书描述中，相似或相同的部分使用相同的图号。且在附图中，实施例的形状或是厚度可扩大，以简化或是方便标示。再者，附图中各元件的部分将以描述说明之，值得注意的是，图中未绘示或描述的元件，为所属技术领域中具有通常知识者所知的形式。另外，特定的实施例仅为揭示本发明使用的特定方式，其并非用以限定本发明。
本发明以一制作CMOS影像感测芯片封装体为例，然而微机电芯片封装体(MEMSchippackage)或其他半导体芯片也可适用。亦即，可以了解的是，在本发明的芯片封装体的实施例中，其可应用于各种包含有源元件或无源元件(activeorpassiveelements)、数字电路或模拟电路(digitaloranalogcircuits)等集成电路的电子元件(electroniccomponents)，例如是有关于光电元件(optoelectronicdevices)、微机电系统(MicroElectroMechanicalSystem；MEMS)、微流体系统(microfluidicsystems)、或利用热、光线及压力等物理量变化来测量的物理感测器(PhysicalSensor)，或是CMOS影像感测器等。特别是可选择使用晶片级封装(waferscalepackage；WSP)制作工艺对影像感测元件、发光二极管(light-emittingdiodes；LEDs)、太阳能电池(solarcells)、射频元件(RFcircuits)、加速计(accelerators)、陀螺仪(gyroscopes)、微制动器(microactuators)、表面声波元件(surfaceacousticwavedevices)、压力感测器(processsensors)或喷墨头(inkprinterheads)等芯片进行封装。
其中上述晶片级封装制作工艺主要指在晶片阶段完成封装步骤后，再予以切割成独立的封装体，然而，在一特定实施例中，例如将已分离的半导体芯片重新分布在一承载晶片上，再进行封装制作工艺，也可称之为晶片级封装制作工艺。另外，上述晶片级封装制作工艺也适用于由堆叠(stack)方式安排具有集成电路的多片晶片，以形成多层集成电路(multi-layerintegratedcircuitdevices)的芯片封装体。
本发明的特征之一是通过重掺杂区达成导电垫结构与导电凸块之间的电连接，而不以重布线路图案与导电垫结构的直接接触为必要。在一实施例中，上述重掺杂区直接设置于导电垫结构下方的半导体基底。在另一实施例中，上述重掺杂区也可设置在一额外的承载基板中。
请参阅图1至图2，其显示依据本发明的一实施例，在半导体晶片上制作芯片封装体的制造方法的剖面示意图。在本实施例中重掺杂区设置于导电垫结构下方的半导体基底。如图1及图2所示，首先提供一半导体晶片300，一般为硅基板，其包括一绝缘层301，可通过热氧化或化学气相沉积法等半导体制作工艺形成，或者在一实施例中可采用一绝缘层上覆硅基板(SOI)，或者通过晶片接合制作工艺(waferbonding)结合两片晶片而成，其中一片晶片具有绝缘层。其次，半导体晶片定义有多个元件区100A，围绕元件区100A者为周边接垫区100B。接续，在半导体晶片300中形成连接至绝缘层301的绝缘壁305以隔离多个区域以作为重掺杂区300B。以及于元件区100A制作半导体元件302，例如影像感测器元件或是微机电结构，而覆盖上述半导体晶片300及半导体元件302者为层间介电层303(IMD)，一般可选择低介电系数(lowk)的绝缘材料，例如多孔性氧化层。接着于周边接垫区100B的层间介电层303中制作多个导电垫结构304。上述绝缘壁和绝缘层可以为绝缘材料例如一般的氧化硅，或是由绝缘空间构成，例如是气隙层或真空隔离层。上述导电垫结构304较佳可以由铜(copper；Cu)、铝(aluminum；Al)或其它合适的金属材料所制成。其中值得注意的是，上述半导体晶片于周边接垫区100B的位置包括多个重掺杂区300B，其电连接导电垫结构304并由绝缘壁305所隔离，重掺杂区300B可通过例如扩散或离子注入步骤，掺杂高浓度的离子如掺杂剂量为1E14～6E15atoms/cm2的磷或砷等形成，以构成一导电路径。在一实施例中，一个重掺杂区对应一个导电垫结构，然而，在多个导电垫结构作为共同输出的情形下，可由一个重掺杂区对应多个导电垫结构。
此外，半导体晶片300在晶片厂产出时一般覆盖有一芯片保护层306(passivationlayer)，同时为将芯片内的元件电连接至外部电路，传统上晶片厂会事先定义芯片保护层306以形成多个暴露出导电垫结构304的开口306h。
接着，如图3A所示，提供封装层500以与半导体晶片接合，其中为方便说明起见，上述半导体晶片300仅揭示导电垫结构304、绝缘壁305和绝缘层301。封装层500例如为玻璃等透明基板、另一空白硅晶片、或是另一含有集成电路元件的晶片。在一实施例中，可通过间隔层310分开封装层500与半导体基板，同时形成由间隔层310所围绕的空腔316。间隔层310可以为密封胶，或是感光绝缘材料，例如环氧树脂(epoxy)、阻焊材料(soldermask)等。此外间隔层310可先形成于半导体晶片300上，之后再通过粘着层与相对的封装层500接合，反之，也可将间隔层310先形成于封装层500上，之后再通过粘着层与相对的半导体晶片300接合。
请参阅图3B，可以封装层500为承载基板，自半导体晶片背面300a进行蚀刻，例如通过各向异性蚀刻制作工艺去除部分硅基板和绝缘层301，在半导体晶片300中形成暴露出重掺杂区300B的连通开口300h。值得注意的是，此些开口300h分别对应各周边接垫区100B中由绝缘壁305隔离的重掺杂区300B。
然后如图3C所示，在开口300h内形成露出重掺杂区300B的绝缘层320，例如可先通过热氧化法或等离子体化学气相沉积法，形成氧化硅层于开口300h内，其并可延伸至半导体晶片300的背面300a，接着，除去开口300h的底部上的绝缘层，例如通过光刻制作工艺定义开口300h的底部以暴露出重掺杂区300B。
接着，如图3D所示，在开口300h内形成导电图案330。在此实施例中，导电图案330作为重布线路图案，因此其除了形成于开口300h的侧壁上，还进一步延伸至半导体晶片下表面300a和重掺杂区300B上。重布线路图案330的形成方式可包括物理气相沉积、化学气相沉积、电镀、或无电镀等。重布线路图案330的材质可为金属材质，例如铜、铝、金、或前述的组合。重布线路图案330的材质还可包括导电氧化物，例如氧化铟锡(ITO)、氧化铟锌(IZO)、或前述的组合。在一实施例中，在整个半导体晶片300上顺应性形成一导电层，接着将导电层图案化为例如图3D所示的重布线路图案分布。
接续，请参阅图3E，其显示保护层340的形成方式。在本发明实施例中，保护层340例如为阻焊膜(soldermask)，可经由涂布防焊材料的方式于半导体晶片背面300a处形成保护层340。然后，对保护层340进行图案化制作工艺，以形成暴露部分重布线路图案330的多个终端接触开口。然后，在终端接触开口处形成焊球下金属层(UnderBumpMetallurgy，UBM)和导电凸块350。举例而言，由导电材料构成的焊球下金属层(UBM)可以是金属或金属合金，例如镍层、银层、铝层、铜层或其合金；或者是掺杂多晶硅、单晶硅、或导电玻璃层等材料。此外，耐火金属材料例如钛、钼、铬、或是钛钨层，也可单独或和其他金属层结合。而在一特定实施例中，镍/金层可以局部或全面性的形成于金属层表面。其中导电凸块350可通过重布线路图案330电连接重掺杂区300B，而非导电垫结构304。在本发明实施例中，导电凸块350用以传递元件302中的输入/输出(I/O)信号、接地(ground)信号或电源(power)信号。接着，沿着周边接垫区的切割线SC将半导体晶片分割，即可形成多个芯片封装体。
其中，在周边接垫区上的重掺杂区300B，由绝缘壁305隔离，因此重布线路图案330可直接和重掺杂区300B电性接触，而不以和导电垫结构304直接接触为必要。此外由于周边接垫区上的重掺杂区300B其区域范围可较导电垫结构为宽，因此开口300h可有较高的对准容许误差。
另如图3F所示，开口300h的深度可以超过绝缘层301，因此开口内的重布线路图案330可以深入重掺杂区300B中，或甚至抵达导电垫结构，以增加接触面积。亦即绝缘层301可位于该些开口300h的底部或其下方。
接下来，请参阅图4至图5，其显示依据本发明的另一实施例，在半导体晶片上制作芯片封装体的制造方法的剖面示意图。在本实施例中，重掺杂区设置于一承载基板中。如图4及图5所示，首先提供一半导体晶片，一般为硅晶片300，半导体晶片包括一上表面300a及一下表面300b。其次，半导体晶片定义有多个对应芯片的切割区和多个基板，每个基板包括至少一元件区100A，围绕元件区100A者为周边接垫区100B。接续，在上表面300a处的元件区100A制作半导体元件302，例如影像感测器元件或是微机电结构，而覆盖上述半导体晶片300及半导体元件302者为层间介电层303(IMD)，一般可选择低介电系数(lowk)的绝缘材料，例如多孔性氧化层。接着于周边接垫区100B的层间介电层303中制作多个导电垫结构304。上述导电垫结构304较佳可以由铜(copper；Cu)、铝(aluminum；Al)或其它合适的金属材料所制成。
此外，半导体晶片300在晶片厂产出时一般覆盖有一芯片保护层306(passivationlayer)，同时为将芯片内的元件电连接至外部电路，传统上晶片厂会事先定义芯片保护层306以形成多个暴露出导电垫结构304的开口306h。
接着，如图6A所示，提供一半导体晶片做为一承载基板，如空白或含有电路结构的硅晶片600，包括一上表面600a及一下表面600b。其次，自上表面600a处去除部分硅晶片600以形成多个开口600h。然后如图6B所示，填入绝缘层610于开口600h中，例如是高分子材料，如聚醯亚胺树脂(polyimide)。或者，通过半导体制作工艺形成绝缘材料如氧化硅层等，例如通过热氧化或是等离子体化学气相沉积法全面性形成氧化硅层，然后去除硅晶片600的上表面600a及/或下表面600b上的氧化硅层。其中值得注意的是，上述硅晶片600为重掺杂基板，可通过例如扩散或离子注入步骤，掺杂高浓度的离子如掺杂剂量为1E14～6E15atoms/cm2的磷或砷等形成，以构成一导电路径。在一实施例中，一个重掺杂区对应一个导电垫结构，然而，在多个导电垫结构作为共同输出的情形下，可由一个重掺杂区对应多个导电垫结构。
请参阅图7A，接着，将上述具有半导体元件的硅基板300接合至承载基板600上，举例而言，可将硅基板300翻转后由上表面300a接合至承载基板600的上表面600a上，使得半导体元件302远离承载基板600，而导电垫结构304则面向承载基板600的上表面600a接合。其中为方便说明起见，上述硅基板300仅揭示导电垫结构304、半导体元件302、和层间介电层303。
之后，请参阅图7B，通过例如是蚀刻(etching)、铣削(milling)、磨削(grinding)或研磨(polishing)的方式，从硅基板300的下表面300b处如虚线所示，薄化至一适当的厚度，以半导体元件为影像感测器为例，上述薄化后的硅基板300被薄化至一可允许足够的光通过的厚度，使得影像感测器元件302可感应此入射的光，进而产生信号，此时硅基板300的下表面300b作为入光面。
如图7C所示，在完成薄化步骤后，提供封装层500以与半导体晶片300的下表面300b接合。封装层500例如为玻璃等透明基板、另一空白硅晶片、或是另一含有集成电路元件的晶片。在一实施例中，可通过间隔层310分开封装层500与半导体基板，同时形成由间隔层310所围绕的空腔316。间隔层310可以为密封胶，或是感光绝缘材料，例如环氧树脂(epoxy)、阻焊材料(soldermask)等。此外间隔层310可先形成于硅基板的下表面300b上，之后再通过粘着层与相对的封装层500接合，反之，也可将间隔层310先形成于封装层500上，之后再通过粘着层与相对的硅基板下表面300b接合。
请参阅图7D，在一选择性(optional)步骤中，可以封装层500为承载基板，对另一承载基板的下表面600b实施一薄化步骤，例如以化学机械研磨制作工艺研磨承载基背面600b，以便于后续暴露出绝缘层610表面，此时，绝缘层610构成一绝缘壁，可分别隔离承载基板600中对应周边接垫区100B内的重掺杂区600B。
然后形成保护层640，在本发明实施例中，保护层640例如为阻焊膜(soldermask)，可经由涂布防焊材料的方式于承载基板的下表面600b处形成保护层640。然后，对保护层640进行图案化制作工艺，以形成暴露部分承载基板下表面600b的多个接触开口。然后，在接触开口处形成焊球下金属层(UnderBumpMetallurgy，UBM)和导电凸块650。举例而言，由导电材料构成的焊球下金属层(UBM)可以是金属或金属合金，例如镍层、银层、铝层、铜层或其合金；或者是掺杂多晶硅、单晶硅、或导电玻璃层等材料。此外，耐火金属材料例如钛、钼、铬、或是钛钨层，也可单独或和其他金属层结合。而在一特定实施例中，也可通过重布线路图案的形成，重新分布导电凸块650的位置。
在本发明实施例中，导电凸块650用以传递元件302中的输入/输出(I/O)信号、接地(ground)信号或电源(power)信号。接着，沿着周边接垫区的切割线SC将上述半导体晶片分割，即可形成多个芯片封装体。
其中，承载基板600于对应周边接垫区的重掺杂区600B，由绝缘壁610隔离，因此导电凸块650可直接或通过重布线路图案和重掺杂区600B电性接触，而不以和导电垫结构304直接接触为必要。此外由于承载基板600于对应周边接垫区的重掺杂区600B其区域范围可较导电垫结构为宽，因此接触开口可有较高的对准容许误差。
图8A至图8D显示依据本发明的另一实施例中，形成芯片封装体的制造方法的剖面示意图。其中与前述实施例的主要差异在于承载基板600为一绝缘层上覆硅基板(SOI)，其包括一绝缘层630。接续，在承载基板600中形成连接至绝缘层630的绝缘壁610以隔离承载基板中对应该些周边接垫区100B内的重掺杂区600B。上述绝缘壁和绝缘层一般可为氧化硅材料。其中重掺杂区600B可通过离子注入步骤完成，其可于绝缘壁610制作工艺之前或之后实施。然后如图8B所示，自半导体晶片300的背面处300b除去部分半导体晶片的厚度。接着如图8C-图8D所示，覆盖封装层500后，薄化承载基板600，并依序完成保护层640和导电凸块650的制作。然而在另一实施例中，在薄化承载基板600的过程中，绝缘层630也可保留，不必去除。在其他实施例中，上述绝缘层630，可通过热氧化或化学气相沉积法等半导体制作工艺形成，或者在一实施例中可通过晶片接合制作工艺(waferbonding)结合两片晶片而成，其中一片晶片具有绝缘层。
虽然结合以上数个较佳实施例揭露了本发明，然而其并非用以限定本发明，任何所属技术领域中熟悉此技术者，在不脱离本发明的精神和范围内，可作任意的更动与润饰，因此本发明的保护范围应以附上的权利要求所界定的为准。

Claims (11)

1.一种芯片封装体，包括：
半导体基板，具有相反的第一表面与第二表面，以及至少一元件区与围绕该至少一元件区的至少一接垫区；
多个导电垫结构，位于该半导体基板的第一表面，且位于该半导体基板的该接垫区上；
多个相互隔离的重掺杂区，设于该些导电垫结构下方，且与该些导电垫结构电连接，其中该些重掺杂区设置于该半导体基板中；
多个开口，由该半导体基板的第二表面深入该半导体基板中以暴露出该些重掺杂区；
导电图案，位于该些开口内并电性接触该些重掺杂区；以及
多个导电凸块，设于该些重掺杂区下方，且经由该些重掺杂区与该些导电垫结构形成电连接，
其中该些重掺杂区之间由一绝缘壁隔离，并且其中该导电图案深入该重掺杂区中，
其中每个所述开口仅暴露一个重掺杂区。
2.如权利要求1所述的芯片封装体，其中该些重掺杂区下方还包括一绝缘层，且该绝缘壁延伸至该绝缘层。
3.如权利要求1所述的芯片封装体，其中该重掺杂区宽于该导电垫结构。
4.如权利要求1所述的芯片封装体，其中该些开口内的导电图案与该半导体基板之间由一绝缘层所隔离。
5.如权利要求1所述的芯片封装体，还包括：
封装层，接合至该半导体基板；以及
间隔层，设置于该半导体基板与该封装层之间，且围绕该元件区形成一空腔。
6.一种芯片封装体的制造方法，包括：
提供一半导体晶片，具有相反的第一表面与第二表面，该半导体晶片包括至少一元件区与围绕该至少一元件区的至少一接垫区，以及多个导电垫结构，位于该第一表面的该接垫区上；
形成多个相互隔离的重掺杂区于该些导电垫结构下方，其中该些重掺杂区和该些导电垫结构形成电连接，该些重掺杂区形成于该半导体晶片中；
形成多个开口，由该半导体晶片的第二表面深入该半导体晶片中以暴露出该些重掺杂区；
形成一导电图案于该些开口内并电性接触该些重掺杂区；以及
形成多个导电凸块于该些重掺杂区的下方，其中该些导电凸块经由该些重掺杂区与该些导电垫结构形成电连接，
其中所述方法还包括于该些重掺杂区之间形成一绝缘壁而予以隔离，并且其中该导电图案深入该重掺杂区中，
其中每个所述开口仅暴露一个重掺杂区。
7.如权利要求6所述的芯片封装体的制造方法，还包括于该些重掺杂区下方形成一绝缘层，且该绝缘壁延伸至该绝缘层。
8.如权利要求6所述的芯片封装体的制造方法，其中该重掺杂区宽于该导电垫结构。
9.如权利要求6所述的芯片封装体的制造方法，还包括在该些开口内形成一绝缘层以隔离该导电图案与该半导体晶片。
10.如权利要求6所述的芯片封装体的制造方法，还包括：
将一封装层接合至该半导体晶片，且该封装层与该半导体晶片之间具有一间隔层所围绕的空腔。
11.如权利要求6所述的芯片封装体的制造方法，还包括切割该半导体晶片以形成多个芯片封装体。
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Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI473223B (zh) 2009-08-19 2015-02-11 Xintec Inc 晶片封裝體及其製造方法
TWI502705B (zh) * 2009-08-19 2015-10-01 Xintec Inc 晶片封裝體及其製造方法
TWI546910B (zh) * 2010-02-26 2016-08-21 精材科技股份有限公司 晶片封裝體及其製造方法
TWI485818B (zh) * 2011-06-16 2015-05-21 Xintec Inc 晶片封裝體及其形成方法
FR2985088B1 (fr) * 2011-12-23 2015-04-17 Commissariat Energie Atomique Via tsv dote d'une structure de liberation de contraintes et son procede de fabrication
US9548283B2 (en) * 2012-07-05 2017-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package redistribution layer structure and method of forming same
US9520380B2 (en) * 2012-09-01 2016-12-13 Alpha And Omega Semiconductor Incorporated Wafer process for molded chip scale package (MCSP) with thick backside metallization
US9379072B2 (en) * 2013-11-27 2016-06-28 Xintec Inc. Chip package and method for forming the same
TWI560829B (en) * 2014-03-07 2016-12-01 Xintec Inc Chip package and method thereof
CN105110286B (zh) * 2015-06-04 2017-10-03 美新半导体（无锡）有限公司 一种圆片级芯片尺寸封装的微电子机械系统及其制造方法
US9741620B2 (en) * 2015-06-24 2017-08-22 Invensas Corporation Structures and methods for reliable packages
US9564345B1 (en) * 2015-08-18 2017-02-07 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
KR102595276B1 (ko) * 2016-01-14 2023-10-31 삼성전자주식회사 반도체 패키지
JP2017204510A (ja) * 2016-05-09 2017-11-16 キヤノン株式会社 光電変換装置の製造方法
KR102525166B1 (ko) * 2017-11-14 2023-04-24 삼성전자주식회사 이미지 센서
US10340249B1 (en) * 2018-06-25 2019-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10707215B2 (en) * 2018-08-22 2020-07-07 Micron Technology, Inc. Methods of forming semiconductor devices, and related semiconductor devices, memory devices, and electronic systems
JP6871317B2 (ja) * 2019-07-26 2021-05-12 藤森工業株式会社 帯電防止表面保護フィルム
US11031462B1 (en) * 2019-12-23 2021-06-08 Nanya Technology Corporation Semiconductor structure with improved guard ring structure
US11309212B2 (en) * 2020-07-30 2022-04-19 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and methods of forming the same
JP7301178B2 (ja) * 2020-09-24 2023-06-30 藤森工業株式会社 帯電防止表面保護フィルム

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101236938A (zh) * 2007-02-01 2008-08-06 精材科技股份有限公司 芯片封装模块的散热方法及构造
CN101355043A (zh) * 2007-07-26 2009-01-28 精材科技股份有限公司 电子元件封装体及其制作方法

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5920108A (en) * 1995-06-05 1999-07-06 Harris Corporation Late process method and apparatus for trench isolation
US6300148B1 (en) * 1998-10-05 2001-10-09 Advanced Micro Devices Semiconductor structure with a backside protective layer and backside probes and a method for constructing the structure
US6710454B1 (en) * 2000-02-16 2004-03-23 Micron Technology, Inc. Adhesive layer for an electronic apparatus having multiple semiconductor devices
US6887753B2 (en) * 2001-02-28 2005-05-03 Micron Technology, Inc. Methods of forming semiconductor circuitry, and semiconductor circuit constructions
US7115973B1 (en) * 2001-03-08 2006-10-03 National Semiconductor Corporation Dual-sided semiconductor device with a resistive element that requires little silicon surface area
US6686627B2 (en) * 2001-12-26 2004-02-03 Sirenza Microdevices, Inc. Multiple conductive plug structure for lateral RF MOS devices
EP2560199B1 (en) * 2002-04-05 2016-08-03 STMicroelectronics S.r.l. Process for manufacturing a through insulated interconnection in a body of semiconductor material
DE60318570T2 (de) * 2002-04-26 2009-01-08 Kaneka Corp. Härtbare zusammensetzung, härtendes produkt, herstellungsverfahren dafür und mit dem gehärteten produkt versiegelte lichtemittierende diode
US6902872B2 (en) * 2002-07-29 2005-06-07 Hewlett-Packard Development Company, L.P. Method of forming a through-substrate interconnect
US6800930B2 (en) * 2002-07-31 2004-10-05 Micron Technology, Inc. Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies
SG111972A1 (en) * 2002-10-17 2005-06-29 Agency Science Tech & Res Wafer-level package for micro-electro-mechanical systems
JP3646720B2 (ja) * 2003-06-19 2005-05-11 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
US6987052B2 (en) * 2003-10-30 2006-01-17 Agere Systems Inc. Method for making enhanced substrate contact for a semiconductor device
US7498647B2 (en) * 2004-06-10 2009-03-03 Micron Technology, Inc. Packaged microelectronic imagers and methods of packaging microelectronic imagers
TWI244152B (en) * 2004-10-22 2005-11-21 Advanced Semiconductor Eng Bumping process and structure thereof
TWI278069B (en) * 2005-08-23 2007-04-01 Nanya Technology Corp Method of fabricating a trench capacitor having increased capacitance
US7491618B2 (en) * 2006-01-26 2009-02-17 International Business Machines Corporation Methods and semiconductor structures for latch-up suppression using a conductive region
KR100794658B1 (ko) * 2006-07-07 2008-01-14 삼성전자주식회사 반도체 칩 제조 방법, 이에 의해 형성된 반도체 칩 및 이를포함하는 칩 스택 패키지
US7816231B2 (en) * 2006-08-29 2010-10-19 International Business Machines Corporation Device structures including backside contacts, and methods for forming same
US20080157342A1 (en) 2007-01-03 2008-07-03 Advanced Chip Engineering Technology Inc. Package with a marking structure and method of the same
DE102007034306B3 (de) 2007-07-24 2009-04-02 Austriamicrosystems Ag Halbleitersubstrat mit Durchkontaktierung und Verfahren zur Herstellung eines Halbleitersubstrates mit Durchkontaktierung
EP2540776B1 (en) * 2007-09-25 2017-08-09 Hitachi Chemical Co., Ltd. Thermosetting light-reflecting resin composition, optical semiconductor element mounting board produced therewith, method for manufacture thereof, and optical semiconductor device
US8178976B2 (en) * 2008-05-12 2012-05-15 Texas Instruments Incorporated IC device having low resistance TSV comprising ground connection
TWI443790B (zh) * 2008-05-21 2014-07-01 Xintec Inc 電子元件封裝體及其製作方法
US8987014B2 (en) * 2008-05-21 2015-03-24 Stats Chippac, Ltd. Semiconductor wafer and method of forming sacrificial bump pad for wafer probing during wafer sort test
TWI508194B (zh) * 2009-01-06 2015-11-11 Xintec Inc 電子元件封裝體及其製作方法
SG175933A1 (en) * 2009-05-12 2011-12-29 Denki Kagaku Kogyo Kk Adhesive, adhesive sheet, and process for producing electronic components
US8067308B2 (en) * 2009-06-08 2011-11-29 Stats Chippac, Ltd. Semiconductor device and method of forming an interconnect structure with TSV using encapsulant for structural support
TWI473223B (zh) * 2009-08-19 2015-02-11 Xintec Inc 晶片封裝體及其製造方法
TWI502705B (zh) * 2009-08-19 2015-10-01 Xintec Inc 晶片封裝體及其製造方法
US8674518B2 (en) * 2011-01-03 2014-03-18 Shu-Ming Chang Chip package and method for forming the same
US8664540B2 (en) * 2011-05-27 2014-03-04 Taiwan Semiconductor Manufacturing Company, Ltd. Interposer testing using dummy connections

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101236938A (zh) * 2007-02-01 2008-08-06 精材科技股份有限公司 芯片封装模块的散热方法及构造
CN101355043A (zh) * 2007-07-26 2009-01-28 精材科技股份有限公司 电子元件封装体及其制作方法

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