CN102034796B - 晶片封装体及其制造方法 - Google Patents

晶片封装体及其制造方法 Download PDF

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CN102034796B
CN102034796B CN201010503607.3A CN201010503607A CN102034796B CN 102034796 B CN102034796 B CN 102034796B CN 201010503607 A CN201010503607 A CN 201010503607A CN 102034796 B CN102034796 B CN 102034796B
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conductive layer
pad structure
cutting area
conductive pad
wafer encapsulation
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CN102034796A (zh
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蔡佳伦
刘沧宇
郑家明
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XinTec Inc
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XinTec Inc
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    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides

Abstract

一种晶片封装体及其制造方法，该晶片封装体包括基板及残余切割区，基板具有一接垫区和一元件区，残余切割区位于基板周围；信号导电垫结构及EMI接地导电垫结构，设置于接垫区上；第一及第二开口，深入基板中以暴露出信号导电垫结构及EMI接地导电垫结构；第一及第二导电层，分别位于第一及第二开口内并分别电性接触信号导电垫结构及EMI接地导电垫结构；其中，第一导电层及信号导电垫结构与残余切割区的边缘相距一间隙，且第二导电层及/或EMI接地导电垫结构的一部分延伸至残余切割区的边缘；及第三导电层，其围绕残余切割区的周围，以与第二导电层及/或EMI接地导电垫结构电性连接。本发明能够较好地实现对电磁干扰的屏蔽。

Description

晶片封装体及其制造方法
技术领域
本发明有关于一种晶片封装体，特别有关于一种具有防电磁干扰(EMI)的屏蔽结构的晶片封装体及其制造方法。
背景技术
随着晶片封装体尺寸日益轻薄短小化及晶片的信号传递速度的日益增加，电磁干扰(electromagnetic interference，EMI)对于晶片封装体的影响也更趋严重。在晶片封装体持续缩小化的同时，要兼顾形成适合的防电磁干扰(EMI)的屏蔽结构更为不容易，例如常会遇到EMI接脚位置受限或制程过于繁琐昂贵等问题。
因此，业界亟需一种新颖的晶片封装体及其制作方法，以克服上述问题。
发明内容
本发明提供一种晶片封装体，包括半导体基板及残余切割区，半导体基板具有至少一接垫区和至少一元件区，残余切割区位于半导体基板周围；信号导电垫结构及EMI接地导电垫结构，设置于接垫区上；第一开口及第二开口，深入半导体基板中以暴露出信号导电垫结构及EMI接地导电垫结构；第一导电层及第二导电层，分别位于第一开口及第二开口内并分别电性接触信号导电垫结构及EMI接地导电垫结构；其中，第一导电层及信号导电垫结构与残余切割区的边缘相距一间隙，且第二导电层及/或EMI接地导电垫结构的一部分延伸至残余切割区的边缘；及第三导电层，其围绕残余切割区的周围，以与第二导电层及/或EMI接地导电垫结构电性连接。
本发明所述的晶片封装体，还包括一绝缘层，其介于该残余切割区与该第三导电层之间。
本发明所述的晶片封装体，该残余切割区呈一倾斜轮廓。
本发明所述的晶片封装体，该EMI接地导电垫结构包括多个金属层，并由其中一层金属层与该第二导电层电性接触。
本发明所述的晶片封装体，该EMI接地导电垫结构包括多个金属层，并由最下层金属层与该第二导电层电性接触。
本发明所述的晶片封装体，该EMI接地导电垫结构包括多个金属层，并由其中一层金属层延伸至该残余切割区的边缘以与该第三导电层电性接触。
本发明所述的晶片封装体，该半导体基板包括一第一表面及相反的第二表面，该信号导电垫结构及该EMI接地导电垫结构位于该第一表面侧，而该第一开口及该第二开口自该第二表面形成。
本发明所述的晶片封装体，该残余切割区呈一L型轮廓。
本发明所述的晶片封装体，该第一开口及该第二开口内的该第一导电层及该第二导电层与该半导体基板之间由一绝缘层所隔离。
此外，本发明还提供一种晶片封装体的制造方法，包括提供半导体基板，具有多个晶粒区和切割区，每一晶粒区包括至少一接垫区和至少一元件区，该切割区则包围晶粒区；于接垫区上形成信号导电垫结构及EMI接地导电垫结构；于晶粒区中形成第一开口及第二开口，以暴露出信号导电垫结构及EMI接地导电垫结构；于第一开口及第二开口内形成第一导电层及第二导电层，以分别电性接触信号导电垫结构及EMI接地导电垫结构，其中，第一导电层及信号导电垫结构与切割区的边缘相距一间隙，且第二导电层及/或EMI接地导电垫结构的一部分横跨切割区至另一晶粒区中；及沿切割区切割半导体基板以分离出多个晶片封装体，并于每个晶片封装体周围留下残余切割区，其中第一导电层及信号导电垫结构与残余切割区的边缘相距一间隙，且第二导电层及/或EMI接地导电垫结构的一部分延伸至残余切割区的边缘。
本发明所述的晶片封装体的制造方法，还包括于该预定切割区形成一凹口。
本发明所述的晶片封装体的制造方法，该绝缘层同时形成于该第一开口、该第二开口及该凹口内。
本发明所述的晶片封装体的制造方法，该凹口通过切割刀预切该预定切割区以形成一倾斜轮廓。
本发明所述的晶片封装体的制造方法，该凹口通过干蚀刻制程形成一垂直轮廓。
本发明所述的晶片封装体的制造方法，该半导体基板包括一第一表面及相反的第二表面，该信号导电垫结构及该EMI接地导电垫结构位于该第一表面侧，而该第一开口、该第二开口及该凹口自该第二表面形成。
本发明所述的晶片封装体的制造方法，还包括沿该预定切割区及该凹口切割该半导体基板以分离出多个晶片封装体，并于每个晶片封装体周围留下该残余切割区，其中该残余切割区周围由该绝缘层围绕。
本发明所述的晶片封装体的制造方法，还包括形成一第三导电层以围绕该残余切割区周围的绝缘层，并与该第二导电层及/或该EMI接地导电垫结构电性连接。
本发明能够较好地实现对电磁干扰的屏蔽。
附图说明
图1A-1H显示依据本发明的一实施例的晶片封装体的制程剖面图。
图2A-2C显示依据本发明的一实施例的晶片封装体的制程剖面图。
图3A-3C显示依据本发明的一实施例的晶片封装体的制程剖面图。
图4A-4B显示依据本发明的一实施例的晶片封装体的制程剖面图。
具体实施方式
为了让本发明之上述目的、特征及优点能更明显易懂，以下配合所附图式，作详细说明如下。
以下以实施例并配合图式详细说明本发明，在图式或说明书描述中，相似或相同的部分使用相同的图号。且在图式中，实施例的形状或是厚度可扩大，以简化或方便标示。再者，图式中各元件的部分将以描述说明，值得注意的是，图中未绘示或描述的元件，为本领域技术人员所知的形式。另外，特定的实施例仅为揭示本发明使用的特定方式，其并非用以限定本发明。
本发明以一制作CMOS影像感测晶片封装体为例，然而微机电晶片封装体(MEMS chip package)或其他半导体晶片亦可适用。亦即，可以了解的是，在本发明的晶片封装体的实施例中，其可应用于各种包含有源元件或无源元件(active or passiveelements)、数字电路或模拟电路(digital or analog circuits)等集成电路的电子元件(electronic components)，例如是有关于光电元件(opto electronic devices)、微机电系统(Micro ElectroMechanical System；MEMS)、微流体系统(micro fluidic systems)或利用热、光线及压力等物理量变化来测量的物理感测器(Physical Sensor)，或是CMOS影像感测器等。特别是可选择使用晶圆级封装(wafer scale package；WSP)制程对影像感测元件、发光二极管(light-emitting diodes；LEDs)、太阳能电池(solarcells)、射频元件(RF circuits)、加速计(accelerators)、陀螺仪(gyroscopes)、微制动器(micro actuators)、表面声波元件(surfaceacoustic wave devices)、压力感测器(process sensors)、喷墨头(ink printer heads)或功率晶片(power IC)等晶片进行封装。
其中上述晶圆级封装制程主要指在晶圆阶段完成封装步骤后，再予以切割成独立的封装体，然而，在一特定实施例中，例如将已分离的半导体晶片重新分布在一承载晶圆上，再进行封装制程，亦可称之为晶圆级封装制程。另外，上述晶圆级封装制程亦适用于通过堆叠(stack)方式安排具有集成电路的多片晶圆，以形成多层集成电路(multi-layer integrated circuit devices)的晶片封装体。
请参阅图1A至1H，其显示依据本发明一实施例的晶片封装体的制造方法剖面示意图。如图1A所示，首先提供一半导体基板300，一般为半导体晶圆(如硅晶圆)或硅基板。其次，半导体基板定义有多个元件区100A，围绕元件区100A者为周边接垫区100B。元件区100A及周边接垫区100B共同形成部分的晶粒区。
接续，如图1B所示，于元件区100A制作半导体元件302，例如影像感测器元件或是微机电结构，而覆盖上述半导体基板300及半导体元件302的为层间介电层303(IMD)，一般可选择低介电系数(low k)的绝缘材料，例如多孔性氧化层。接着于周边接垫区100B的层间介电层303中制作多个导电垫结构。在此实施例中，所形成的导电垫结构包括信号导电垫结构304a及EMI(electromagnetic interference)接地导电垫结构304b。上述导电垫结构较佳可以由铜(copper；Cu)、铝(aluminum；Al)或其它合适的金属材料所制成。
此外，半导体基板300可覆盖有一晶片保护层306(passivation layer)，同时为将晶片内的元件电性连接至外部电路，可事先定义晶片保护层306以形成多个暴露出导电垫结构的开口306h。
接着，如图1C所示，提供封装层500以与半导体基板接合，其中为方便说明起见，上述半导体基板300仅揭示导电垫结构304a及304b。封装层500例如为玻璃等透明基板、另一空白硅晶圆、另一硅基板或是另一含有集成电路元件的晶圆。在一实施例中，可通过间隔层310分开封装层500与半导体基板300，同时形成由间隔层310所围绕的间隙316。间隔层310可以为密封胶，或是感光绝缘材料，例如环氧树脂(epoxy)、阻焊材料(soldermask)等。此外间隔层310可先形成于半导体基板300上，之后再通过粘着层与相对的封装层500接合，反之，亦可将间隔层310先形成于封装层500上，之后再通过粘着层与相对的半导体基板300接合。
请参阅图1D，可以封装层500为承载基板，自半导体基板300的背面300a进行蚀刻，例如通过非等向性蚀刻制程去除部分的半导体基板300，以于其中形成分别暴露出信号导电垫结构304a及EMI接地导电垫结构304b的连通开口300ha及300hb。
图1E显示半导体基板300的较大范围的剖面图，除了图1D所示的部分晶粒区外，还包括相邻的切割区域以及另一晶粒区，切割区域一般包括预定的切割区SC2，而标号“SC1”则代表切割刀片将实际切除的区域。在此实施例中，EMI接地导电垫结构304b上方的间隔层310横跨预定切割区而延伸至另一周边接垫区的EMI接地导电垫结构304b上，然而，上述两晶粒区上之间隔层310亦可为两分离的不连续结构。此外，在图1E中，本领域技术人员当可了解切割区SC1的大小及位置可能随切割刀片的种类、尺寸及切割制程的差异而有所不同，不限于图1E所示的型式。预定切割区SC2通常较实际切割区SC1为宽，以于实际切除时预留一残余切割区SC3，避免切割时对半导体基板300中的元件造成伤害。
如图1E所示，于开口300ha及300hb内选择性形成露出信号导电垫结构304a及EMI接地导电垫结构304b的绝缘层320，例如可先通过热氧化法或等离子化学气相沉积法，同时形成氧化硅层于开口300ha及300hb内，其并可延伸至半导体基板300的背面300a，接着，除去开口300ha及300hb的底部上的绝缘层(例如通过微影制程)以暴露出信号导电垫结构304a及EMI接地导电垫结构304b。在此实施例中，开口300ha及300hb内的绝缘层320同时形成。此外，亦可视需求分次于开口300ha及300hb内形成绝缘层320，例如于露出EMI接地导电垫结构304b的开口300hb内形成厚度较厚的绝缘层。
接着，如图1F所示，于开口300ha及开口300hb中分别形成第一导电层330a及第二导电层330b。在此实施例中，如有必要，可以第一导电层为重布线路图案，因此其除了形成于开口300ha的侧壁上，还进一步延伸至半导体基板300的下表面300a上。然应注意的是，第一导电层330a不与第二导电层330b电性接触。此外，第一导电层330a至少需与实际切割区SC1的边缘需相距一间隙335，较佳者为与预定切割区SC2相距一间隙。
再者，在此实施例中，第二导电层330b亦可作为重布线路图案，因此其除了形成于开口300hb的侧壁上，还进一步延伸至半导体基板300的下表面300a上。此外，第二导电层330b进一步延伸跨越切割区SC2而至另一晶粒区中。如图1F所示，延伸于预定切割区的第二导电层以标号“330c”标示以方便辨识，其至少延伸至该残余切割区SC3与该实际切割区SC1的交接处。例如在本实施例中，第二导电层330b通过导电层330c而进一步与另一晶粒区的第二导电层300b相连。然应注意的是，本发明实施方式不限于此，在其他实施例中，第二导电层330b可能仅延伸跨越切割区SC2而到达另一晶粒区中，但不与另一晶粒区中的第二导电层330b电性接触。或者，在另一实施例中，第二导电层330b亦可仅延伸至实际切割区SC1之内，而不进一步延伸至相邻的另一晶粒区中。
第一导电层330a及第二导电层330b的形成方式可包括物理气相沉积、化学气相沉积、电镀或无电镀等，其材质可为金属材质，例如铜、铝、金或前述的组合。第一导电层330a及第二导电层330b的材质还可包括导电氧化物，例如氧化铟锡(ITO)、氧化铟锌(IZO)或前述的组合。在一实施例中，于整个半导体基板300上顺应性形成一导电层，接着将导电层图案化为例如图1F所示的导电图案分布。虽然，在图1E中的导电层顺应性形成于开口300ha及300hb的侧壁上，然在其他实施例中，导电层亦可大抵分别将开口300ha及300hb填满。此外，在此实施例中，开口300ha及300hb内的第一导电层330a及第二导电层330b与半导体基板300之间由同一绝缘层320所隔离。
接续，请参阅图1G，其显示保护层340的形成方式。在本发明实施例中，保护层340例如为阻焊膜(solder mask)，可经由涂布防焊材料的方式于半导体基板背面300a处形成保护层340。然后，对保护层340进行图案化制程，以形成暴露部分第一导电层330a及第二导电层330b的多个终端接触开口。然后，于终端接触开口处形成焊球下金属层(Under Bump Metallurgy，UBM)(未显示)和导电凸块350。举例而言，由导电材料构成的焊球下金属层(UBM)可以是金属或金属合金，例如镍层、银层、铝层、铜层或其合金；或者是掺杂多晶硅、单晶硅或导电玻璃层等材料。此外，耐火金属材料例如钛、钼、铬或是钛钨层，亦可单独或和其他金属层结合。而在一特定实施例中，镍/金层可以局部或全面性的形成于金属层表面。其中导电凸块350可通过第一导电层330a及第二导电层330b而分别电性连接至信号导电垫结构304a及EMI接地导电垫结构304b。在本发明实施例中，连接至信号导电垫结构304a的导电凸块350用以传递元件(未显示于图1G中，可参照图1B的元件302)中的输入/输出(I/O)信号。连接至EMI接地导电垫结构304b的导电凸块350用以接地(ground)。
接着，沿着周边接垫区的切割区SC1(即切割线)将半导体基板300分割，即可形成多个分离的晶片封装体。图1H显示其中一晶片封装体的剖面图。经切割后，晶片封装体的两侧保留有预定切割区SC2边缘与实际切割区SC1边缘之间的残余切割区SC3。
如图1H所示，在此实施例中，于分离出多个晶片封装体之后，可选择性形成围绕残余切割区SC3的周围的第三导电层330d。由于第一导电层330a及信号导电垫结构304a与实际切割区SC1或残余切割区SC3的边缘相距一间隙，因此所形成的第三导电层330d不会与第一导电层330a及信号导电垫结构304a电性接触而影响信号传递。
此外，由于导电层330c延伸跨越至切割区SC1或更进一步延伸至相邻的另一晶粒区，因此在晶片封装体经切割制程而彼此分离之后，导电层330c的一部分将于残余切割区SC3的边缘的表面上露出。因此，在形成第三导电层330d之后，第三导电层330d可通过所露出的导电层330c及第二导电层330b而与EMI接地导电垫结构304b电性连接。围绕晶片封装体的第三导电层330d有助于提供电磁干扰屏蔽。
在一实施例中，第三导电层330d可完全涂满于晶片封装体的周围。第三导电层330d的形成方式可通过任何的导电层形成制程及/或图案化制程。举例而言，可通过电镀制程而于晶片封装体的周围(即残余切割区SC3的周围)上形成第三导电层330d。或者，在另一实施例中，亦可先不形成导电凸块350及保护层340中的终端接触开口，并于第三导电层330d形成之后，才进行与形成导电凸块350的相关制程。
图2A-2C显示本发明另一实施例的晶片封装体的制程剖面图，其中相同或相似的元件将以相同或相似的标号标示。此外，部分相同或相似元件的材质或形成方法与图1A-1H所述实施例相同或相似，将不再重复叙述。
如图2A所示，此实施例与图1E所示结构相似，主要差异在于图2A-2C所述实施例的晶片封装体的切割步骤采用分段进行。如图2A所示，在形成绝缘层320之前，先于切割区SC2中的半导体基板300中形成凹口400。例如，可通过切割刀自半导体基板300的背面300a预切割此切割区SC2的一部分以形成具有一倾斜轮廓的凹口400。在另一实施例中，此凹口可伸入间隔层310至一既定深度，亦即，此时间隔层310的表层可作为切割刀的阻挡缓冲层。另外，切割刀预切的深度愈深，后续形成的导电层330c也愈接近间隔层而可完全包覆晶粒侧壁。接着，可于第一开口330ha、第二开口330hb及凹口400内同时形成绝缘层320，并将的图案化以如图2A所示露出信号导电垫结构304a及EMI接地导电垫结构304b。残余切割区SC3的周围由绝缘层320所围绕。
接着，如图2B所示，以类似于图1A-1H实施例所述的相似方式，分别于第一开口330ha、第二开口330hb及凹口400中形成第一导电层330a、第二导电层330b及延伸跨越切割区至相邻的另一晶粒区的导电层330c。在此实施例中，导电层330c顺应凹口400的轮廓而具有倾斜轮廓，并分别与左右两晶粒区的第二导电层330b电性接触。然如前所述，导电层330c至少仅需延伸至该残余切割区SC3与该实际切割区SC1的交接处即可，不以和另一晶粒区的导电层330c相连为必要。之后，可形成图案化保护层340以保护晶片封装体，并定义出终端接触开口。
如图2C所示，于预先定义出的终端接触开口中形成导电凸块350，并沿着切割线(即切割区SC1)切割半导体基板300以形成多个分离的晶片封装体。在此实施例中，延伸在残余切割区SC3的倾斜轮廓上的导电层330c围绕残余切割区SC3的边缘，可用作第三导电层以提供电磁干扰屏蔽。在此实施例中，第三导电层(即导电层330c)与第二导电层330b于同一道制程中形成，不需额外的形成步骤。此实施例的第三导电层(即导电层330c)围绕残余切割区SC3周围的绝缘层320。
图3A-3C显示本发明另一实施例的晶片封装体的制程剖面图，其中相同或相似的元件将以相同或相似的标号标示。此外，部分相同或相似元件的材质或形成方法与图2A-2C所述实施例相同或相似，将不再重复叙述。
图3A所示的结构相似于图2A，其差异主要在于此实施例不形成具倾斜轮廓的凹口400，而改以具有大抵垂直轮廓的凹口502取代。例如，可以干式蚀刻法自半导体基板300的背面300a移除部分的半导体基板300，因而形成具有垂直轮廓的凹口502。在一实施例中，凹口502、第一开口300ha及第二开口300hb可于同一道蚀刻制程中同时形成。或者，在其他实施例中，凹口502、第一开口300ha及第二开口300hb亦可视情况分次形成。接着，可于第一开口330ha、第二开口330hb及凹口502内同时形成绝缘层320，并将之图案化以如图3A所示露出信号导电垫结构304a及EMI接地导电垫结构304b。
接着，如图3B所示，以类似于图2A-2C实施例所述的相似方式，分别于第一开口330ha、第二开口330hb及凹口502中形成第一导电层330a、第二导电层330b及延伸跨越切割区至相邻的另一晶粒区的导电层330c。在此实施例中，导电层330c顺应凹口502的轮廓而具有垂直轮廓，并分别与左右两晶粒区的第二导电层330b电性接触。然在其他实施例中，导电层330c至少延伸至残余切割区SC3与实际切割区SC1的交接处即可，例如导电层330c仅延伸至实际切割区SC1的位置。之后，可形成图案化保护层340以保护晶片封装体，并定义出终端接触开口。
如图3C所示，于预先定义出的终端接触开口中形成导电凸块350，并沿着切割线(即切割区SC1)切割半导体基板300以形成多个分离的晶片封装体。在此实施例中，残余切割区SC3具有一L型轮廓。此外，延伸在残余切割区SC3的L型轮廓上的导电层330c围绕残余切割区SC3的边缘，可用作第三导电层以对提供电磁干扰屏蔽。在此实施例中，第三导电层(即导电层330c)与第二导电层330b于同一道制程中形成，不需额外的形成步骤。
图4A-4B显示本发明另一实施例的晶片封装体的制程剖面图，其中相同或相似的元件将以相同或相似的标号标示。此外，部分相同或相似元件的材质或形成方法与图1A-1H所述实施例相同或相似，将不再重复叙述。
图4A所示的结构与图1G相似，其差异主要在于图4A实施例的EMI接地导电垫结构304c至少延伸至残余切割区SC3与实际切割区SC1的交接处，例如延伸跨越预定切割区SC1而到达相邻的另一晶粒区中的周边接垫区。然而，在另一实施例中，EMI接地导电垫结构304c亦可仅延伸至实际切割区SC1的位置即可。
接着，如图4B所示，沿着切割线(即切割区SC1)切割半导体基板300以形成多个分离的晶片封装体。由于EMI接地导电垫结构304c延伸跨越切割区，因此在切割制程之后，EMI接地导电垫结构304c会于残余切割区SC3的一边缘的表面露出。
之后，形成围绕残余切割区SC3的周围的第三导电层330d。由于第一导电层330a及信号导电垫结构304a与残余切割区SC3的边缘相距一间隙，因此所形成的第三导电层330d不会与第一导电层330a及信号导电垫结构304a电性接触而影响信号传递。此外，在形成第三导电层330d之后，第三导电层330d可与所露出的导电层330c及EMI接地导电垫结构304c电性接触。围绕晶片封装体的第三导电层330d有助于提供电磁干扰屏蔽。虽然，在此实施例中，第三导电层330d同时与导电层330c及EMI接地导电垫结构304c电性接触，但第三导电层330d亦可仅与露出的EMI接地导电垫结构304c接触。
此外，在上述各实施例中，EMI接地导电垫结构可包括多个金属层(例如是图1B所示的情形)，并通过其中一层金属层而与第二导电层直接接触。例如，可通过多个金属层中的最下层金属层与第二导电层电性接触及/或直接接触。此外，在与图4A-4B所示的类似实施例中，EMI接地导电垫结构亦可包括多个金属层，并可由其中一层金属层延伸至残余切割区SC3的边缘以与第三导电层电性接触及/或直接接触。
通过本发明实施例所揭露的方法，可自由地于晶片封装体的底部布置电性连接至EMI接地导电垫结构的导电凸块，有助于提升晶片封装体设计上的自由度。此外，在部分实施例中，用作电磁遮蔽的导电层或导电图案可与用作信号传递的导电层或导电图案同时定义形成，可增加产能并减少制程时间与成本。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。
附图中符号的简单说明如下：
100A：元件区；100B：周边接垫区；300：半导体基板；300a：背面；300ha、300hb：开口；302：半导体元件；303：层间介电层；304a、304b、304c：导电垫结构；306：保护层；306h：开口；310：间隔层；316、335：间隙；320：绝缘层；330a、330b、330c、330d：导电层；340：保护层；350：导电凸块；400、502：凹口；500：封装层；SC1、SC2、SC3：切割区。

Claims (17)

1.一种晶片封装体，其特征在于，包括：
一半导体基板及一残余切割区，该半导体基板具有至少一接垫区和至少一元件区，该残余切割区位于该半导体基板周围；
一信号导电垫结构及一EMI接地导电垫结构，设置于该接垫区上；
一第一开口及一第二开口，深入该半导体基板中以暴露出该信号导电垫结构及该EMI接地导电垫结构；
一第一导电层及一第二导电层，分别位于该第一开口及该第二开口内并分别电性接触该信号导电垫结构及该EMI接地导电垫结构，且该第一导电层不与该第二导电层电性接触，其中，该第一导电层及该信号导电垫结构与该残余切割区的边缘相距一间隙，该间隙是绝缘的，且该第二导电层及/或该EMI接地导电垫结构的一部分延伸至该残余切割区的边缘；及
一第三导电层，其围绕该残余切割区的周围，以与该第二导电层及/或该EMI接地导电垫结构电性连接，其中，该第三导电层不与该第一导电层及该信号导电垫结构电性接触。
2.根据权利要求1所述的晶片封装体，其特征在于，还包括一绝缘层，其介于该残余切割区与该第三导电层之间。
3.根据权利要求1所述的晶片封装体，其特征在于，该残余切割区呈一倾斜轮廓。
4.根据权利要求1所述的晶片封装体，其特征在于，该EMI接地导电垫结构包括多个金属层，并由其中一层金属层与该第二导电层电性接触。
5.根据权利要求1所述的晶片封装体，其特征在于，该EMI接地导电垫结构包括多个金属层，并由最下层金属层与该第二导电层电性接触。
6.根据权利要求1所述的晶片封装体，其特征在于，该EMI接地导电垫结构包括多个金属层，并由其中一层金属层延伸至该残余切割区的边缘以与该第三导电层电性接触。
7.根据权利要求1所述的晶片封装体，其特征在于，该半导体基板包括一第一表面及相反的第二表面，该信号导电垫结构及该EMI接地导电垫结构位于该第一表面侧，而该第一开口及该第二开口自该第二表面形成。
8.根据权利要求1所述的晶片封装体，其特征在于，该残余切割区呈一L型轮廓。
9.根据权利要求1所述的晶片封装体，其特征在于，该第一开口及该第二开口内的该第一导电层及该第二导电层与该半导体基板之间由一绝缘层所隔离。
10.一种晶片封装体的制造方法，其特征在于，包括：
提供一半导体基板，具有多个晶粒区和预定切割区，每一晶粒区包括至少一接垫区和至少一元件区，该预定切割区则包围该晶粒区，其中该预定切割区内包括一实际切割区，该预定切割区与该实际切割区之间为一残余切割区；
于该接垫区上形成一信号导电垫结构及一EMI接地导电垫结构；
于该晶粒区中形成一第一开口及一第二开口，以暴露出该信号导电垫结构及该EMI接地导电垫结构；
于该第一开口及该第二开口内分别形成一第一导电层及一第二导电层，以分别电性接触该信号导电垫结构及该EMI接地导电垫结构，且该第一导电层不与该第二导电层电性接触，其中，该第一导电层及该信号导电垫结构与该预定切割区或残余切割区的边缘相距一间隙，该间隙是绝缘的，且该第二导电层及/或该EMI接地导电垫结构的一部分至少延伸至该残余切割区与该实际切割区的交接处；
沿该实际切割区切割该半导体基板以分离出多个晶片封装体，并于每个晶片封装体周围留下该残余切割区，其中该第二导电层及/或该EMI接地导电垫结构的一部分延伸至该残余切割区的边缘；及
形成一第三导电层以围绕该残余切割区周围，并与该第二导电层及/或该EMI接地导电垫结构电性连接，其中，该第三导电层不与该第一导电层及该信号导电垫结构电性接触。
11.根据权利要求10所述的晶片封装体的制造方法，其特征在于，还包括于该预定切割区形成一凹口。
12.根据权利要求11所述的晶片封装体的制造方法，其特征在于，还包括于该第一开口、该第二开口及该凹口内形成一绝缘层。
13.根据权利要求12所述的晶片封装体的制造方法，其特征在于，该凹口通过切割刀预切该预定切割区以形成一倾斜轮廓。
14.根据权利要求12所述的晶片封装体的制造方法，其特征在于，该凹口通过干蚀刻制程形成一垂直轮廓。
15.根据权利要求11所述的晶片封装体的制造方法，其特征在于，该半导体基板包括一第一表面及相反的第二表面，该信号导电垫结构及该EMI接地导电垫结构位于该第一表面侧，而该第一开口、该第二开口及该凹口自该第二表面形成。
16.根据权利要求12所述的晶片封装体的制造方法，其特征在于，还包括沿该预定切割区及该凹口切割该半导体基板以分离出多个晶片封装体，并于每个晶片封装体周围留下该残余切割区，其中该残余切割区周围由该绝缘层围绕。
17.根据权利要求16所述的晶片封装体的制造方法，其特征在于，该第三导电层围绕该残余切割区周围的绝缘层。
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