TWI508194B - 電子元件封裝體及其製作方法 - Google Patents

電子元件封裝體及其製作方法 Download PDF

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Publication number
TWI508194B
TWI508194B TW098145735A TW98145735A TWI508194B TW I508194 B TWI508194 B TW I508194B TW 098145735 A TW098145735 A TW 098145735A TW 98145735 A TW98145735 A TW 98145735A TW I508194 B TWI508194 B TW I508194B
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TW
Taiwan
Prior art keywords
wafer
electronic component
opening
component package
layer
Prior art date
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TW098145735A
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English (en)
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TW201027641A (en
Inventor
Chien Hung Liu
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Xintec Inc
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Publication of TW201027641A publication Critical patent/TW201027641A/zh
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Publication of TWI508194B publication Critical patent/TWI508194B/zh

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00325—Processes for packaging MEMS devices for reducing stress inside of the package structure
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00301—Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
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    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
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    • B81B2207/097—Interconnects arranged on the substrate or the lid, and covered by the package seal
    • B—PERFORMING OPERATIONS; TRANSPORTING
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Description

電子元件封裝體及其製作方法
本發明係有關於一種電子元件封裝體(electronics package)，特別是有關於一種利用晶圓級封裝(Wafer Level Package,WLP)製程製作的電子元件封裝體及其製作方法。
微機電結構MEMS(Micro Electro Mechanical Systems)是利用半導體製程技術，整合電子及機械功能製作而成的微型裝置，主要的產品類別大致可分為加速計、陀螺儀、壓力感測器、光通訊元件、DLP(數位光源處理)、噴墨頭，以及無線網路RF感測元件等，目前已逐漸應用在包括汽車胎壓量測、光通訊網路、投影機、感測網路、數位麥克風、時脈振盪器，以及包括遊戲機在內的各種產品之中。甚至在新一代記憶體技術、生物晶片、顯示技術、新興能源等先進研究方面，它也扮演了一個重要的角色。例如壓力感測器(pressure sensor)主要是在感知物體所處環境壓力的變化，部分汽車應用如油壓表等已相當成熟，新應用如胎壓監控等未來需求亦十分具有成長潛力，因此，亟需一種可用於上述微機電結構的封裝體及其製造方法。
有鑑於此，本發明之一實施例係提供一種電子元件封裝體的製作方法，包括提供一晶圓，其具有一上表面和一下表面，上述上表面上設有一導電電極；於上述晶圓的上述上表面覆蓋一蓋板；於上述晶圓的上述下表面覆蓋一保護層；於上述保護層上形成電性接觸上述導電電極之一導電凸塊；於上述蓋板上形成一開口結構；其中形成上述開口結構之步驟，係於上述晶圓的上述上表面覆蓋上述蓋板之前實施，或者於上述晶圓的上述下表面覆蓋上述保護層之後且於形成上述導電凸塊之前實施。
本發明之另一實施例係提供一種電子元件封裝體，包括一感測晶片，上述感測晶片的一上表面包括一感測薄膜；一具有開口結構之蓋板，覆蓋上述感測晶片的上述上表面，上述蓋板與上述感測晶片之間於對應上述感測薄膜位置上包括一連通上述開口結構之間隙；一間隔層，介於上述蓋板與上述感測晶片之間且圍繞著上述間隙，其中上述間隔層與上述感測薄膜水平方向之間包括一應力緩衝區。
以下以各實施例詳細說明並伴隨著圖式說明之範例，做為本發明之參考依據。在圖式或說明書描述中，相似或相同之部分皆使用相同之圖號。且在圖式中，實施例之形狀或是厚度可擴大，並以簡化或是方便標示。再者，圖式中各元件之部分將以分別描述說明之，值得注意的是，圖中未繪示或描述之元件，為所屬技術領域中具有通常知識者所知的形式，另外，特定之實施例僅為揭示本發明使用之特定方式，其並非用以限定本發明。
本發明係以製作電子元件封裝體，例如是壓力感測器(pressure sensor)的實施例作為說明。然而，可以了解的是，在本發明之封裝體實施例中，其可應用於各種包含主動元件或被動元件(active or passive elements)、數位電路或類比電路(digital or analog circuits)等積體電路的電子元件(electronic components)，例如是有關於光電元件(opto electronic devices)、微機電系統(Micro Electro Mechanical System;MEMS)、微流體系統(micro fluidic systems)、或利用熱、光線及壓力等物理量變化來測量的物理感測器(Physical Sensor)。特別是可選擇使用晶圓級封裝(Wafer Level Package,WLP)製程對影像感測元件(image sensors)、發光二極體、太陽能電池(solar cells)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力感測器(process sensors)或噴墨頭(ink printer heads)等半導體晶片進行封裝。
其中上述晶圓級封裝製程主要係指在晶圓階段完成封裝步驟後，再予以切割成獨立的封裝體，然而，在一特定實施例中，例如將已分離之半導體晶片重新分布在一承載晶圓上，再進行封裝製程，亦可稱之為晶圓級封裝製程。另外，上述晶圓級封裝製程亦適用於藉堆疊(stack)方式安排具有積體電路之多片晶圓，以形成多層積體電路(multi-layer integrated circuit devices)之電子元件封裝體。
第1A-1I圖顯示根據本發明之一實施例中，製作例如壓力感測器封裝體之電子元件封裝體500a的示意圖。如第1A圖所示，提供一晶圓(wafer)3，其具有一上表面20和一下表面30，其下表面30向內部形成有複數個凹洞(cavity)5，且係藉由一接合晶圓3的下表面30之承載基板1所密封。承載基板1可例如為玻璃基板，其厚度可介於300μm至500μm之間，較佳可為400μm。在本發明實施例中，上述晶圓3的材質可以是矽，或者是其它具有良好散熱能力或高傳導熱係數的基材，並藉由例如是濕蝕刻(wet etching)的方式，蝕刻此晶圓3，以形成上述凹洞5。上述晶圓3的厚度可介於100μm至200μm之間，較佳可為140μm。在本發明一實施例中，可採用黏著膠如環氧樹脂(epoxy)，用以接著晶圓3與承載基板1，但非必須採用環氧樹脂接著。在本發明一實施例中，晶圓3上可設有包括壓力感測晶片等多個微機電裝置，感測薄膜9係形成於晶圓3中並鄰近於晶圓3的上表面20，且覆蓋上述微機電裝置，感測薄膜9例如可為壓電材料，可用以感應外界環境或流體的變化，在感測薄膜9的周圍則包括導電電極或導電墊7。如第1A圖所示，導電電極7與感測薄膜9連接，用以傳導來自感測薄膜9的感測信號。在本發明另一實施例中，感測薄膜9亦可形成於晶圓3的上表面20上且與導電電極7相連接。而且矽晶圓3與導電電極7之間係藉由形成絕緣層予以隔離，例如，由氧化矽、氮氧化矽或低介電常數材料層組成，在此未予顯示。
如第1B圖所示，接著，在晶圓3的上表面20上還可以形成封裝層或蓋板13。在一實施例中，蓋板13與導電電極7之間可設置間隔層(spacer)11或支撐架(dam)，以在蓋板13與感測薄膜9之間形成間隙(cavity)15，而間隔層11則圍繞著間隙15。蓋板13可以是例如玻璃、石英(quartz)、蛋白石(opal)、塑膠等，在此係以矽基板為例，主要是用以在後續形成開口以供流體進出，其厚度可介於500μm至800μm之間，較佳可為700μm。間隔層11可例如為環氧樹脂(epoxy)等黏著材料，一般而言，間隔層11位於導電電極7上。
接著，可選擇進一步薄化承載基板1的步驟。例如從承載基板1的背面10予以薄化至一預定厚度，例如由400um研磨至120um。該薄化製程可以是蝕刻(etching)、銑削(milling)、磨削(grinding)或研磨(polishing)等方式。
其次，請參閱第1C圖，於預定切割道或導電電極7下方的位置形成一貫穿承載基板1並深入至部分晶圓3的一開口17，在一實施例中，可藉由刻痕裝置(notch equipment)實施一刻痕步驟，如以大致為60度角的切刀切開承載基板1及晶圓3而形成可視為通道凹口(channel notch)的開口17。
然後，如第1D圖所示，沿著開口17對晶圓3進行蝕刻以形成一底部較寬的開口19，例如對矽晶圓3實施矽蝕刻步驟以去除掉開口側壁及底部的晶圓材料，其中導電電極7與晶圓3之間的絕緣層在此步驟中可作為蝕刻停止層。
請參閱第1E圖，接著，於開口19的位置形成一由寬漸窄的開口21，例如使用刻痕裝置(notch equipment)實施一刻痕步驟以切割承載基板1，其中此刻痕裝置的切刀較寬或切角較大，例如選擇大於60度角的切刀，較佳者為選擇75度至80度角的切刀，因此所形成的開口21其上部(位於承載基板1內部的部分)較寬且傾斜角大於底部(位於晶圓3內部的部分)，有利於後續導線層的沈積，此外，開口21的上部(位於承載基板1內部的部分)及底部(位於晶圓3內部的部分)的側壁係連接在一起，因此，可避免後續填充如第1F圖所示之絕緣層23時產生孔洞。
請參閱第1F圖，於上述開口21中形成一絕緣層23。在一實施例中，上述絕緣層23形成於承載基板1下表面10，並填充至開口21中。上述絕緣層23較佳可以是環氧樹脂(epoxy)、防銲材料(solder mask)或其它適合之絕緣物質，例如無機材料之氧化矽層、氮化矽層、氮氧化矽層、金屬氧化物或其組合，或者是有機高分材料之聚醯亞胺樹脂(polyimide;PI)、苯環丁烯(butylcyclobutene;BCB)、聚對二甲苯(parylene)、萘聚合物(polynaphthalenes)、氟碳化物(fluorocarbons)、丙烯酸酯(accrylates)等的絕緣沈積層，且可以是利用塗佈方式，例如旋轉塗佈(spin coating)、噴塗(spray coating)或淋幕塗佈(curtain coating)，或者是其它適合之沈積方式，例如液相沈積(liquid phase deposition)、物理氣相沈積(physical vapor deposition;PVD)、化學氣相沈積(chemical vapor deposition;CVD)、低壓化學氣相沈積(low pressure chemical vapor deposition;LPCVD)、電漿增強式化學氣相沈積(plasma enhanced chemical vapor deposition;PECVD)、快速熱化學氣相沈積(rapid thermal-CVD;RTCVD)或常壓化學氣相沈積(atmospheric pressure chemical vapor deposition;APCVD)的方式形成
接著，請參閱第1G圖，形成深入間隔層11中且暴露導電電極7的開口25。例如藉由微影/蝕刻(photolithography/etching)步驟，圖案化此絕緣層23，介於導電電極7與晶圓3之間的絕緣層以及部分間隔層11，以形成深入間隔層11中且暴露導電電極7的開口25(未顯示)；或是藉由刻痕裝置實施一刻痕步驟以切開絕緣層23及導電電極7而深入至部分的間隔層11，以形成暴露電極7側邊的開口25。
然後，於開口25內側壁及底部上形成導線層27，且延伸至承載基板1下表面的部分絕緣層23上，其中，導線層27可與導電電極7電性接觸，在本例中為與導電電極7的側邊電性接觸；在另一實施例中，導線層27可與導電電極7的下表面電性接觸。導線層27一般可以是銅、鋁、銀、鎳或其合金的導電材料層，並利用例如是電鍍或濺鍍的方式，順應性地沈積於承載基板1的背面10上，並延伸至開口25的傾斜側面及底部。之後，進行一微影/蝕刻製程(photolithography/etching)，圖案化上述導電材料層，以形成導線層27。
其次，如第1H圖所示，於上述導線層27完成後，形成保護層(passivation layer)29於各導線層27上，覆蓋承載基板1的背面10及填滿開口25，保護層29例如為阻焊膜(solder mask)，在一實施例中，於形成上述保護層29後，可藉由圖案化此保護層29以形成暴露部分導線層27的開口31。
接著，請參閱第1I圖，在形成導電凸塊(conductive bump)33之前，於蓋板13中對應感測薄膜9的位置上形成連通至間隙15的開口35，其中此開口35可以是單一開口或是多孔結構以連通外在的流體，並薄化蓋板13。在一實施例中，感測薄膜9的面積係大於或等於開口35的總面積，較佳比例為介於1至1.5之間，如此可維持蓋板13的強度和保護的效果，同時不影響感測薄膜9偵測通過開口35的流體，其中當蓋板13由矽基板構成時，上述開口35可藉由乾蝕刻製程形成；此外為避免蓋板13透過間隔層11傳導應力而影響到感測薄膜9的偵測，此間隔層11與感測薄膜9水平方向之間可包括一應力緩衝區40，例如此間隔層11與感測薄膜9水平方向之間可相隔一既定間距40，例如100um以上，或者在間隔層11與感測薄膜9水平方向之間的矽晶圓3上可形成一或多個凹洞以阻隔應力，此凹洞中亦可考慮填入緩衝材料。最後，於開口31的位置形成導電凸塊(conductive bump)33以與導線層27電性連接。在一實施例中，可藉由電鍍或網版印刷(screen printing)的方式，將一銲料(solder)填入於上述開口31中，且進行一迴銲(re-flow)製程，以形成例如是銲球(solder ball)或銲墊(solder paste)的導電凸塊33。接著，沿切割道SC(scribe line)分割上述晶圓3，以分離出各壓力感測晶片，完成上述電子元件封裝體500a的製作。
在上述實施例中，蓋板13的開口35選擇於保護層29製程之後才暴露出來，因此可避免感測薄膜9遭受先前製程的汙染，而於導電凸塊33製程之前形成上述蓋板13的開口35，則可避免於製程中破壞導電凸塊結構33。
第2A-2E圖顯示根據本發明另一實施例之製作例如壓力感測器封裝體之電子元件封裝體500b的示意圖。如第2A圖所示，提供一晶圓(wafer)3，其具有一上表面20和一下表面30，其下表面30向內部形成有複數個凹洞(cavity)5，且係藉由一接合晶圓3下表面30之承載基板1所密封，承載基板1可例如為玻璃基板，其厚度可介於300μm至500μm之間，較佳可為400μm。上述晶圓3的材質可以是矽，或者是其它具有良好散熱能力或高傳導熱係數的基材，並藉由例如是濕蝕刻(wet etching)的方式，蝕刻此晶圓3，以形成上述凹洞5。上述晶圓3的厚度可介於100μm至200μm之間，較佳可為140μm。在一實施例中，黏著膠如環氧樹脂(epoxy)，可用來接著晶圓3與承載基板1。在本發明一實施例中，晶圓3上可設有包括壓力感測晶片等多個微機電裝置，在晶圓3的上表面20則覆蓋著一層感測薄膜9，例如壓電材料，可用以感應外界環境或流體的變化，在感測薄膜9的周圍則包括導電電極或導電墊7，用以傳導來自感測薄膜9的感測信號。而且矽晶圓3與導電電極7之間係藉由形成絕緣層予以隔離，例如，由氧化矽、氮氧化矽或低介電常數材料層組成，在此未予顯示。
如第2B圖所示，接著，在晶圓3的上表面20上還可以形成封裝層或蓋板53。在一實施例中，蓋板53與導電電極7之間可設置間隔層(spacer)11，以在蓋板53與感測薄膜9之間形成間隙(cavity)55，而間隔層11則圍繞著間隙15。蓋板53可以是例如玻璃、石英(quartz)、蛋白石(opal)、塑膠等，在此係以矽基板為例，主要是用以在後續形成開口以供流體進出，其厚度可介於200μm至400μm之間，較佳可為300μm。間隔層11可例如為環氧樹脂(epoxy)等黏著材料，一般而言，間隔層11位於導電電極7上。其中，上述蓋板53可先行製作開口65，並於蓋板53上表面先行貼上一層密封層67如膠帶並封住該開口65，之後再將此蓋板53附著於晶圓3之上表面上以連通間隙55與開口65，其中此開口65可以是單一開口或是多孔結構。
接著，可選擇進一步薄化承載基板1的步驟。例如從承載基板1的背面10予以薄化至一預定厚度，例如由400um研磨至120um。該薄化製程可以是蝕刻(etching)、銑削(milling)、磨削(grinding)或研磨(polishing)等方式。
其次，請參閱第2C圖，於預定切割道或導電電極7下方的位置形成一貫穿承載基板1並深入至晶圓3的開口17，在一實施例中可藉由刻痕裝置(notch equipment)實施一刻痕步驟，如以大致為60度角的切刀切開承載基板1及晶圓3而形成可視為通道凹口(channel notch)的開口17。然後，沿著開口17對晶圓3進行蝕刻以形成一底部較寬的開口19，例如對矽晶圓3實施矽蝕刻步驟以去除掉開口側壁及底部的晶圓材料，其中導電電極7與晶圓3之間的絕緣層在此步驟中可作為蝕刻停止層。
請參閱第2D圖，接著於開口19的位置形成一上部較寬的開口21，例如使用刻痕裝置(notch equipment)實施一刻痕步驟以切割承載基板1，其中此刻痕裝置的切刀較寬或切角較大，例如選擇大於60度角的切刀，較佳者為選擇75度至80度角的切刀，因此所形成的開口21其上部(位於承載基板1內部的部分)較寬且傾斜角大於底部(位於晶圓3內部的部分)，有利於後續導線的沈積，此外，開口21的上部(位於承載基板1內部的部分)及底部(位於晶圓3內部的部分)的側壁係連接在一起，因此，可避免後續填充絕緣層23時產生孔洞。接著，形成一絕緣層23於上述開口21中。在一實施例中，上述絕緣層23形成於承載基板1下表面10，並填充至開口21中。上述絕緣層23較佳可以是環氧樹脂(epoxy)、防銲材料(solder mask)或其它適合之絕緣物質，例如無機材料之氧化矽層、氮化矽層、氮氧化矽層、金屬氧化物或其組合，或者是有機高分材料之聚醯亞胺樹脂(polyimide;PI)、苯環丁烯(butylcyclobutene;BCB)、聚對二甲苯(parylene)、萘聚合物(polynaphthalenes)、氟碳化物(fluorocarbons)、丙烯酸酯(accrylates)等的絕緣沈積層，且可以是利用塗佈方式，例如旋轉塗佈(spin coating)、噴塗(spray coating)或淋幕塗佈(curtain coating)，或者是其它適合之沈積方式，例如液相沈積(liquid phase deposition)、物理氣相沈積(physical vapor deposition;PVD)、化學氣相沈積(chemical vapor deposition;CVD)、低壓化學氣相沈積(low pressure chemical vapor deposition;LPCVD)、電漿增強式化學氣相沈積(plasma enhanced chemical vapor deposition;PECVD)、快速熱化學氣相沈積(rapid thermal-CVD;RTCVD)或常壓化學氣相沈積(atmospheric pressure chemical vapor deposition;APCVD)的方式形成
接著，仍請參閱第2D圖，形成暴露導電電極7的開口25。例如藉由微影/蝕刻(photolithography/etching)步驟，圖案化此絕緣層23以及介於導電電極7與晶圓3之間的絕緣層，以形成暴露導電電極7的開口25(未顯示);或是藉由刻痕裝置實施一刻痕步驟以切開絕緣層23及導電電極7而深入至部分的間隔層11，以形成暴露導電電極7側邊的開口25。
然後，於開口25內側壁及底部上形成導線層27，且延伸至承載基板1下表面的絕緣層上，其中，導線層27可與導電電極7電性接觸，在本例中為與導電電極7的側邊電性接觸；在另一實施例中，導線層27可與導電電極7的下表面電性接觸。導線層27一般可以是銅、鋁、銀、鎳或其合金的導電材料層，並利用例如是電鍍或濺鍍的方式，順應性地沈積於承載基板1的背面10上，並延伸至開口25的傾斜側面及底部。之後，進行一微影/蝕刻製程(photolithography/etching)，圖案化上述導電材料層，以形成導線層27。
其次，如第2E圖所示，於上述導線層27完成後，形成保護層(passivation layer)29於各導線層27上，覆蓋承載基板1的背面10及填滿開口25，保護層29例如為阻焊膜(solder mask)，在一實施例中，於形成上述保護層29後，可藉由圖案化此保護層29以形成暴露部分導線層27的開口31。
接著，於開口31的位置形成導電凸塊(conductive bump)33以與導線層27電性連接。在一實施例中，可藉由電鍍或網版印刷(screen printing)的方式，將一銲料(solder)填入於上述開口31中，且進行一迴銲(re-flow)製程，以形成例如是銲球(solder ball)或銲墊(solder paste)的導電凸塊33。在形成導電凸塊(conductive bump)33之後，將膠帶67去除，以於蓋板13中對應感測薄膜9的位置上露出連通至間隙55的開口65，其中此開口可以是單一開口或是多孔結構以連通外在的流體。在一實施例中，感測薄膜9的面積係大於或等於開口65的總面積，較佳比例為介於1至1.5之間，如此可維持蓋板53的強度和保護的效果，同時不影響感測薄膜9偵測通過開口65的流體；此外為避免蓋板13透過間隔層11傳導應力而影響到感測薄膜9的偵測，此外為避免蓋板13透過間隔層11傳導應力而影響到感測薄膜9的偵測，此間隔層11與感測薄膜9水平方向之間可包括一應力緩衝區40，例如此間隔層11與感測薄膜水平方向之間可相隔一既定間距40，例如100um以上，或者在間隔層11與感測薄膜9水平方向之間的矽晶圓3上可形成一或多個凹洞以阻隔應力，此凹洞中亦可考慮填入緩衝材料。最後，將例如膠帶之密封層67撕開，沿切割道SC(scribe line)分割上述晶圓，以分離出各壓力感測晶片，完成上述電子元件封裝體500b。
在上述實施例中，由於蓋板53先行製作開口65且以例如膠帶之密封層67密封後，再附著於晶圓3上，因此可避免製造過程中對感測薄膜9的汙染。
由於上述實施例的電子元件封裝體500a或500b皆以晶圓級封裝製程製作，因此，電子元件封裝體具有相對較小的尺寸。此外，在電子元件封裝體中係使用導線層或導電凸塊電性連接晶片的電極，並非是接合導線(wire bond)，因此，也可縮小電子元件封裝體的尺寸。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定為準。
1．．．承載基板
3．．．晶圓
5．．．凹洞
7．．．導電電極
9．．．感測薄膜
10．．．背面
11．．．間隔層
13、53．．．蓋板
15；55．．．間隙
17、19、21、25、31、35、65．．．開口
20．．．上表面
23．．．絕緣層
27．．．導線層
29．．．保護層
30．．．下表面
33．．．導電凸塊
40．．．應力緩衝區
67．．．密封層
SC．．．切割道
500a、500b．．．電子元件封裝體
第1A-1I圖顯示製作一種根據本發明一實施例之電子元件封裝體的示意圖；及
第2A-2E圖顯示製作一種根據本發明另一實施例之電子元件封裝體的示意圖。
1．．．承載基板
3．．．晶圓
5．．．凹洞
7．．．導電電極
9．．．感測薄膜
11．．．間隔層
13．．．蓋板
15．．．間隙
35．．．開口
23．．．絕緣層
27．．．導線層
29．．．保護層
33．．．導電凸塊
40．．．應力緩衝區
SC．．．切割道
500a．．．電子元件封裝體

Claims (24)

  1. 一種電子元件封裝體的製作方法，包括：提供一晶圓，其具有一上表面和一下表面，該上表面上設有一導電電極；於該晶圓的該上表面覆蓋一蓋板；於該晶圓的該下表面覆蓋一保護層；於該保護層上形成電性接觸該導電電極之一導電凸塊；以及於該蓋板上形成一開口結構；其中形成該開口結構之步驟，係於該晶圓的該上表面覆蓋該蓋板之前實施，或者於該晶圓的該下表面覆蓋該保護層之後且於形成該導電凸塊之前實施。
  2. 如申請專利範圍第1項所述之電子元件封裝體的製作方法，其中該晶圓上設有多個微機電裝置。
  3. 如申請專利範圍第2項所述之電子元件封裝體的製作方法，其中該些微機電裝置包括壓力感測晶片，該上表面覆蓋一感測薄膜。
  4. 如申請專利範圍第3項所述之電子元件封裝體的製作方法，其中該感測薄膜與該蓋板之間包括一間隙，該間隙由一間隔層所圍繞，且該間隔層與該感測薄膜水平方向之間包括一應力緩衝區。
  5. 如申請專利範圍第4項所述之電子元件封裝體的製作方法，其中該間隔層位於該蓋板與該導電電極之間。
  6. 如申請專利範圍第4項所述之電子元件封裝體的製作方法，其中該間隔層與該感測薄膜相距一既定間距。
  7. 如申請專利範圍第1項所述之電子元件封裝體的製作方法，其中該開口結構包括單一開口或多孔結構。
  8. 如申請專利範圍第1項所述之電子元件封裝體的製作方法，其中該晶圓的該下表面向內部形成有複數個凹洞，且該些凹洞係藉由接合該晶圓的該下表面之一承載基板所密封。
  9. 如申請專利範圍第8項所述之電子元件封裝體的製作方法，於該晶圓的該上表面覆蓋該蓋板之後更包括對該承載基板的一背面進行一薄化製程，以薄化該承載基板至一預定厚度。
  10. 如申請專利範圍第9項所述之電子元件封裝體的製作方法，其中該薄化製程包括蝕刻(etching)、銑削(milling)、磨削(grinding)或研磨(polishing)。
  11. 如申請專利範圍第1項所述之電子元件封裝體的製作方法，於該晶圓的該下表面覆蓋該保護層之前更包括：從該晶圓的該下表面移除部分該晶圓，以於該導電電極下方的位置形成一第一開口；於該晶圓的該下表面和該第一開口中形成一絕緣層；移除部分該第一開口中的部分該絕緣層，以形成一第二開口，並暴露出該導電電極；以及於該第二開口的內側壁及底部上形成一導線層，且延伸至該晶圓的該下表面的部分該絕緣層上，其中該導線層係電性接觸該導電電極。
  12. 如申請專利範圍第11項所述之電子元件封裝體的製作方法，其中該保護層形成於該導線層上，且填入該第二開口。
  13. 如申請專利範圍第4項所述之電子元件封裝體的製作方法，其中該開口結構對應形成於該感測薄膜位置的正上方，且連通至該間隙。
  14. 如申請專利範圍第3項所述之電子元件封裝體的製作方法，其中該感測薄膜與該開口結構的面積比介於1至1.5之間。
  15. 一種電子元件封裝體，包括：一感測晶片，該感測晶片的一上表面包括一感測薄膜；一具有開口結構之蓋板，覆蓋該感測晶片的該上表面，該蓋板與該感測晶片之間於對應該感測薄膜位置上包括一連通該開口結構之間隙；以及一間隔層，介於該蓋板與該感測晶片之間且圍繞著該間隙，其中該間隔層與該感測薄膜水平方向之間包括一應力緩衝區，且位於該應力緩衝區的該晶片具有一或多個凹洞。
  16. 如申請專利範圍第15項所述之電子元件封裝體，其中該間隔層與該感測薄膜水平方向之間包括一應力緩衝區。
  17. 如申請專利範圍第15項所述之電子元件封裝體，更包括一導電電極，設置於該感測晶片的該上表面上，且介於該間隔層與該感測晶片之間。
  18. 如申請專利範圍第15項所述之電子元件封裝體，其中，該間隔層與該感測薄膜相距一既定間距。
  19. 如申請專利範圍第15項所述之電子元件封裝體，其中，該蓋板為一矽基板。
  20. 如申請專利範圍第16項所述之電子元件封裝體，其中，該開口結構包括單一開口或多孔結構。
  21. 如申請專利範圍第15項所述之電子元件封裝體，其中該感測晶片的該下表面向內部形成有複數個凹洞，且該些凹洞係藉由接合該感測晶片的該下表面之一承載基板所密封。
  22. 如申請專利範圍第17項所述之電子元件封裝體，更包括：一開口，從該感測晶片的該下表面深入至該晶圓，其中該開口的一底部係暴露出該導電電極；一絕緣層，形成於感測晶片的該下表面和該開口的一內側壁上；一導線層，形成於該開口的該內側壁及該底部上，且延伸至該感測晶片的該下表面的部分該絕緣層上，其中該導線層係電性接觸該導電電極；一保護層，覆蓋於感測晶片的該下表面；以及一導電凸塊，形成於該保護層上，且電性接觸該導電電極。
  23. 如申請專利範圍第22項所述之電子元件封裝體，其中該保護層形成於該導線層上，且填入該開口。
  24. 如申請專利範圍第15項所述之電子元件封裝 體，其中該感測薄膜與該開口結構的面積比介於1至1.5之間。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI606560B (zh) * 2016-06-16 2017-11-21 思鷺科技股份有限公司 封裝結構

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI579995B (zh) 2009-08-19 2017-04-21 Xintex Inc 晶片封裝體及其製造方法
TWI473223B (zh) 2009-08-19 2015-02-11 Xintec Inc 晶片封裝體及其製造方法
US8698316B2 (en) 2010-03-11 2014-04-15 Yu-Lin Yen Chip package
US8692382B2 (en) 2010-03-11 2014-04-08 Yu-Lin Yen Chip package
WO2012002446A1 (ja) * 2010-07-02 2012-01-05 独立行政法人産業技術総合研究所 微小機械システム
US8618620B2 (en) * 2010-07-13 2013-12-31 Infineon Technologies Ag Pressure sensor package systems and methods
CN102009378B (zh) * 2010-11-01 2012-01-11 天水七四九电子有限公司 电子器件特殊管基的启盖方法
KR101688006B1 (ko) * 2010-11-26 2016-12-20 삼성전자주식회사 반도체 장치
CN102593085B (zh) * 2011-01-10 2014-08-13 原相科技股份有限公司 芯片封装结构以及芯片封装制程
CN102730623B (zh) * 2011-04-06 2015-08-12 原相科技股份有限公司 微机电感测装置及其制作方法
TWI459529B (zh) * 2011-07-21 2014-11-01 Xintec Inc 晶片封裝體及其形成方法
US8866237B2 (en) 2012-02-27 2014-10-21 Texas Instruments Incorporated Methods for embedding controlled-cavity MEMS package in integration board
US20130307147A1 (en) * 2012-05-18 2013-11-21 Xintec Inc. Chip package and method for forming the same
TWI512930B (zh) * 2012-09-25 2015-12-11 Xintex Inc 晶片封裝體及其形成方法
US9733142B2 (en) * 2012-10-17 2017-08-15 Kabushiki Kaisha Saginomiya Seisakusho Pressure sensor, and sensor unit provided with same
CN102922961A (zh) * 2012-11-12 2013-02-13 西安交通大学 一种电容式微型胎压传感器
DE102013107862A1 (de) * 2013-07-23 2015-01-29 Osram Opto Semiconductors Gmbh Oberflächenmontierbares optoelektronisches Halbleiterbauteil und Verfahren zur Herstellung zumindest eines oberflächenmontierbaren optoelektronischen Halbleiterbauteils
US11033898B2 (en) * 2014-02-01 2021-06-15 Ezmems Ltd. Fluidic microelectromechanical sensors/devices and fabrication methods thereof
US10305019B1 (en) 2014-03-28 2019-05-28 Intel Corporation Piezoelectric devices fabricated in packaging build-up layers
US9704772B2 (en) 2014-04-02 2017-07-11 Xintec Inc. Chip package and method for forming the same
TWI569427B (zh) * 2014-10-22 2017-02-01 精材科技股份有限公司 半導體封裝件及其製法
KR20160090972A (ko) * 2015-01-22 2016-08-02 에스케이하이닉스 주식회사 이미지 센서 패키지 및 제조 방법
TWI588954B (zh) * 2015-02-16 2017-06-21 精材科技股份有限公司 晶片封裝體及其製造方法
TWI600125B (zh) * 2015-05-01 2017-09-21 精材科技股份有限公司 晶片封裝體及其製造方法
TWI624039B (zh) * 2015-05-28 2018-05-11 精材科技股份有限公司 晶片封裝體及其製造方法
JP6557776B2 (ja) * 2015-09-02 2019-08-07 蘇州晶方半導体科技股▲分▼有限公司Ｃｈｉｎａ Ｗａｆｅｒ Ｌｅｖｅｌ Ｃｓｐ Ｃｏ．， Ｌｔｄ． パッケージ構造およびパッケージング方法
US10672937B2 (en) * 2015-09-02 2020-06-02 Pixart Imaging Inc. Optical sensor module and sensor chip thereof
US10354114B2 (en) * 2016-06-13 2019-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Fingerprint sensor in InFO structure and formation method
CN107146799A (zh) * 2017-05-11 2017-09-08 北京工业大学 一种基于硅基板的影像芯片封装结构及其制作方法
WO2019023646A2 (en) 2017-07-27 2019-01-31 Maxim Integrated Products, Inc. ANALYTE SENSOR HOUSING AND METHOD FOR ANALYZING FLUID SAMPLES
CN109794855B (zh) * 2017-11-17 2020-09-11 长鑫存储技术有限公司 对作用于基底上的压力的测量方法
CN110627013A (zh) * 2018-06-22 2019-12-31 日月光半导体制造股份有限公司 电气装置及其制造方法
DE102020108775B4 (de) * 2020-03-30 2022-08-18 Infineon Technologies Ag Sensorpackages und verfahren zur herstellung von sensorpackages

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6383832B1 (en) * 2001-04-16 2002-05-07 Mitsubishi Denki Kabushiki Kaisha Pressure responsive device and method of manufacturing semiconductor substrate for use in pressure responsive device
US20090263927A1 (en) * 2007-01-04 2009-10-22 Visera Technologies Company Limited Isolation structures for cmos image sensor chip scale packages

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6278167B1 (en) * 1998-08-14 2001-08-21 Infineon Technologies Ag Semiconductor sensor with a base element and at least one deformation element
US6432737B1 (en) * 2001-01-03 2002-08-13 Amkor Technology, Inc. Method for forming a flip chip pressure sensor die package
DE102005053765B4 (de) * 2005-11-10 2016-04-14 Epcos Ag MEMS-Package und Verfahren zur Herstellung
GB0605576D0 (en) * 2006-03-20 2006-04-26 Oligon Ltd MEMS device
CN100423249C (zh) * 2006-10-17 2008-10-01 晶方半导体科技（苏州）有限公司 “n”形电连接晶圆级芯片尺寸封装结构及其制造方法
TWI315295B (en) 2006-12-29 2009-10-01 Advanced Semiconductor Eng Mems microphone module and method thereof
CN101236938A (zh) 2007-02-01 2008-08-06 精材科技股份有限公司 芯片封装模块的散热方法及构造
CN100552963C (zh) 2007-03-28 2009-10-21 精材科技股份有限公司 集成电路封装体及其制作方法
CN101123231B (zh) * 2007-08-31 2010-11-03 晶方半导体科技（苏州）有限公司 微机电系统的晶圆级芯片尺寸封装结构及其制造方法
CN101249936B (zh) 2008-04-10 2010-06-02 日月光半导体制造股份有限公司 微机电系统的封装构造及其制造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6383832B1 (en) * 2001-04-16 2002-05-07 Mitsubishi Denki Kabushiki Kaisha Pressure responsive device and method of manufacturing semiconductor substrate for use in pressure responsive device
US20090263927A1 (en) * 2007-01-04 2009-10-22 Visera Technologies Company Limited Isolation structures for cmos image sensor chip scale packages

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI606560B (zh) * 2016-06-16 2017-11-21 思鷺科技股份有限公司 封裝結構

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